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EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling 2007 H.K. Page 1

Midterm Exam Statistics

0

1

2

3

4

5

6

10 15 16 17 17.5 18

Grade

Max.=20

Number ofOccurrence

Mean=16

Standard Deviation: 2


EE247Lecture 18

ADC Converters Sampling (continued)

Sampling switch considerations

Switch induced distortion

Sampling switch conductance dependence on inputvoltage

Clock voltage boosters

Sampling switch charge injection & clock feedthrough

Complementary switch

Use of dummy device Bottom-plate switching

Track & hold circuits

T/H circuit incorporating gain & offset cancellation

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Summary of Last Lecture

DAC Converters (continued) Dynamic element matching

DAC reconstruction filter

ADC Converters Sampling (continued)

Sampling switch considerations

Thermal noise due to switch resistance

Sampling switch bandwidth limitations

Switch induced distortion Sampling switch conductance dependence on input

voltage


Practical SamplingSummary So Far!

2

2

212

B

B

FS

C k TV

( )1 forinON o o ox DD thDD th

WVg g g C V V

V V L

= =

0.72

s

RB f C

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Switch On-ResistanceSwitch MOS operating in triode mode:

Vin

C

M1

1VDD( ) ( )

( )( )

0

1,

2

1 1

is a function of results in distortion

What if instead of connecting G to a fixed voltage,

DS

D triodeDSD triode ox GS TH DS

ON DS V

ON

ox GS th ox DD th in

ON in

dIW VI C V V V

L R dV

RW W

C V V C V V V L L

R V

=

= =

a floating and fixed voltage source is connected to G & S?

Desirable to maximize on voltage of GS Minimize ONR


Boosted & Constant VGS Sampling

VGS=const.

OFF ON

Increase gate overdrive voltage as

much as possible + keep VGSconstant

Switch overdrive voltage

independent of signal level Error due to finite RON linear (to

1st order)

Lower Ron lower time constant

Higher frequency of operation

Gate voltage VGS =low

Device off

Beware of signal

feedthrough due to parasiticcapacitors

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Constant VGS Sampling

(= voltage @ the switch input terminal)


Constant VGS Sampling Circuit

VP1

100ns

M12

M8

M9

M6

M11Vin

1.5V1MHz

Chold

P

C1 C2

M1 M2

VDD=3V

M3

C3

M5

M4

P

This Example: All device sizes:10/0.35All capacitor size: 1pF (except for Chold)

Note: Each critical switch requires a separate clock booster

Vg

Va Vb

Sampling switch & C

PB

Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC

May 1999, pp. 599.

PB

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Clock Voltage Doubler Operation

C1 C2

M10ff

M2Saturation

mode

VP1

=clock

PB

VDD=03V

P

a) Startup

03V

03V 00

03V 0(3V-VthM2)Acquire

charge C1 C2

M1Triode

M2off

VP1

PB

VDD=3V

P

3V0

3V0

3V03V (3V-VthM2) (6V-VthM2)

b) Next clock transition

03V

VP1


Clock Voltage Doubler Operation

C1 C2

M10ff

M2

VP1

PB

VDD=3V

P

03V

03V

3V ~6V

3V0

c) Next clock phase

(6V-VthM2) (3V-Vth

M2) ~ 3V

M2Triode

Acquires

charge

Both C1 & C2

charged to

VDD after one

clock cycle

Note that

bottom plate

of C1 & C2 is

either 0 or

VDD while top

plates are atVDD or 2VDD

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Clock Voltage DoublerSimulation

C1 C2

M1 M2

VP1Clock period: 100ns

PB

P_Boost

VDD

2VDD

0

VDD=3V

R1 R2

*R1 & R2=1GOhmdummy resistors added for simulation only

P


Constant VGS Sampler: Low

Sampling switch M11

is OFF

C3 charged to ~VDDInput voltage

source

M3Triode

C3

M12

Triode

M4

OFF

VS11.5V1MHz

Chold

1pF

~ 2 VDD

(boosted clock)

VDD

VDD

OFF M11OFF

DeviceOFF

VDD=3V

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Constant VGS Sampler: High

C3 previously

charged to VDD

M8 & M9 are on:

C3 across G-S of M11

M11 on with constant

VGS = VDD

C31pF

M8

M9 M11

VS11.5V1MHz

Chold

1pF

VDD


Constant VGS SamplingSimulation

Input Switch VGate

Input Signal

Chold Signal

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Boosted Clock SamplingComplete Circuit

Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC

May 1999, pp. 599.

Clock Multiplier

Switch

M7 & M13 for

reliability

Remaining issues:

-VGS constant only

for Vin

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Advanced Clock Boosting Technique

clk low Capacitors C1a & C1b charged to VDD

MS off Hold mode

Sampling

Switch

clk low



Sampling

Switch

clk

high Top plate of C1a & C1b connected to gate of sampling switch Bottom plate of C1a connected to VIN Bottom plate of C1b connected to VOUT VGS & VGD of MS both @ VDD & ac signal on G of MS average of VIN &

VOUT

clk high

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Gate tracks average of input and output, reduces effect of IR drop athigh frequencies

Bulk also tracks signal reduced body effect (technology used allowsconnecting bulk to S) Reported measured SFDR = 76.5dB at fin=200MHz

Ref: M. Waltari et al., "Aself-calibrated pipeline

ADC with 200MHz IF-sampling frontend,"ISSCC 2002, Dig.Tech. Papers, pp. 314

Sampling

Switch


Constant Conductance Switch

Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dBSFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000

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OFF




ON

M2 Constant current

constant gds

M1 replica of M2

& same VGS

as M2

M1 also

constant gds

Note: Authors report requirement

of 280MHz GBW for the opamp for

12bit 50Ms/s ADC

Also, opamp common-modecompliance for full input range

required

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Switch Off-Mode Feedthrough Cancellation

Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend,"ISSCC 2002, Dig. Techn. Papers, pp. 314


Practical Sampling

Vo

C

M1

1

Rsw = f(Vi) distortion

Switch charge injection & clock feedthrough

Vi

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Sampling Switch Charge InjectionSwitching from Track to Hold

Vi VO

Cs

M1

VG

First assume Vi is a DC voltage When switch turns off offset voltage (V) induced on Cs Why?

VG

t

VH

Vi

VL

Vi +Vth

VO

Vi

toff

V

t


SamplingSwitch Charge Injection

Channel distributed RC network formed between G,S, and D

Channel to substrate junction capacitance distributed & voltage dependant

Drain/Source junction capacitors to substrate or well voltage dependant

Over-lap capacitance Cov =LDxWx Cox associated with G-S & G-D overlap

MOS xtor operating in triode region

Cross section view

Distributed channel resistance &

gate & junction capacitances

S

G

D

B

LD

L

Cov Cov

Cjdb

Cjsb

CHOLD

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Switch Charge InjectionSlow Clock

Slow clock clock fall time >> device speed During the period (t- to toff) current in channel discharges channel

charge acquired during the previous clock cycle into low

impedance signal source

Only source of error Clock feedthrough from Cov toCs

VG

t

VH

Vi

VL

Vi +Vth

tofft-

Device still

conducting


Switch Clock FeedthroughSlow ClockVG

t

VH

Vi

VL

Vi +Vth

VO

Vi

toff

V

t

D

Cov

VG

( )

( )

( ) ( )

( )

( )

ovi th L

ov s

ovi th L

s

o i

ov ov ovo i i th L i th L

s s s

o i os

ov ovos th L

s s

CV V V V

C C

CV V V

CV V V

C C CV V V V V V 1 V V C C C

V V 1 V

C Cwhere ; V V V

C C

= + +

+

= +

= + =

= + +

= =

t-

Cs

VO

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Switch Charge Injection & Clock FeedthroughSlow Clock- Example

( )

' 2ov ox th L

ov

s

ovos th L

s

C 0.1 fF / C 9 fF / V 0.4V V 0

C 1 0 x0 .1 fF / .1 %

C 1pF Al lo wi ng 1/ 2L SB AD C re so lu ti on ~ 9bi t

CV V V 0.4mV C

= = = =

= = =

= Wn preferable)

11B

1

1B

VG

t

VH

Vi

VL

1 1B


Switch Charge InjectionComplementary Switch

Fast Clock

In fast clock case

To 1st order, offset due to overlap caps

cancelled for equal device width

Input voltage dependant error worse!

1

1B

VG

t

VH

Vi

VL

( )

( )

( )

ch n n ox n H i th n

th pch p p ox p i L

ch pch no

s s

o i os

n ox n p ox p

s

Q W C L V V V

VQ W C L V V

Q1 QV

2 C C

V V 1 V

1 W C L W C L

2 C

=

=

= + +

+

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Switch Charge InjectionDummy Switch

Vi

VO

Cs

t

VH

Vi

VL

VG VGB

WM2=1/2WM1

VG VGB

M1 M2

M1 M11 ch ov

M 2 M 22 c h ov

2 M1 2 1

1Q Q Q

2Q Q 2Q

1For W W Q Q

2

+

+

= =

Q1 Q2



Vi

VO

Cs

t

VH

Vi

VL

VG VGB

Dummy switch same L as main switch but half W

Main device clock goes low, dummy device gate goes high dummy

switch acquires same amount of channel charge main switch needs tolose

Effective only if exactly half of the charge stored in M1 is transferred to M2

(depends on input/output node impedance) and requires good matching

between clock fall/rise

WM2=1/2WM1

VG VGB

M1 M2

Q1 Q2

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Vi VOM1

VG

M2

VGB

To guarantee half of charge goes to each side create the same

environment on both sides

Add capacitor equal to sampling capacitor to the other side of the switch

+ add fixed resistor to emulate input resistance of following circuit

Issues: Degrades sampling bandwidth

CsCs

R

WM2=1/2WM1


Dummy Switch Effectiveness Test

Ref: L. A. Bienstman et al, An Eight-Channel 8 13it Microprocessor Compatible NMOS D/A

Converter with Programmable Scaling, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980

Dummy switch

W=1/2Wmain

As Vin is

increased Vc1-Vin

is decreased

channel charge

decreased less

charge injection

Note large Ls

good devicearea matching

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Switch Charge InjectionDifferential Sampling

Vi+

VO+

Vi-

VO-

To 1st order, offset terms cancel

Note gain error still about the same Has the advantage of better immunity to

noise coupling and cancellation of evenorder harmonics

Cs

Cs

( )

( )

( )( )

o o od i i id

o o i ioc ic

o i 1 os1

o i 2 os2

1 2od i d id 1 2 ic os1 os2

V V V V V V

V V V V V V

2 2V V 1 V

V V 1 V

V V V V V V 2

+ +

+ +

+ +

= =

+ += =

= + +

= + +

+= + + +


Avoiding Switch Charge InjectionBottom Plate Sampling

Switches M2 opened slightly earlier compared to M1

Injected charge by the opening of M2 is constant since its DS voltageis zero & eliminated when used differentially

Since Cs bottom plate is already open when M1 is opened

No charge injected on Cs

1aVH

VL

t

1bViVO

M1

1b

1a M2Cs

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Flip-Around Track & Hold

vIN

vOUT

C

S1A

1D

S2

2

S2A

2

S3

1D

1 S1vCM

Concept based on bottom-

plate sampling

1

21D


Flip-Around T/H-Basic Operation1high

vIN vOUT

C

S1A

1D

S2

2

S2A

2

S3

1D

1 S1vCM

Charging C

11D2

Note: Opamp has to be

stable in unity-gain

configuration

Q1

=VIN

xC

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Flip-Around T/H-Basic Operation

2high

vINvOUT

C

S1A

1D

S2

2

S2A

2

S3

1D

1 S1vCM

Holding

1

21D

Q2=VOUTxCVOUT=VIN


Flip-Around T/H - Timing

S1 opens earlier than S1A

No resistive path from Cbottom plate to Gnd charge

can not change

"Bottom Plate Sampling"

vIN

vOUT

C

S1A

1D

S2

2

S2A

2

S3

1D

1S1

vCM

1

21D

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Charge Injection

At the instant of transitioning from track to hold

mode, some of the charge stored in sampling

switch S1 is dumped onto C

With "Bottom Plate Sampling", only charge

injection component due to opening of S1 and

is to first-order independent of vIN Only a dc offset is added. This dc offset can be

removed with a differential architecture


Flip-Around T/H

vIN vOUT

C

S1A

1D

S2

2

S2A

2

S3

1D

1 S1vCM

Constant switch VGSto minimize distortion

Note: Among all switches

only S1A & S2A

experience full

input voltage swing

1

21D

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Flip-Around T/H S1 is chosen to be an n-channel MOSFET

Since it always switches the same voltage, its on-resistance, RS1, is signal-independent (to first order)

Choosing RS1 >> RS1A minimizes the non-linearcomponent of R = RS1A+ RS1 Typically, S1A is a wide (much lower resistance than S1) &

constant VGS switch

In practice size of S1A is limited by the (nonlinear) S/Dcapacitance that also adds distortion

If S1As resistance is negligible delay depends only on S1resistance

S1 resistance is independent of VIN error due to finitetime-constant independent of VIN


Differential Flip-Around T/H

Ref: W. Yang, et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input, IEEE

JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931

Offset voltage associated with charge injection of S11 & S12 cancelled by differential

nature of the circuit

During input sampling phase amp outputs shorted together

S11

S12

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Differential Flip-Around T/H

Gain=1 Feedback factor=1

112


Differential Flip-Around T/HIssues: Input Common-Mode Range

Vin-cm=Vout_com-Vsig_com Amplifier needs to have large input common-mode compliance

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Differential Flip-Around T/HIssues: Input Common-Mode Range

Vin-cm=Vout_com-Vsig_com

Amplifier needs to have large input common-mode compliance


Input Common-ModeCancellation

Ref: R. Yen, et al. A MOS Switched-Capacitor Instrumentation Amplifier, IEEE JOURNAL OF

SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008

Note: Shorting switch M3 added

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Input Common-Mode Cancellation

Track mode ( high)VC1=VI1 , VC2=VI2Vo1=Vo2=0

Hold mode ( low)Vo1+Vo2 =0

Vo1-Vo2= -(VI1-VI2)(C1/(C1+C3))

Input common-mode level removed


T/H + Charge Redistribution Amplifier

Track mode: (S1, S3 on S2 off)

VC1=VosVIN , VC2=0

Vo=Vos

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T/H + Charge Redistribution AmplifierHold Mode

Hold/amplify mode (S1, S3 off S2 on)

Offset NOT cancelled, but not amplified Input-referred offset =(C2/C1) x VOS, & often C2

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