L12: 6.111 Spring 2008 1 Introductory Digital Systems Laboratory L12: Reconfigurable Logic Architectures L12: Reconfigurable Logic Architectures Acknowledgements: ¾ Lecture material adapted from R. Katz, G. Borriello, “Contemporary Logic Design” (second edition), Copyright 2005 Prentice-Hall/Pearson Education. ¾ Frank Honore ¾Lecture Notes prepared by Professor Anantha Chandrakasan
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L12: 6.111 Spring 2008 1Introductory Digital Systems Laboratory
e.g. TTL packages: Data Book for 100’s of different parts
Gate Arrays (IBM 1970s)Transistors are pre-placed on the chip & Place and Route software puts the chip together automatically – only program the interconnect (mask programming)
Software Based Schemes (1970’s- present)Run instructions on a general purpose core
Programmable Logic (1980’s to present)A chip that be reprogrammed after it has been fabricatedExamples: PALs, EPROM, EEPROM, PLDs, FPGAsExcellent support for mapping from Verilog
ASIC Design (1980’s to present)Turn Verilog directly into layout using a library of standard cells Effective for high-volume and efficient use of silicon area
L12: 6.111 Spring 2008 3Introductory Digital Systems Laboratory
InterconnectWires to connect inputs andoutputs to logic blocks
I/O blocksSpecial logic blocks at periphery of device forexternal connections
Key questions:How to make logic blocks programmable?(after chip has been fabbed!)What should the logic granularity be?How to make the wires programmable?(after chip has been fabbed!)Specialized wiring structures for localvs. long distance routes?How many wires per logic block?
LogicLogic
Configuration
Inputs Outputsn m
Q
QSET
CLR
D
L12: 6.111 Spring 2008 4Introductory Digital Systems Laboratory
Based on the fact that any combinational logic can be realized as a sum-of-productsPALs feature an array of AND-OR gates with programmable interconnect
input signals
output signals
programming of product terms
programming of sum terms
AND array OR array
L12: 6.111 Spring 2008 5Introductory Digital Systems Laboratory
Inside the 22v10 PALInside the 22v10 PAL
Each input pin (and its complement) sent to the AND arrayOR gates for each output can take 8-16 product terms, depending on output pin“Macrocell” block provides additional output flexibility...
L12: 6.111 Spring 2008 6Introductory Digital Systems Laboratory
Cypress PAL CE22V10Cypress PAL CE22V10
Combinational/active low
Combinational/active high
Outputs may be registered or combinational, positive or inverted
From Lattice SemiconductorFrom Cypress
L12: 6.111 Spring 2008 7Introductory Digital Systems Laboratory
RAM Based Field Programmable RAM Based Field Programmable Logic Logic -- XilinxXilinx
CLB
CLB
CLB
CLB
SwitchMatrix
ProgrammableInterconnect I/O Blocks (IOBs)
ConfigurableLogic Blocks (CLBs)
D Q
SlewRate
Control
PassivePull-Up,
Pull-Down
Delay
Vcc
OutputBuffer
InputBuffer
Q D
Pad
D QSD
RDEC
S/RControl
D QSD
RDEC
S/RControl
1
1
F'G'
H'
DIN
F'G'
H'
DIN
F'
G'H'
H'
HFunc.Gen.
GFunc.Gen.
FFunc.Gen.
G4G3G2G1
F4F3F2F1
C4C1 C2 C3
K
Y
X
H1 DIN S/R EC
L12: 6.111 Spring 2008 8Introductory Digital Systems Laboratory
The Xilinx 4000 CLBThe Xilinx 4000 CLB
L12: 6.111 Spring 2008 9Introductory Digital Systems Laboratory
Two 4Two 4--input Functions, Registered Outputinput Functions, Registered Output and a Two Input Functionand a Two Input Function
L12: 6.111 Spring 2008 10Introductory Digital Systems Laboratory
L12: 6.111 Spring 2008 11Introductory Digital Systems Laboratory
LUT MappingLUT Mapping
N-LUT direct implementation of a truth table: any function of n-inputs.N-LUT requires 2N storage elements (latches)N-inputs select one latch location (like a memory)
4LUT example
Latches set by configuration bitstream
Inputs
Output
Why Latches and Not Registers?
L12: 6.111 Spring 2008 12Introductory Digital Systems Laboratory
Configuring the CLB as a RAMConfiguring the CLB as a RAM
Memory is built using Latches not FFs
Read is same a LUT Function!
16x2
L12: 6.111 Spring 2008 13Introductory Digital Systems Laboratory
Xilinx 4000 InterconnectXilinx 4000 Interconnect
L12: 6.111 Spring 2008 14Introductory Digital Systems Laboratory
L12: 6.111 Spring 2008 26Introductory Digital Systems Laboratory
How are How are FPGAsFPGAs Used?Used?
(courtesy of IKOS)FPGA-based Emulator
Logic EmulationPrototyping
Ensemble of gate arrays used to emulate a circuit to be manufacturedGet more/better/faster debugging done than with simulation
Reconfigurable hardwareOne hardware block used to implement more than one function
Special-purpose computation engines
Hardware dedicated to solving one problem (or class of problems)Accelerators attached to general-purpose computers (e.g., in a cell phone!)
L12: 6.111 Spring 2008 27Introductory Digital Systems Laboratory
SummarySummary
FPGA provide a flexible platform for implementing digital computingA rich set of macros and I/Os supported (multipliers, block RAMS, ROMS, high-speed I/O)A wide range of applications from prototyping (to validate a design before ASIC mapping) to high-performance spatial computingInterconnects are a major bottleneck (physical design and locality are important considerations)
“College students will study concurrent programming instead of “C” as their first