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L10: 6.111 Spring 2006 1Introductory Digital Systems
Laboratory
L10: Analog Building BlocksL10: Analog Building Blocks
((OpAmpsOpAmps, A/D, D/A), A/D, D/A)
Acknowledgement:Materials in this lecture are courtesy of the
following sources and are used with permission.
Dave Wentzloff
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L10: 6.111 Spring 2006 2Introductory Digital Systems
Laboratory
Introduction to Operational AmplifiersIntroduction to
Operational Amplifiers
Typically very high input resistance ~ 300KHigh DC gain
(~105)Output resistance ~75
DC Model
LM741 Pinout
inout VfaV = )(
a(f)
f10Hz
105 -20dB/decade
+10 to +15V
-10 to -15V
idva idv
inR outR+
outv
Reprinted with permission of National Semiconductor
Corporation.
Reprinted with permission of National Semiconductor
Corporation.
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L10: 6.111 Spring 2006 3Introductory Digital Systems
Laboratory
The Inside of a 741 The Inside of a 741
OpAmpOpAmpDifferentialInput Stage
AdditionalGain Stage Output Stage
Current Source for biasing
Bipolar versionhas small inputBias current
MOS OpAmpshave ~ 0 input current
Gain is Sensitive to Operating Condition (e.g., Device,
Temperature, Power supply voltage, etc.)
Output devicesprovides large
drive current
Reprinted with permission of National Semiconductor
Corporation.
Reprinted with permission of National Semiconductor
Corporation.
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L10: 6.111 Spring 2006 4Introductory Digital Systems
Laboratory
Simple Model for an Simple Model for an OpAmpOpAmp
+
-
i+ ~ 0
i- ~ 0+-
+-
vidvout
vout
vid
VCC = 10V
-VCC = -10V
= 100V
-100V
Reasonable approximation
+
-vid +- avid
+
-vout
Linear Mode
If -VCC < vout < VCC
+
-vid -VCC
+
-vout
Negative Saturation
vid < -
-++
-vid
+
-vout
Positive Saturation
vid >
-+ +VCC
-VCC
VCC
Small input range for Open loop Configuration
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L10: 6.111 Spring 2006 5Introductory Digital Systems
Laboratory
The Power of (Negative) FeedbackThe Power of (Negative)
Feedback
inv outv
1R 2R
-+
-
+vid +- avid
+
-voutinv
R2
-+
R1
021
=+
++
Rvv
Rvv idoutidin
avv outid =
++=
2211
11RR
aRa
vRv outin
( ) ( )11 12
21
2 >>++
= aifRR
RRaaR
vv
in
out
Overall (closed loop) gain does not depend on open loop
gainTrade gain for robustnessEasier analysis approach: virtual
short circuit approach
v+ = v- = 0 if OpAmp is linear
+-
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L10: 6.111 Spring 2006 6Introductory Digital Systems
Laboratory
Basic Basic OpAmpOpAmp CircuitsCircuits
+
Voltage Follower (buffer) Non-inverting
Differential Input
invoutv
inout vv
Integrator
+
-
inout vRRRv
1
21 +
( )121
2ininR
Rout vvv dtvv
t
inRCout
1
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L10: 6.111 Spring 2006 7Introductory Digital Systems
Laboratory
Use With Open LoopUse With Open Loop
Analog Comparator:
Is V+ > V- ?The Output is a DIGITAL signal
LM311 is a single supplycomparator
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L10: 6.111 Spring 2006 8Introductory Digital Systems
Laboratory
Data Conversion: Quantization NoiseData Conversion: Quantization
Noise
Quantization noise exists even with ideal A/D and D/A converters
inv
noisev
LSB
A/D D/A
digitalcode
inv
Quantizationnoise
+
00 01 10 1104refV
2refV4
3 refV
Binary code
Ana
log
Out
put
00
01
10
11
04refV
2refV
43 refV
Analog Input
Bin
ary
Ou t
put
refV
4refV
2refV
43 refV
refV
A/D Conversion D/A Conversion
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L10: 6.111 Spring 2006 9Introductory Digital Systems
Laboratory
NonNon--idealities in Data Conversionidealities in Data
Conversion
Binary code
Ana
log
Ideal
Offseterror
Binary code
Ana
log
Ideal
Gainerror
Offset a constant voltage offset that appears at the output when
the digital input is 0
Gain error deviation of slope from ideal value of 1
Binary code
Ana
log
Ideal
Integralnonlinearity
Integral Nonlinearity maximum deviation from the ideal analog
output voltage
Differential nonlinearity the largest increment in analog output
for a 1-bit change
Binary code
Ana
log Ideal
Non-monoticity
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L10: 6.111 Spring 2006 10Introductory Digital Systems
Laboratory
RR--2R Ladder DAC Architecture2R Ladder DAC Architecture
Note that the driving point impedance (resistance) is the same
for each cell.R-2R Ladder achieves large current division ratios
with only two resistor values
-1
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L10: 6.111 Spring 2006 Introductory Digital Systems Laboratory
11
8-bit DACSingle Supply Operation: 5V to 15VIntegrates required
references (bandgap voltage reference)Uses a R-2R resistor ladder
Settling time 1sProgrammable output range from0V to 2.56V or 0V to
10VSimple Latch based interface
Image courtesy of Analog Devices. Used with permission.
DAC (AD 558) SpecsDAC (AD 558) Specs
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L10: 6.111 Spring 2006 12Introductory Digital Systems
Laboratory
Chip Architecture and InterfaceChip Architecture and
Interface
CE CS
LATCHD[7:0]
Outputs are noisy when input bits settles, so it is best to have
inputs stable before latching the input data
Image courtesy of Analog Devices. Used with permission.
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L10: 6.111 Spring 2006 13Introductory Digital Systems
Laboratory
Setting the Voltage RangeSetting the Voltage Range
Very similar to anon-inverting amp
Strap output fordifferent voltageranges
Convert data to Offset binary
Image courtesy of Analog Devices. Used with permission.
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L10: 6.111 Spring 2006 14Introductory Digital Systems
Laboratory
Another Approach: BinaryAnother Approach: Binary--Weighted
DACWeighted DAC
Analog Devices AD9768 uses two banks of ratioed
currentsAdditional current division performed by 750 resistor
between the two banks
Switch binary-weighted currentsMSB to LSB current ratio is
2N
AD9768
3b 2b 1b 0b
R
outv
( )08
114
122
13 bbbbIRvout +++=
+-
I2I
I4
I8
Reference current sourceImage courtesy of Analog Devices. Used
with permission.
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L10: 6.111 Spring 2006 15Introductory Digital Systems
Laboratory
GlitchingGlitching and Thermometer D/Aand Thermometer D/A
Glitching is caused when switching times in a D/A are not
synchronizedExample: Output changes from 011 to 100 MSB switch is
delayedFiltering reduces glitch but increases the D/A settling
timeOne solution is a thermometer code D/A requires 2N 1 switches
but no ratioedcurrents
100011outv
t
Binary Thermometer0 0 0 0 00 1 0 0 11 0 0 1 11 1 1 1 1
0TI
R
outv
( )210 TTTIRvout ++=
I I1T 2T
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L10: 6.111 Spring 2006 16Introductory Digital Systems
Laboratory
SuccessiveSuccessive--Approximation A/DApproximation A/D
Example: 3-bit A/D conversion, 2 LSB < Vin < 3 LSB
D/A converters are typically compact and easier to design. Why
not A/D convert using a D/A converter and a comparator?
D to A generates analog voltage which is compared to the input
voltageIf D to A voltage > input voltage then set that bit;
otherwise, reset that bitThis type of A to D takes a fixed amount
of time proportional to the bit length
Vin code
D/A
Comparatorout
C+
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L10: 6.111 Spring 2006 17Introductory Digital Systems
Laboratory
SuccessiveSuccessive--Approximation A/DApproximation A/D
Serial conversion takes a time equal to N(tD/A + tcomp)
SuccessiveApproximation
Generator
Control
Done
Go
-
+Sample/Hold
D/AConverter
vin
N
Data
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L10: 6.111 Spring 2006 18Introductory Digital Systems
Laboratory
SuccessiveSuccessive--Approximation A/D Approximation A/D
(AD670)(AD670)
~10s conversion time
Unipolar (BPO =0)
Bipolar (BPO =1)
Image courtesy of Analog Devices. Used with permission.
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L10: 6.111 Spring 2006 19Introductory Digital Systems
Laboratory
Single Write, Single Read OperationSingle Write, Single Read
Operation(see data sheet for other modes)(see data sheet for other
modes)
R/W
CE, CS
Data Data Valid
tw
Valid
tDC
tw (write/start pulse width) = 300ns (min)tDC (delay to start
conversion) = 700ns (max)tc (conversion time) = 10s (max)tTD (Bus
Access Time) = 250 (max)tDT (Output Float Delay) = 150 (max)
tc tTDtDT
Write
Read
Control bits CE and CS can be wired to ground if A/D is the only
chip driving the busSuggestion: tie CE and CS pins together and
hardwire BPO and Format
Status
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L10: 6.111 Spring 2006 20Introductory Digital Systems
Laboratory
Simple A/D Interface FSMSimple A/D Interface FSM
Data[7:0]
STATUS
CS
CE
AD670
cs_b
R/W r_w_b
FSM
clk
reset
sample
DQ
dataavail
status
Status should be synchronized: why?
Courtesy of James Oey and Cemal Akcaba Figure by MIT
OpenCourseWare.
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L10: 6.111 Spring 2006 21Introductory Digital Systems
Laboratory
2/5
Example A/D Example A/D VerilogVerilog InterfaceInterface
module AD670 (clk, reset, sample, dataavail, r_wbar, cs_bar,
status, state);
// System Clkinput clk; // Global Reset signal, assume it is
synchronized
input reset;
// User Interface input sample; output dataavail;
// A-D Interfaceinput status;reg status_d1, status_d2;output
r_wbar, cs_bar;output [3:0] state;
// internal state reg [3:0] state;reg [3:0] nextstate;reg
r_wbar_int, r_wbar;reg cs_bar_int, cs_bar;reg dataavail; 1/5
// State declarations.parameter IDLE = 0;parameter CONV0 =
1;parameter CONV1 = 2;parameter CONV2 = 3;parameter WAITSTATUSHIGH
= 4;parameter WAITSTATUSLOW = 5;parameter READDELAY0 = 6;parameter
READDELAY1 = 7;parameter READCYCLE = 8;
always @ (posedge clk or negedge reset) begin
if (!reset) state
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L10: 6.111 Spring 2006 22Introductory Digital Systems
Laboratory
3/5
Example A/D Example A/D VerilogVerilog Interface
(cont.)Interface (cont.)
always @ (state or status_d2 or sample) begin//
defaultsr_wbar_int = 1; cs_bar_int = 1; dataavail = 0;
case (state)
IDLE: beginif(sample) nextstate = CONV0;else nextstate =
IDLE;end
CONV0:begin
r_wbar_int = 0; cs_bar_int = 0; nextstate = CONV1;
end
CONV1:begin
r_wbar_int = 0; cs_bar_int = 0; nextstate = CONV2;
end
CONV2:begin
r_wbar_int = 0; cs_bar_int = 0; nextstate = WAITSTATUSHIGH;
end WAITSTATUSHIGH:begin
cs_bar_int = 0; if (status_d2) nextstate = WAITSTATUSLOW;
else nextstate = WAITSTATUSHIGH;end
WAITSTATUSLOW:begin
cs_bar_int = 0; if (!status_d2) nextstate = READDELAY0;else
nextstate = WAITSTATUSLOW;
end
4/5
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L10: 6.111 Spring 2006 23Introductory Digital Systems
Laboratory
Example A/D Example A/D VerilogVerilog
Interface(contInterface(cont.).)
READDELAY0:begin
cs_bar_int = 0; nextstate = READDELAY1;
end
READDELAY1:begin
cs_bar_int = 0; nextstate = READCYCLE;
end
READCYCLE:begin
cs_bar_int = 0; dataavail = 1;nextstate = IDLE;
end
default: nextstate = IDLE;endcase // case(state)
end // always @ (state or status_d2 or sample)endmodule //
adcInterface
5/5
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L10: 6.111 Spring 2006 24Introductory Digital Systems
Laboratory
SimulationSimulationOn reset, present state goes to 0
Sample pulse initiates data conversion
Notice a one cycle delay since A/D control signal delayed
through a register
r_w_b must stay low for at least 3 cycles (@ 100ns period)
Status is synchronized two register delays
Wait for ~10s for status to go low
Enable read flip-flop
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L10: 6.111 Spring 2006 25Introductory Digital Systems
Laboratory
Flash A/D ConverterFlash A/D Converter
Brute-force A/D conversionSimultaneously compare the analog
value with every possible reference valueFastest method of A/D
conversionSize scales exponentially with precision(requires 2N
comparators)
C+
C+
C+
R
R
refV inv
0b
1b
The
r mom
eter
t ob i
n ar y
ComparatorsR
R
Can be implemented as OpAmp in open loop
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L10: 6.111 Spring 2006 26Introductory Digital Systems
Laboratory
AD 775 AD 775 Flash Data ConverterFlash Data Converter
Image courtesy of Analog Devices. Used with permission.
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L10: 6.111 Spring 2006 27Introductory Digital Systems
Laboratory
Amplifier Amplifier Sample/ A/D D/A Sample/ A/D D/A 2 2Hold
Converter Converter Hold Converter Converter+ +
1-bit 1-bit
Pipelining (used in video rate, RF basestations, etc.)
Parallelism (use many slower A/Ds in parallel to build veryhigh
speed A/D converters)
[ISSCC 2003],Poulton et. al.
20Gsample/sec,8-bit ADCfrom Agilent Labs
Figure by MIT OpenCourseWare. Adapted from Poulten, Ken, et al.
"A 20 GS/s 8b ADC with a 1MB Memory in 0.18um CMOS."IEEE
International Solid-State Circuits Conference Paper 18.1, 2003.
DLL1 GHzClock
Clock
Gen
CMOS Buffer Chip 2 muxes
80 T/Hs and V
/Is
80 AD
C Slices
80 Radix C
onverters
80 Slice Decim
ator
8 Mem
Controllers
1MB
yte SRA
M
0.18- CMOS ADC Chip
High Performance Converters:High Performance Converters:Use
Pipelining and Parallelism!Use Pipelining and Parallelism!
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L10: 6.111 Spring 2006 28Introductory Digital Systems
Laboratory
New Trend: Eliminate New Trend: Eliminate OpAmpsOpAmps!!(Use
Comparators, more digital(Use Comparators, more digital))
Op amps must achieve high open-loop gain and fast settling time
under feedback.High gain becomes increasingly difficult achieve due
to low device gain.Solution: Comparator based analog DesignDramatic
power savings possible
Courtesy of Prof. Harry Lee, ISSCC 2006. Used with
permission.
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L10: 6.111 Spring 2006 29Introductory Digital Systems
Laboratory
Summary of Analog BlocksSummary of Analog Blocks
Analog blocks are integral components of any system. Need data
converters (analog to digital and digital to analog), analog
processing (OpAmps circuits, switched capacitors filters, etc.),
power converters (e.g., DC-DC conversion), etc.We looked at example
interfaces for A/D and D/A converters
Make sure you register critical signals (enables, R/W, etc.)
Analog design incorporate digital principlesGlitch free
operation using codingParallelism and Pipelining!More advanced
concepts such as calibration
L10: Analog Building Blocks(OpAmps, A/D, D/A)Introduction to
Operational AmplifiersThe Inside of a 741 OpAmpSimple Model for an
OpAmpThe Power of (Negative) FeedbackBasic OpAmp CircuitsUse With
Open LoopData Conversion: Quantization NoiseNon-idealities in Data
ConversionR-2R Ladder DAC ArchitectureDAC (AD 558) SpecsChip
Architecture and InterfaceSetting the Voltage RangeAnother
Approach: Binary-Weighted DACGlitching and Thermometer
D/ASuccessive-Approximation A/DSuccessive-Approximation
A/DSuccessive-Approximation A/D (AD670)Single Write, Single Read
Operation(see data sheet for other modes)Simple A/D Interface
FSMExample A/D Verilog InterfaceExample A/D Verilog Interface
(cont.)Example A/D Verilog Interface(cont.)SimulationFlash A/D
ConverterAD 775 Flash Data ConverterHigh Performance Converters:Use
Pipelining and Parallelism!Summary of Analog Blocks