L01-Introduction-to-VLSI

8/7/2019 L01-Introduction-to-VLSI

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July 25, 2007 Prof. Indranil Sen Gupta, IIT Kharagpur 1

Introduction to VLSI Design


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Typical VLSI Design Flow

Design entry

Logic synthesis

System partitioning Floorplanning

Placement

Routing

Fabrication / Prototyping


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Design and Fabrication of VLSI Devices

VLSI chips are typically based on MOStechnology.

The basic problem is how to fabricatethese devices on the silicon floor.

The process of fabrication makes use of

masks.A mask is a specification of geometric shapes

that need to be created on a certain layer.

Masks are used to create specific patterns ofeach material in a sequential manner andcreate a complex pattern of several layers.


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Details of Fabrication Processes

Crystal growth and wafer preparation

Epitaxy

Dielectric and polysilicon film deposition Oxidation

Diffusion

Ion implantation

Lithography

Etching Packaging


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Issues Related to Fabrication Processes

Process scaling allows:High level of integration

Better yields (for a constant die size)

Lower costs

Possibility of larger die sizes (for a constantyield)

Several problems and issues crop up:Parasitic effects

Stray capacitances

Interconnect-related issues Interconnect delay

Noise and crosstalk

Power dissipation and yield


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Parasitic Effects

Circuit elements lie in close proximity. Inter-component capacitances play a major

role in the performance of these circuits.

Stray capacitanceCapacitance between signal paths and ground

Inherent capacitance of a MOS transistor

Interconnect capacitances.Between wires across layers.

More significant.

Can be reduced by connecting wires in adjacentlayers perpendicular to each other.

Between wires within the same layer.Can be reduced by increasing the wire spacing and

using power lines shielding.


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Interconnect Delay

Two types of delays in a circuit:

Gate delay

Interconnect delay Both types of delay depend on parameters

as:Width and length of the poly

Thickness of oxide

Width and length of metal lines

The process of extracting these parameters

is called extraction.Using a tool called RC-extractor.


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Noise and Crosstalk

Reduction in feature sizes and signalmagnitudes.

Circuits become more susceptible to externaldisturbances (noise).

Noise mainly arises out of resistive andcapacitive coupling.

Smaller feature sizes result in reduced nodecapacitances (i.e. less circuit delay).

These nodes also become more vulnerable to

external noise, especially they are dynamicallycharged.


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Contd.

Coupling between neighboring circuitsand interconnections is the most

prevalent form of internal noise.

Noise generated by off-chip drivers alsopose a major problem.

Noise margin is closely related to input-output voltage characteristics.

LNM = max (VIL

) max (VOL

)

HNM = min (VOH) min (VIH)


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Contd.

Crosstalk

A particular form of noise.

Result of mutual capacitance and inductancebetween neighboring lines.

Amount of coupling depends on:

Closeness of the lines.

How far they are from the ground plane.

The distance they run close to each other.

As a result of crosstalk, propagation delay

increases and logic faults occur.


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Power Dissipation

Heat is generated in a chip.

Primary heat sources are the individualtransistors.

Has to be removed by some type of heattransfer.

For high levels of integration, heat removal

becomes the dominant design factor.

If all the generated heat is not removed,

Chip temperature may rise resulting in thermal

breakdown.Hotspotsmay appear.


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Contd.

Power dissipation has become a topic ofintense research and development.

Due to the proliferation of lap-top computersand mobile devices.

Development of low-power circuits havebecome an important research area.

Typically, 25-35% power in a microprocessor isdissipated in the clock circuitry.

Low power dissipation can be achieved by literallyswitching-off blocks that are not needed for

computation in any particular step.


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Future of Fabrication Process

Fabrication process is very costly todevelop and deploy.

Semiconductor Industry Association (SIA)published the National TechnologyRoadmap for semiconductors in 1977.

Provides a vision for the future.Several manufacturers have released

roadmaps, which are far more aggressive thanthe SIA roadmap.


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SIA Roadmap

768768512512Package pins

7-876-76Wiring levels

520430360300Chip size (sq mm)

>1500>1100>750>500Frequency (MHz)

39186.23.7Transistors(millions/sq cm)

2006200319991997Time frame

0.100.130.180.25Feature size (micron)


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n-channel Transistor


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n-channel Transistor Operation


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n-channel Transistor Layout


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p-channel MOS Transistor


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Fabrication Layers


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MOS Transistor Behavior


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Summary of VLSI Layers


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VLSI Fabrication


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Silicon Wafer


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General Design Rules


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Types of Fabrication Errors


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Width/Spacing Rules (MOSIS)


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Poly-Diffusion Interaction


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Contacts


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Contact Spacing


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M2 Contact (Via)


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CMOS Layout Example


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Stick Diagrams


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Static CMOS Inverter


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Static CMOS NAND Gate


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Static CMOS NOR Gate


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Static CMOS Design :: General Rule


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Simple Static CMOS Design Example


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Static CMOS Design Example Layout


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More Difficult Static CMOS Design Example


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S


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Layout Styles

Hi hi l L


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Hierarchical Layout

C td


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Contd.

St d d C ll


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Standard Cells


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VLSI Design Styles

The Alternatives


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The Alternatives

Programmable Devices

Programmable Logic Device (PLD)

Field Programmable Gate Array (FPGA)

Gate Array

Standard Cell (Semi-Custom Design)

Full-Custom Design


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Field Programmable Gate Array(FPGA)

Introduction


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Introduction

User / Field Programmability.

Array of logic cells connected via routingchannels.

Different types of cells: Special I/O cells.

Logic cells.

Mainly lookup tables (LUT) with associated registers.

Interconnection between cells:

Using SRAM based switches.

Using antifuse elements.

Xilinx XC4000 Architecture


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CLB

CLB

CLB

CLB

SwitchMatrix

Programmable

InterconnectI/O Blocks (IOBs)

ConfigurableLogic Blocks (CLBs)

D Q

SlewRate

Control

PassivePull-Up,

Pull-Down

Delay

Vcc

Output

Buffer

InputBuffer

Q D

Pad

D QSD

RD

EC

S/RControl

D Q

SD

RD

EC

S/RControl

1

1

F'

G'

H'

DIN

F'

G'

H'

DIN

F'

G'

H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3

F2F1

C4C1 C2 C3

K

Y

X

H1 DIN S/R EC

Xilinx XC4000 Architecture

XC4000E Configurable Logic Blocks


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XC4000E Configurable Logic Blocks

D Q

SD

RD

EC

S/R

Control

D Q

SD

RD

EC

S/R

Control

1

1

F'

G'

H'

DIN

F'

G'

H'

DIN

F'

G'

H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2

F1

C4C1 C2 C3

K

YQ

Y

XQ

X

H1 DIN S/R EC

CLB Functionalities


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CLB Functionalities

Two 4-input function generators

Implemented using Lookup Tables using 16x1RAM.

Can also implement 16x1 memory.

Two Registers

Each can be configured as flip-flop or latch.

Independent clock polarity.

Synchronous and asynchronous Set / Reset.

Look Up Tables


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Look Up Tables

Capacity is limited by numberof inputs, not complexity

Choose to use each functiongenerator as 4 input logic (LUT)or as high speed sync.dual portRAM

Combinatorial Logic is stored in 16x1 SRAM Look Up Tables(LUTs) in a CLB

Example:

A B C D Z0 0 0 0 00 0 0 1 00 0 1 0 0

0 0 1 1 10 1 0 0 10 1 0 1 1

. . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

Look Up Table

Combinatorial Logic

AB

CD

Z

4-bit address

XC4000X I/O Block Diagram


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XC4000X I/O Block Diagram

Xilinx FPGA Routing


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Xilinx FPGA Routing

1) Fast Direct Interconnect - CLB to CLB

2) General Purpose Interconnect - Uses switch matrix

CLBCLB

CLBCLB

CLBCLB

CLBCLB

Switch

Matrix

Switch

Matrix

FPGA Design Flow


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FPGA Design Flow

Design Entry In schematic, VHDL, or Verilog.

Implementation

Placement & RoutingBitstream generation

Analyze timing, view layout, simulation, etc.

DownloadDirectly to Xilinx hardware devices with

unlimited reconfigurations.


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Gate Array

Introduction


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In view of the fast prototyping capability,the gate array (GA) comes after the FPGA.

Design implementation of

FPGA chip is done with user programming,

Gate array is done with metal mask design andprocessing.


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Gate array implementation requires atwo-step manufacturing process:

1. The first phase, which is based on generic

(standard) masks, results in an array ofuncommitted transistors on each GA chip.

2. These uncommitted chips can be customized

later, which is completed by defining themetal interconnects between the transistorsof the array.


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Channeled vs. Channel-less (SoG) Approaches


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The GA chip utilization factor is higherthan that of FPGA.

The used chip area divided by the total chip

area.

Chip speed is also higher.

More customized design can be achieved with

metal mask designs. Current gate array chips can implement as

many as millions of logic gates.


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Standard Cell Based Design

Introduction


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One of the most prevalent custom design styles. Also called semi-custom design style.

Requires developing full custom mask set.

Basic idea: All of the commonly used logic cells are developed,

characterized, and stored in a standard cell library.

A typical library may contain a few hundred cells.

Inverters, NAND gates, NOR gates, complex AOI, OAIgates, D-latches, and flip-flops.

Characteristic of the Cells


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Each cell is designed with a fixed height. To enable automated placement of the cells, and routing

of inter-cell connections.

A number of cells can be abutted side-by-side to formrows.

The power and ground rails typically run parallelto upper and lower boundaries of cell.

Neighboring cells share a common power and groundbus.

The input and output pins are located on theupper and lower boundaries of the cell.

Standard Cells


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Standard Cell Layout


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Floorplan for Standard Cell Design


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Inside the I/O frame which is reserved for I/Ocells, the chip area contains rows or columns ofstandard cells.

Between cell rows are channels for dedicated inter-cellrouting.

Over-the-cell routing is also possible.

The physical design and layout of logic cells

ensure that When placed into rows, their heights match.

Neighboring cells can be abutted side-by-side, whichprovides natural connections for power and ground

lines in each row.


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Full Custom Design


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In real full-custom layout the geometry,orientation and placement of every transistor isdone individually by the designer.

Design productivity is usually very low.

Typically 10 to 20 transistors per day, per designer.

In digital CMOS VLSI, full-custom design is rarelyused due to the high labor cost.

Exceptions to this include the design of high-volumeproducts such as memory chips, high-performancemicroprocessors and FPGA masters.

Comparison Among Various Design Styles


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Full

custom

Standard

cell

Gate

array

FPGA

SlowMediumFastVery fastDesign time

VariableVariableVariableProgram

mable

Interconnect

VariableIn rowFixedFixedCell placement

VariableVariableFixedProgram

mable

Cell type

VariableFixedheight

FixedFixedCell size

Design Style


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Various CMOS Structures

Transmission Gate


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Dynamic Register


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Semi-static Storage


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Dynamic Shift Register


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CMOS Clocked Logic


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CMOS Clocked Logic Design


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A D Flip-flop


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CMOS Inverter Delay


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Estimating R and C


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Pseudo-NMOS Logic


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Domino CMOS


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Domino CMOS Example


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July 25, 2007Prof. Indranil Sen Gupta, IIT Kharagpur

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Charge Sharing


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Evaluation of Domino CMOS gates


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Pass Transistor Logic


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Delay Through Pass Transistor Chains


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Full Adder

A B


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A B

Cout

Sum

Cin Fulladder

Express Sum and Carry in terms ofP,G,D

D fi 3 i bl hi h ONLY d d A B


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Define 3 new variable which ONLY depend on A, B

Generate (G) = AB

Propagate (P) = A B

Delete = A B

Can also derive expressions for Sand Cobased on D

and P

The Ripple Carry Adder

A B A B A B A3 B3


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A0 B0

S0

Co,0Ci,0

A1 B1

S1

Co,1

A2 B2

S2

Co,2

A3 B3

S3

Co,3

(= Ci,1)FA FA FA FA

Worst case delay linear with the number of bits

tadder

N 1( )tcarry tsum+

td = O(N)

Goal: Make the fastest possible carry path circuit

CMOS Full Adder

V


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VDD

VDD

VDD

VDD

A B

Ci

S

Co

X

B

A

Ci A

BBA

Ci

A B Ci

Ci

B

A

Ci

A

B

BA

28 Transistors

Inversion Property


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A B

S

CoCi FA

A B

S

CoCi FA

Minimize Critical Path by Reducing InvertingStages

Odd CellEven Cell


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A0 B0

S0

Co,0

Ci,0

A1 B1

S1

Co,1

A2 B2

S2

Co,2

Co,3FA FA FA FA

A3 B3

S3

Exploit Inversion Property

Note: need 2 different types of cells

nMOS Pass Transistor Logic

B B ACCA A


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A

A

B B

C

C

Sum Sum

ACC

B

CoutCout

B

A

A

A A

Transistor count (CPL) : 28

Carry Bypass Adder

P0 G1 P0 G1 P2 G2 P3 G3


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FA FA FA FACo,3Co,2Co,1Co,0Ci,0

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,2Co,1Co,0Ci,0

Co,3

Multip

lexer

BP=PoP1P2P3

Idea: If (P0 and P1 and P2 and P3 = 1)

then Co3 = C0, else kill or generate.

Manchester Carry Chain


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P0

Ci,0

P1

G0

P2

G1

P3

G2

BP

G3

BP

Co,3

Carry Bypass Adder (contd.)

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12 15


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Setup

Carry

Propagation

Sum

Setup

Carry

Propagation

Sum

Setup

Carry

Propagation

Sum

Setup

Carry

Propagation

Sum

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

Ci,0

The Binary Shifter

Right Leftnop


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Ai

Ai-1

Bi

Bi-1

Bit-Slice i

...

The Barrel Shifter

A3B


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Sh3Sh2Sh1Sh0

Sh3

Sh2

Sh1

A2

A1

A0

B3

B2

B1

B0

: Control Wire

: Data Wire

Contd.


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BufferSh3S h2Sh 1Sh0

A3

A2

A 1

A 0

Logarithmic Shifter

Sh1 Sh1 Sh2 Sh2 Sh4 Sh4


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A3

A2

A1

A0

B1

B0

B2

B3

Contd.


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Summary

An overview of the process of VLSI designh b t d


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p ghas been presented.

Various nMOS/CMOS design styles have

been discussed. As case studies, MOS realizations of

typical arithmetic circuits and shifters are

shown.

L01-Introduction-to-VLSI

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