Kunal Datta and Prof. Hossein Hashemi Ming Hsieh Department of Electrical Engineering Contact: Kunal Datta (213)-587-1109, [email protected] 220 fF 10 Ω 400 fF 96 pH V IN 48 pH 200 fF 80 pH 10 pF 2 x 16 m 40 pH 75 Ω 52 pH 150 fF 10 Ω 400 fF 96 pH V b_Core V OUT 260 Ω 260 Ω 42 fF V CC_Driver 86 pH 10 pF 6 x 16 m V CC_Core 44 pH 1.7mm 1mm Performance at Peak P out Performance Metric Simulated Performance Measured Performance Technology Node IBM 130nm SiGe BiCMOS IBM 130nm SiGe BiCMOS Center Frequency / BW -1dB 39 GHz / 3.5 GHz 39 GHz / 4 GHz Output Power 19.2 dBm (84 mW) 19.6 dBm (91 mW) Power Gain 8 dB 8.9 dB Drain Efficiency (η) 25.5% 16.1% PAE MAX 21.4% 14% 1.3mm 0.8mm 200 fF 140fF V C L 1 C 12 V out L 2 500fF 10K 58pH 51pH 100Ω 46pH 60fF 6x12um 6x16um V CC_Core V Bias 10 pF Avalanche Compensated Bias Circuit 140 fF 10 Ω 250 fF 96 pH 48 pH 80 pH 10 pF 2 x 16 m 62 pH 75 Ω V CC_Driver V IN Performance Metric Simulated Performance Technology Node IBM 130nm SiGe BiCMOS Center Frequency / BW -1dB 45 GHz / 4 GHz Output Power 22.15 dBm (165 mW) Power Gain 11.5 dB Drain Efficiency (η) 31.5% PAE MAX 29% 140 fF 10 Ω 250 fF 96 pH 48 pH 80 pH 10 pF 2 x 16 m 62 pH 75 Ω VCC_Drive r VIN VCC_Core Vout 500fF 1K 58pH 1K 140fF 46pH 60fF 6x12um 6x16um 6x12um 60fF 100Ω 500fF VBias_Cor e Avalanche Compensated Bias Circuit 1.3mm 0.8mm Performance Metric Simulated Performance Technology Node IBM 130nm SiGe BiCMOS Center Frequency / BW -1dB 45 GHz / 4 GHz Output Power 23.4dBm (220 mW) Power Gain 12.7dB Drain Efficiency (η) 25% PAE MAX 24% Control Bits (n) Unit Module Output Power (P out ) Total Power Combining Loss (0.5dB per combiner) Total Output Power (P out_Total ) P out_Total Resolution (2 n ) System PAE (25% PAE per unit module) 2 25.0dBm (316mW) 1.0dB 30dBm 4 19.8% 3 22.5dBm (176mW) 1.5dB 30dBm 8 17.6% 4 20.0 dBm (100mW) 2.0dB 30dBm 16 15.6% 5 17.5 dBm (56mW) 2.5dB 30dBm 32 14% Port 1 Port 2 Port 3 120μm 80μm 920μm 80μm M2 50μm 8.5μm AM Wilkinson Power Combiner RF in RF out Unit Module VCC Unit Module VCC Unit Module VCC Unit Module VCC Technological Constraints Topological Constraints P out PAE Linear Saturated Desired Class A Class D,E,F ClassB Class C Linearity PAE Linear PA Saturated PA Desired Performance Breakdown voltage of transistors scale down with increasing f T & f max . V breakdown < 6 V (in 130nm SiGe process), hinders watt-level power generation. Efficiency decreases with frequency due to -20 dB/dec roll off in power gain. Higher ohmic loss in passives at higher frequency (due to lower skin depth) degrades efficiency. Peak efficiency in linear PAs degrade with power back-off. Maintaining high efficiency with power back off is essential for modulating signals with high Peak to Average Power Ratio (PAPR) (as in OFDM). Saturated/switching PAs can give higher efficiency but at the cost of linearity. a(n) Modulator + Rect-to-Polar (n) Calibration and Control Sensing Reciever AM-AM, AM-PM, Phase Error, Delay, Sensing Receiver Calibration Miscellaneous Controls Data In AM-PM Pre- distortion AM-AM Pre- distortion LUTs Digital Baseband Serial Port Interface Crystal XTAL Oscillator Digital ΔΣ Modulator I/Q VCO Digital to Phase Converter (DPC) PLL Binary-to- Therm Saturated PA Array + Combiner Digital Envelope Combiner (DEC) Phase Skew Calibration FDEC FDPC I-Q & Phase Calibration Ref Q Synthesizer Digital ΔΣ Modulator N n m 1 2 N VDD VDD VDD Phase Distribution Clock Gen I RF Out Saturated/switching class PAs in individual power modules for high efficiency. Amplitude modulation using low-loss switching supplies. Phase modulation using phase-shifters. ∆Σ modulators for minimizing in-band quantization noise. Digital polar architecture ensures high PAE at both peak and average power. Active Device ON Active Devices OFF V CC V out V C L 1 i L i Device i load R Load X L L 2 C 2 V B +V SIG V CC V ou t V C L 1 i sw R Load X L L 2 C 2 r on V C t V B +V SIG V in V CC V out V C L 1 i C R Load L 2 C 2 C sub t V C X L V B +V SIG V in t V in V C V out I Device High V CC (for higher P out ) causes avalanche induced base instability. Interconnect parasitic degrade f MAX of the device and lower performance. Passive networks must be properly chosen to have high enough self resonating frequency. Passive structures and interconnect are modeled using electromagnetic simulators. Small signal and large signal stability are analyzed using periodic steady state simulations. Avalanche phenomenon can be alleviated by using series stacking of transistors to increase stability margin without compromising power and PAE performance. V CC V out V C L 1 C 12 i L i Device i C i load R Load X L L 2 C 2 C 11 V mid C C R DC2 R DC1 V B +V SIG V Bias t V be1 V be2 V mid V C t V out I C V b2 V b1 Active Devices ON V CC V out V C L 1 i sw R Load X L L 2 C 2 V mid C π2 C C R DC2 R DC1 r on r on t t V Bias V B +V SIG t V b1 V b2 V b2 V b1 V CC V out V C L 1 C 12 i C R Load X L L 2 C 2 C 11 V mid C π2 C C R DC2 R DC1 V mid t V C V mid t V b2 V Bias V B +V SIG V b1 t V b1 V b2 Active Devices OFF Series stacking of devices ensure higher voltage swing across the same load resulting in higher output power Measurement of stacked devices. Large signal characterization and modeling of SiGe HBTs. Designing other blocks of the digital polar transmitter. Large signal nonlinear stability analysis. Deriving efficiency limit of active devices in power amplifier implementation. Analyzing trade-off of performance vs stability in mm-wave power amplifiers. Watt-Level Efficient Linear Power Amplifier in Sillicon Technology BiCMOS Frequency 45 GHz Peak Power 36 dBm Power Added Efficiency (PAE) at peak power 65% RF Bandwidth 3.5 GHz Data rate (64 QAM) 0.520 Gbps Bandwidth 100 MHz Error Vector Magnitude (EVM) < 2% ACPR @ 1*BW ch < –55 dBc High Data Rate Wireless Communication Active Radars Active mm-Wave Imaging 23GHz 29GHz 35GHz 59GHz 64GHz 71GHz 76GHz 81GHz 86GHz 92GHz 95GHz 110GHz 122GHz Automotive Radar Radio Navigation Military ISM Fixed Wireless Fixed Wireless Fixed Wireless Radio Astronomy ISM Automotive Radar mm-Wave Spectrum Allocation H 2 O O 2 O 2 Absorption Spectra