ki_thua_t_vi_xu_ly.pdf

I HC THI NGUYN

KHOA CNG NGH THNG TIN

Nguyn Trung ng

Bi Th Mai Hoa

GIO TRNH

K THUT VI X L

THI NGUYN, THNG 11 NM 2006

Gio trnh K thut Vi x l

LI NI U Cng ngh thng tin ang c ng dng rng ri trong nhiu lnh vc khoa hc

cng ngh v cuc sng thng nht. Bn cnh khi lng phn mm h thng v ng dng s, cng ngh phn cng cng pht trin v cng nhanh chng. C th ni cc h thng my tnh c ci thin trong nhng khong thi gian rt ngn, cng ngy cng nhanh hn, mnh hn v hin i hn.

Nhng kin thc c bn v v phn cng ca cc h thng my tnh lun lun l i hi cp thit ca nhng ngi chn cng ngh thng tin lm nh hng cho ngh nghip v s nghip khoa hc trong tng lai.

Gio trnh K thut Vi x l ny c vit trn c s nhng bi ging theo st cng mn hc c thc hin ti Khoa Cng ngh thng tin trc thuc Trng i hc Thi Nguyn t khi thnh lp n nay, v lun lun c sa cha b sung p ng nhu cu kin thc ca sinh vin hc tp ti Khoa.

Gio trnh c chia thnh 5 chng: Chng I gii thiu nhng kin thc tng quan c s dng trong k thut Vi x

l cc h m cch thc biu din thng tin trong cc h Vi x l v my tnh, cng nh nhn nhn qua v lch s pht trin ca cc trung tm Vi x l.

Chng II gii thiu cu trc v hot ng ca cc n v x l trung tm t P8085 n cc cu trc ca Vi x l h 80x86, cc cu trc RISC v CISC. Do nhng ng dng thc t rng ln trong i sng, trong chng II c gii thiu thm cu trc v chc nng ca chip Vi x l chuyn dng C8051.

Chng III cung cp nhng kin thc v t chc b nh cho mt h Vi x l k thut v cc bc xy dng vi nh ROM, RAM cho h Vi x l.

Chng IV i su kho st mt s mch chc nng kh lp trnh nh mch iu khin vo/ra d liu song song, mch iu khin vo/ra d liu ni tip, mch nh thi v mch iu khin ngt.

Chng V gii thiu cc cu trc v cch xy dng phi ghp mt s thit b vo/ra c bn cho mt h Vi x l nh bn phm Hexa, h thng ch th 7 thanh, bn phm my tnh v mn hnh.

Cun gio trnh chc chn c nhiu thiu st, rt mong c s gp ca cc c gi. Mi kin ng gp xin gia theo a ch.

B mn k thut my tnh Khoa Cng ngh Thng tin i hc Thi Nguyn Thi Nguyn Hoc theo a ch Email [email protected]

Nhm bin son

B mn K thut my tnh 2


CHNG 1. TNG QUAN V CC H VI X L

I.1. Cc h m

H m thng dng nht trong i sng l h m c s 10 (thp phn - Decimal), s dng 10 k t s t 0 n 9. Ngoi ra, trong sn xut, kinh doanh cn c khi s dng h m c s 12 (t - dozen).

Trong cc h thng my tnh, x l, tnh ton, ta s dng h m c s 2 (nh phn - Binary), h c s 8 (bt phn - Octal), h c s 16 (Hexa). Tuy nhin, vic nhp d liu hay a kt qu x l ta li dng h m c s 10.

Mt s N trong mt h m bt k c n +1 ch s, trong gm n ch s thuc phn nguyn v l ch s thuc phn thp phn, c trin khai theo cng thc tng qut:

R l c s ca h m

ak l trng ca ch s v tr th k (O < ak < R)

{ak}R = {0, 1, 2, 3,..., R - 1}

l, n l s nguyn

N = anan-1a1a0,a-1a-2a-1

Theo cng thc trn, cc s c biu din trong cc h m khc nhau s nh sau:

I.1.1. H m thp phn (R = 10 - Decimal)

{ak}D = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}

123,45D = 1 x 102 + 2 x 101 + 3 x 100 + 4 x 10-1 + 5 x 10-2

I.1.2. H m nh phn (R = 2 - Binary)

{ak}B = {0, 1}

11011.01B = 1 x 24 + 1 x 23 + 0 x 22 + 0 x 21 + 1 x 20 + 0 x 2-1 + 1 x 2-2 =

= 16 + 8 + 0 + 2 + 1 + 0 + 0,25 = 27,25D

I.1.3. H m bt phn (R = 8 - Octal)

{ak}O = {0, 1, 2, 3, 4, 5, 6, 7}

653,12O = 6 x 82 + 5 x 81 + 3 x 80 + 1 x 8-1 + 2 x 8-2 =

= 384 + 40 + 3 + 0, 125 + 0,03125 = 427,1562D

Lu : Cc ch s trong h ny c th biu din nh 3 k t s ("0" v "1")



trong h m nh phn theo bng sau:

Oct Binar Oct Binar Oct Binar Oct Binar

al y al y al y al y

0O 000B 2O 010B 4O 100B 6O 110B

1O 001B 3O 011B 5O 101B 7O 111B

I.1.4. H m 16 (R = 16 - Hexa)

{ak}H = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F}

3A7,C H = 3 x 162 + 10 x 161 + 7 x 160 + 12 x 16-1=

= 768 + 160 + 7 + 0,75 = 935,75D

Lu : Mt gi tr k t s Hexa c th biu din thng qua 4 k t s h nh phn theo bng sau:

Hex Binarr Hex Binarr Hex Binarr Hex Binarr

a y a y a y a y

0H 0000B 4H 0100B 8H 1000B CH 1100B

1H 0001B 5H 0101B 9H 1001B DH 1101B

2H 0010B 6H 0110B AH 1010B EH 1110B

3H 0011B 7H 0111B BH 1011B FH 1111B

Nhn xt:

1. Trong cc h m va c nu, h m c s 2 c rt nhiu u im khi x l trong my tnh. Th nht, vic m phng gi tr ca mt k t s l rt n gin: ch cn mt phn t c hai trng thi khc bit. S dng bn cht vt l ca vt mang thng tin biu din hai trng thi ny rt d thc hin. Trn dy dn in l cc trng hp c dng in (tng ng vi trng s l 1) hoc khng c dng in (tng ng vi trng s l 0).

2. Vic chuyn i gia hai gi tr 0 hoc 1 c th thc hin thng qua mt cng tc, trong thc t l cc phn t logic in t thc hin cc chc nng ca kho in t: ng (dng in i qua c) hoc m (dng in khng i qua).

I.2. Chuyn i ln nhau gia cc h m

I.2.1. H nh phn v h thp phn

a) T nh phn sang thp phn. S dng biu thc trin khai tng qut nu, cng tt c cc s hng theo gi tr s thp phn, tng s l dng thp phn ca s nh



phn cho.

V d. 11011.11B= 1 x 24 + 1 x 23 + 0 x 22 + 1 x 21 + 1 x 20 + 1 x 2-1 + 1 x 2-2

= 16 + 8 + 0 + 2 + 1 + 0.5 + 0.25 = 27.75D

b) T thp phn sang nh phn:

Phn nguyn: Ta c ng thc sau (v tri l s thp phn, v phi l biu din nh phn ca s ):

SD = kn2n + kn-12n-l + kn-22n-2 +... k121 + k020 + =

= 2(kn2n-l + kn-l2n-2 + kn-22n-3 +... + k1) + k0

V Ki = {0, 1}, ng phn vi s 0, 1 trong s thp phn, nn ta c th vit:

SD-K0 2

=kn2n-1 + kn-12n-2 + kn-22n-3 + + k1 = 2(kn2n-2 + kn-12n-3 + + k2) + k1

Thy rng: K t u tin ca s nh phn l k0, ng vi s d khi chia SD cho 2, k t tip theo, k1 chnh l s d khi chia thng cho 2, v. v... nn ta c th tm tt c cc k t khc nh sau:

V d: i s l73D ra s nh phn

Vy 173D = 10101101B

Phn phn s: ng thc quan h gia s thp phn v s nh phn (phn phn s) (v tri l s thp phn, v phi l s nh phn) nh sau:

SD = k-12-1 + k-22-2 + k-32-3 + k-m+12-m+1 + k-m2-m

2SD = k-1 + (k-22-1 + k-32-2 + k-m+12-m+2 + k-m2-m+1)

Thy rng k-1 tr thnh phn nguyn ca v phi, vy:

2SD k-1 = (k-22-1 + k-32-2 + k-m+12-m+2 + k-m2-m+1)

2(2SD - k-1) = k-2 + (k-32-1 + k-m+12-m+3 + k-m2-m+2)

k-2 l phn nguyn tip theo ca v phi c th bng 0 hoc bng 1. Tip tc tng t, thu c cc k t s ca cc phn t cn li.

V d: Chuyn i s 0.8128 thnh s nh phn

Thc hin php nhn lin tip vi 2, phn nguyn ca tch bao gi cng l cc gi



tr hoc bng "0" hoc bng "1", thu c kt qu sau:

0.81281 x 2 = 1.6256 = 1 + 0.6256

0.6256 x 2 = 1.2512 = 1 + 0.2512

0.25121 x 2 = 0.5024 = 1 + 0.5024

0.50241 x 2 = 1.0048 = 1 + 0.0048

0.0048 x 2 Qu nh c th b qua

Lu : Qu trnh bin i ny kt thc khi phn phn s ca tch s bng 0, tuy nhin, nu qu ko di, tu theo yu cu ca chnh xc d liu khi tnh ton v x l, c th b qua.

I.2.2. H nh phn v h Hexa

Chuyn i mt d liu nh phn sang h Hexa rt n gin, nu ch rng ta c 24 = 16, c ngha l mt s Hexa tng ng vi mt nhm 4 s ca s nh phn (t 0 n F). V vy, khi chuyn i, ch cn thay nhm 4 ch s ca s nh phn bng mt ch s tng ng ca h Hexa nh sau.

T hp nh phn

K t s

Hex

T hp nh phn

K t s

Hex

T hp nh phn

K t s Hex

T hp nh phn

K t s Hex

a a a a 0 0 0 0 0 0 1 0 0 4 1 0 0 0 8 11 0 0 C 0 0 0 1 1 0 1 0 1 5 1 0 0 1 9 11 0 1 D 0 0 1 0 2 0 11 0 6 1 0 1 0 A 11 1 0 E 0 0 11 3 0 11 1 7 1 0 11 B 11 11 F

V d:

Lu : Phn nguyn c nhm tnh t v tr ca ch s c trng nh nht, phn

phn s c nhm tnh t v tr ca ch s c trng ln nht.

T cch chuyn i trn, d dng nhn ra php chuyn i ngc t mt s h Hexa sang s h nh phn bng cch thay mt ch s trong h Hexa bng mt nhm 4 ch s trong h nh phn.

V d: F5E7.8CH = 1111 01011110 0111.1000.1100B



I.3. Biu din thng tin trong cc h Vi x l

Cc h Vi x l x l cc thng tin s v ch. Cc thng tin c biu din di dng m nht nh. Bn cht vt l ca vic biu din thng tin l in p ("0" ng vi khng c in p, "1" ng vi in p mc quy chun trong mch in t) v vic m ho cc thng tin s v ch c tun theo chun quc t. Mt bin logic vi ch hai gi tr duy nht l "0" hoc "1" c gi l mt bit. Hai trng thi ny ca bit c s dng m ho cho tt c cc k t (gm s, ch v cc k t c bit khc). Cc bit c ghp li thnh cc n v mang thng tin y cho cc k t biu din cc s, cc k t ch v cc k t c bit khc.

Bit (BInary digiT) l n v c bn ca thng tin theo h m nh phn. Cc mch in t trong my tnh pht hin s khc nhau gia hai trng thi (in p mc "1" v in p mc "0") v biu din hai trng thi di dng mt trong hai s nh phn "1" hoc "0".

Nhm 8 bit ghp k lin nhau, to thnh n v d liu c s ca h Vi x l c gi l 1 Byte. Do c lu gi tng ng vi mt k t (s, ch hoc k t c bit) nn Byte cng l n v c s o cc kh nng lu gi, x l ca h Vi x l. Cc thut ng nh KiloByte, MegaByte hay GigaByte thng c dng lm bi s trong vic m Byte, d nhin theo h m nh phn, ngha l:

1 KiloByte = 1024 Bytes,

1 MegaByte = 1024 KiloBytes,

1 GigaByte = 1024 MegaBytes.

Cc n v ny c vit tt tng ng l KB, MB v GB.

1.3.1. M ho cc thng tin khng s

C hai loi m ph cp nht c s dng l m ASCII v EBCDIC.

- M ASCII (American Standard Code for Information lnterchange) dng 7 bits m ho cc k t.

- M ABCDIC (Extended Binary Coded Decimal Interchange Code) dng c 8 bits (1 Byte) m ho thng tin.

- Loi m c dng trong ngnh bu in, trong cc my teletype l m BAUDOT, ch s dng 5 bits m ho thng tin.

I.3.2. M ho cc thng tin s

Cc s c m ho theo cc loi m sau:



- M nh phn s dng cc s c biu din theo h m nh phn nh nu trn.

- M nh thp phn (BCD Code - Binary Coded Decimal Code) s dng cch nhm 4 bits nh phn biu din mt gi tr thp phn t 0 n 9. Cc gi tr vt qu gii hn ny (> 9) khng c s dng.

I.3.3. Biu din d liu s trong my tnh

Biu din d liu l s nguyn c du: Gi s dng 2 bytes (16 bits) biu din mt s nguyn c du, bit cao nht (MSB - Most Significant Bit) c dng nh du. S dng c bit du S = "0", s m c bit du S = "1".

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

S x x x x x x x x x x x x x x x

- Biu din d liu l s thc c du: V nguyn tc, du ca s vn l gi tr ca MSB nh quy c trn. C hai dng s c du phy c s dng trong my tnh: S du phy tnh (fixed point) v s du phy ng (foatting point).

+ Du phy tnh s phn chia chui ch s thnh phn nguyn v phn phn s. V d ta c th vit:

0011101.01101101

Nhng ni chung, trong cc my chuyn dng, thng phi tm mt phng php thch hp c th biu din s c du phy c nh m du phy c t ngay sau du, ngha l s du phy tnh c dng:

0.knkn-1kn-2k1k0

+ Du phy ng c dng rt ph bin, dng chun tc nh sau:

N = F x 2 trong : F l phn nh tr (Mantissa)

E l phn c tnh (Exponent - s m)

Theo nguyn tc ny, mt s thc c biu din trong cc my 32 bit nh sau:

S c biu din c gi tr thc tnh theo biu thc:

N = (-l)s x 2E-127 x F

Vi cch biu din ny, c th thy ln ca cc s nh sau:

S dng: +3.4 x 1038 < N < +3.4 x 10-38

s m: - 3.4 x 1038 < N < - 3.4 x 10-38



Lu : Khi kt qu php tnh vt qu cc gii hn trn, nu s m (exponent) l dng, s c coi l - hoc + . Trong trng hp s m l m v vt qua s m cc i cho php, kt qu c coi l bng 0.

Dng s chnh xc gp i (Double precision) c biu din nh sau (64 bits):

V gi tr thc c tnh theo biu thc: N = (-l)s x 2E-l023 x F.

Cng cn lu rng, i vi cc d liu s c du thun tin cho x l v tnh ton, trong my thng c biu din di cc dng m thun, m ngc (complement) hoc m b 2 (two-complement). Gi s ta c s A=+0.10010, cc m trn u biu din nh nhau, nhng vi s B = -0.10010 th s c biu din nh sau:

Bnh thng A = -0.10010

M ngc A = 1.00110 (b 1, tc l o cc ch s trong s )

M b 2 A = 1.00111 (tng ng vi b 1 cng thm 1)

I.3.4. Bn cht vt l ca thng tin trong cc h Vi x l

Trong cc h Vi x l, thng tin v cc gi tr "0" hay "1" c biu din thng qua mt mc in p so vi mc chun chung, thng l t (GND - GrDund). ln ca in p biu din cc gi tr ny ph thuc vo cng ngh c s dng to nn phn t mang thng tin. i vi cc mch t hp TTL (Transistor-Transistor-Logic), cc mc in p c m t trong hnh I.1

Hnh 1.1. Phm vi mc cao "1" thp "0" Ca mch TTL

Ta thng dng k hiu VH ch mc cao, VL ch mc thp. Trong mch TTL, ta dng mc cao mc thp ch in p cao, in p thp so vi in p chun chung. Cc mc cao, thp khng phi l mt gi tr c nh, m l mt vng gii hn cho php. Ngoi phm vi nu, vng khng thuc hai mc trn l vng khng chc chn, khng xc nh.



Vt mang thng tin v cc gi tr "0" hoc "1" l mt mch in t c bit, m

u ra ca n s tng ng vi mt trong hai mc trn, c gi chung l Flip-Flop. Tu theo yu cu s dng, cc Flip-Flop c cc kh nng thu nhn cc tn hiu vo v a tn hiu ra theo nhng quy lut nht nh (Hnh I.2)

I.4. Vi nt v thc hin cc php tnh trong h m nh phn

Php cng v php tr hai s nh phn 1 bit c thc hin theo quy tc nu trong bng sau:

A B Carr (Nh)

0 + 0 = 0 0

0 + 1 = 1 0

1 + 0 = 1 0

1 + 1 = 0 1

A B Hiu Carrow (Mn)

0 + 0 = 0 0

0 + 1 = 1 1

1 + 0 = 1 0

1 + 1 = 0 0

I.4.1. Php cng v php tr

a) Php cng i s cc s hng du phy c inh

i vi php cng i s: Thc hin bnh thng. Trong trng hp c mt ton hng l mt s m ta s dng m ngc hoc m b 2 ca n, hiu chnh kt qu theo cc quy tc thng qua cc v d minh ho sau:



Thy rng:

S biu th kt qu s l m thun nu l mt s dng. S biu th kt qu l m ngc nu ta dng m ngc i vi s hng m v

cho kt qu l mt s m

S biu th kt qu l mt s b 2 nu dng m b 2 i vi s hng m v kt qu l mt s m.

b) php cng i s cc s hng du phy ng:

i vi php cng i s cc s hng du phy ng, cn tin hnh cc bc sau:

Cn bng phn c tnh (s m) bng cch dch chuyn phn nh tr c tnh ca tng bng c tnh chung nh tr ca tng bng tng cc nh tr Chun ho kt qu nu cn. I.4.2. Php nhn v php chia

a) Php nhn:

i vi php nhn cc ton hng du phy tnh, vic quan trng l phi xc nh du ca kt qu, theo hu ca kt qu bng tng modulo 2 ca cc bit du. Tr s ca tch l kt qu ca php tnh tin (dch phi) v php cng.

Vi cc ton hng c du phy ng, du ca tch c xc nh nh php nhn vi du phy tnh, sau tin hnh tm tch s nh sau:

Cng phn c tnh (s m), kt qu l c tnh ca tch. Nhn phn nh tr, khng n du ca cc ton hng. Chun ho kt qu nu cn. b) Php chia:

i vi php chia cc ton hng du phy tnh, vic quan trng l phi xc nh du ca kt qu, theo du ca kt qu bng tng modulo 2 ca cc bit du. Tr s ca thng s l kt qu ca php dch tri v php tr.

Vi cc ton hng c du phy ng, du ca thng s c xc nh nh php



chia vi du phy tnh, sau tin hnh tm thng s nh sau:

Tr phn c tnh (s m), kt qu l c tnh ca thng s Chia phn nh tr, khng n du ca cc ton hng Chun ho kt qu nu cn. Nhn xt: D dng nhn thy rng cc php tnh s hc nu trn chung quy li vn

ch yu l thc hin php cng v php dch (shift).

I.5. Cu trc ca h Vi x l v my vi tnh

I.5.1. Vi nt v lch s pht trin cc trung tm Vi x l

S xut hin ca my tnh in t (MTT) vo khong nm 1948 m ra mt trang mi trong nghin cu khoa hc ni chung v khoa hc tnh ton ni ring. Nhng phi mi n nm 1971 , cc h Vi x l mi bt u xut hin. S ra i ca Single chip 4-bit Microprocessor Intel 4004 P4004) vo nm thc s l mt cuc cch mng trong ngnh cng nghip my tnh. C th ni P4004, vi di t x l 4 bits, lm i thay ton b cch nhn nhn v cc thit b u cui ca MTT, hay cc c cu chp hnh trong iu khin qu trnh. P4004 c th qun l trc tip 4K t lnh 8bit ca b nh chng trnh v 5120 bits b nh d liu RAM. CPU cn c 16 thanh ghi ch s c s dng lm b nh tm cho d liu. Vi tp lnh gm 46 lnh, P4004 chim c nhiu u th trong cc ng dng thc t lc by gi. Tip tc ca dng P 4bit ny l P4004, c nhiu ci tin mnh m so vi P4004 v mt lot cc chip chc nng, chip nh ra i. Trong giai on tip theo t nm 1974 n 1 977, Intel i u trong vic ch to cc CPU 8bit, P8008, P8080 v c bit l P8085, nhng CPU c BUS d liu 8 bits v BUS a ch 16 bits. Cc loi CPU ny c kh nng qun l dc 64K t nh ca b nh v 256 thit b ngoi vi. iu ng ch P8085 l cng ngh dn knh v chia s thi gian hp l trn

BUS cho php a ra thm nhng tn hiu iu khin rt mnh, cho php xy dng nhng my vi tnh u tin.

Khong thi gian nm 1978 n nm 1982 l giai on ra i v pht trin mnh m ca cc trung tm Vi x l 16 bits. c bit cui giai on ny l s xut hin cc trung tm Vi x l P8088, P8086, vi kh nng x l d liu 16 bits v BUS a ch 20 bits, c s dng to ra cc my vi tnh XT, c a mm lu gi chng trnh ng dng v d liu.

Tip theo ca giai on ny l s pht trin v bo ca cc loi P80186, P80286, 80386SX, 80486-SX v 80486-DX, vi nhp ng h ln n IOOMHZ. My vi tnh AT v cc my tnh PC ra i trong giai on ny gi thnh cn rt cao, nhng tr thnh rt thng dng trong i sng con ngi.

T khong gia nhng nm 1993 tr li y, cc trung tm vi x l Pentium ra



i, tc ngy cng cao, vi nhp ng h ln n hng GHZ, v s xut hin ca cc trung tm x l a phn lung nh cc chip Pentium IV hin nay.

I.5.2. Cu trc c bn ca h Vi x l

Cc khi chc nng c bn ca mt h Vi x l (hnh I.3) gm:

- n v x l trung tm (CPU)

- B nh ROM, RAM

- Thit b vo (nhp d liu - Input device)

- Thit b ra (a d liu ra - Output device)

Ngoi ra cn phi k n khi to xung nhp (Clock Generator) v khi ngun (Power Supply).

Hnh I.3. S khi cu trc c bn h Vi x l

Cc khi chc nng c bn c ni vi nhau qua mt tp ng dy truyn dn tn hiu in gi l BUS h thng. BUS h thng bao gm 3 BUS thnh phn: BUS a ch, BUS d liu v BUS iu khin. Thit b vo/ra thng c ghp ni vi BUS h thng thng qua giao din ghp ni (I/O lnterface).

n v x l trung tm (Central Processing Unit - CPU) l khi chc nng c bn nht to nn mt h Vi x l hay my tnh c nhn (Personal Computer - PC). My vi tnh l mt trong nhng ng dng c th ca mt h thng gi l H Vi x l.

a) CPU thc hin chc nng x l d liu thng qua cc hot ng chnh sau:

c m lnh - c tp cc bit thng tin "0" hoc "1" t b nh chnh Gii m lnh - to cc xung iu khin tng ng vi m lnh iu khin

hot ng ca cc khi chc nng khc

Thc hin tng bc cc thao tc x l d liu theo yu cu ca lnh. Bn trong CPU c cc thanh ghi (Registers):



Thanh ghi con tr lnh IP (Instruction Pointer), trong cc trung tm vi x l trc y cn gi l thanh m chng trnh PC (Program Counter) cha a ch ca lnh k tip cn c thc hin trong tun t thc hin chng trnh

Cc thanh ghi a dng khc GPRS (General Purpose Registers) lu tr tm thi d liu, kt qu trung gian hay trng thi ca h thng cng vi n v s hc v logic ALU (Arithmetic and Logic Unit) thc hin cc thao tc x l d liu

n v iu khin CU (Conlrol Unit) l thnh phn phc tp nht, c chc nng gii m lnh v to cc tn hiu iu khin hot ng ca ton h thng.

b) B nh chnh c t chc t cc t nh, trong IBM/PC t nh c di 1 byte (8 bits). B nh ny gm cc chip nh ch c ROM (Read Only Memory) v cc chip nh truy xut ngu nhin RAM (Random Access Memory) c tc truy cp nhanh. B nh c s dng cha cc chng trnh v cc d liu iu khin hot ng ca h thng. CPU nhn cc lnh t y khi ng h thng. Cc chng trnh ng dng v d liu c th c cha ROM hoc RAM, cc kt qu trung gian hay kt qu cui cng ca c c t hao tc x l c th dc cha trong c c thanh ghi a dng hoc trong khi nh RAM

c) Cc mch ghp ni vo/ra l cc mch in t cho php CPU trao i d liu vi cc thit b ngoi vi nh bn phm, mn hnh, my in... lm giao din vi ngi dng hoc cc b chuyn i s-tng t DAC (Digital/Analog Converter), chuyn i tng t-s ADC (Analog/Digital Converter), cc mch vo/ra s Do (Digiral Outputs), DI (Digital Inputs)...

d) H Vi x l cn c mt mch to xung nhp gi l ng h h thng (Clock Generator) iu khin v duy tr hot ng ng b ca tt c cc khi chc nng. B to xung ny c iu khin bng mt mch thch anh c tn s thch hp v m bo tn s lm vic n nh cho ton b h thng.

e) Mt khi ngun nui (Power Supply) cung cp nng lng cho h thng t mng in li.

B ngun ca cc h Vi x l thng thng l b ngun xung vi k thut ng-ngt dng bn dn cng sut (Switching Power Supply), va gn nh cng sut ln li va m bo gn sng nh nht v kh nng chng nhiu cao. Hnh I.4 l s khi ca b ngun ng-ngt. in p li (220VAC) c chnh lu trc tip, lc bng t ho cung cp cho mt b dao ng tn s cao (t 20KHZ n 40KHZ). Cc xung in p tn s cao c chuyn sang bin p xung cng sut h p. in p li ra ca bin p xung c chnh lu v lc thnh in p ngun mt chiu cung cp cho h thng. Nguyn l n p y l thay i rng ca cc xung c tn s n nh do vy s dao ng ca in p u ra khi c ti c chuyn qua b cm bin iu chnh rng ny, m bo s n nh ca in p ra.



Hnh I.4. S khi b ngun nui my tnh

I.5.3. T h Vi x l n my vi tnh PC

Trong thc t, cc h Vi x l hin i c trang b thm nhiu thit b ngoi vi tin dng tu theo yu cu, mc ch s dng v c giao din thn thin vi con ngi. l cc my vi tnh PC. Cng c th l nhng h Vi x l chuyn dng cho nhng mc ch tnh ton hay iu khin.

a) My tnh x l d liu: L cc my tnh c dng tnh ton x l cc d liu nh qun l nhn vin trong c quan, tnh ton tin lng, tnh ton kt cu cng trnh, phn tch d liu trong kinh doanh, v.v... Quan im ng cho rng my tnh ch gm CPU v b nh chnh, cn cc thit b ph tr khc nh bn phm, my in, cc a cng, a mm, CD, chut, mn hnh, my in..., l nhng thit b ngoi vi. Cc chng trnh x l d liu c lu gi trong b nh chnh hoc trong cc a, c nhim v x l nhng d liu c ngi dng nhp vo v a kt qu x l ra mn hnh, in ra giy hoc lu gi trong cc a. nh gi tnh nng v cht lng ca cc my ny, ta thng cn c vo tc x l d liu, dung lng b nh, a, cht lng mn hnh, my in v.v...

Hnh I.4. My Vi tnh PC

b) My tnh l b x l s: i vi cc my tnh ny, thi gian dnh cho x l d liu rt nh, cn thi gian tnh ton, x l cc s liu li v cng ln. Cc my tnh loi ny c s dng ch yu trong cc c quan d bo, nh d bo kh tng, thu



vn, trong tnh ton qu o bay ca tn la, my bay, tu thu, v.v... hay trong cc phng nghin cu khoa hc. Nhng my tnh loi ny thng thng thc hin nhng chng trnh tnh ton khng l, nn chng c trang b cc CPU rt mnh v cc thit b ngoi vi, b nh ngoi rt ln. l nhng siu my tnh (Supercomputer).

c) My tnh o lng v iu khin: S pht trin nhanh chng ca cc h thng my tnh to ra nhng ng dng ln lao trong cc h thng o lng v iu khin t ng. i vi cc ng dng thng thng nh trong cc dng c gia dng, t Ti vi, iu ho nhit , my git v.v... l nhng my tnh nh c ch to di dng mt vi mch (Single-chip Microcomputer). Tuy nhin, cng cn phi tnh n nhng my tnh ny trong cc thit b hin i v phc tp nh trong cc h thng t ng li my bay (Autopilot), tu thu, tn la...

d) Cn c vo tnh nng k thut v cc ch tiu v kch thc: Cc my tnh cn c cha ra thnh my tnh ln gii cc bi ton cc ln vi tc rt nhanh, my tnh nh s dng trong gia nh, trong trng hc hay cc tnh ton thng dng, iu khin cc qu trnh cng ngh va v nh.

Cng cn nhc n y mt s khc bit gia hai khi nim h Vi x l v my vi tnh: Cc my vi tnh lun lun c trang b mt phn mm c bn l H iu hnh, v d: MS-DOS hay cc phin bn iu hnh a nhim (MS WINDOWS ca hng phn mm Microsoft, hoc cc h iu hnh ca cc hng khc...) v cc chng trnh hay phn mm ng dng, trong khi cc h Vi x l ch cn trang b mt chng trnh Monitor (chng trnh gim st) n gin c ghi trong b nh ROM.



CHNG II. CC N V VI X L TRUNG TM

(CPU - Central Processing Unit)

V hu ht cc my vi tnh ang c s dng Vit nam u c xy dng trn c s ca cc chip x l ca hng lntelR nn ti liu ny cng gii hn s trnh by trong khun kh cc trung tm vi x l ca hng ny. Cc c gi c th tm hiu thm v cc trung tm vi x l ca cc hng khc nh Motorola, AMD,... mt s ti liu tham kho lit k phn cui gio trnh.

Khi CPU c ch to t mt mch vi in t c tch hp rt cao th n c gi l b Vi x l (P - Microprocessor). Trong qu trnh pht trin, hng lntel cho ra i nhiu th h P t n gin n phc tp, t thng dng n chuyn dng. Tnh pht huy v k tha lun c coi trng trong qu trnh ny, v vy, cc chng trnh ng dng chun phn ln c th thc hin c trn bt k my vi tnh c xy dng t th h P no.

II.1. Trung tm Vi x l, P8085

Hnh II.1a) l s khi cu trc ca P8085



Hnh II.1a) l s ni chn ca P8085. Khc vi cc loi P xut hin trc nh P8008 hay P8080, P8085 c nhng bc pht trin c tnh t ph nh sau:

Hnh II.1b) S ni chn ca P8085

1. C cu ngt theo nhiu mc khc nhau c hnh thnh qua mt khi iu khin ngt, to ra mt vector ngt trnh c s chn nhau do lnh RET N trn BUS d liu. Tn hiu nhn bit yu cu ngt INTA c to bi khi iu khin ngt, ch khng phi t mch ph 8228 nh P8080.

2. Cc tn hiu iu khin ghi/c WR v RD c to ra t i nh thi v iu khin chc nng. Cc tn hiu INTA , WR v RD c to ngay trong CPU, ch khng do mch ph tr bn ngoi.

3. P8085 c mch to xung ng h c tch hp ngay trong CPU.

4. Khi chc nng iu khin vo/ra ni tip c tch hp cng cho php P8085 thc hin cc lnh vo/ra d liu ni tip m nhiu khi khng cn n s h tr ca vi mch chuyn dng.

5. c bit hn, P8085 c hai thanh ghi m a ch, l thanh ghi m Ai5 - A8 V thanh ghi m AD7-AD0 cho c d liu v a ch. Vic dn knh nh trn to iu kin cho nhng chn chc nng khc c to thm, lm tng thm sc mnh cho CPU.

II.1.1. Cc nhm tn hiu trong P8085

A8 A15. Nhm tn hiu ra: 8 bit cao ca a ch, cc chn ny l cc chn c ni vi bn ngoi qua mch 3 trng thi. Cc phn t 3 trng thi s c t trng thi high-z trong cc trng hp mt trong cc tn hiu HOLD hay HALT l tch cc.



AD0 AD7. Nhm tn hiu dn knh 3 trng thi. giai on u ca chu k my, T1 ca M1, s l byte thp ca 16 b a ch.

ALE (Address mch Enable). Tn hiu ra qua mch 3 trng thi. c s dng cht byte thp ca tn hiu a ch (A7 - A7) Tn hiu ny c to ra trong giai on u tin ca chu k my, T1 ca M1, v cng c dng cht cc tn hiu trng thi S0 v S1 khi cn thit.

S0 v S1 (Data BUS Status). L cc tn hiu ch trng thi ca cc chn thuc BUS d liu trong mi chu k my. T hp ca hai tn hiu ny cng cho bit trng thi ca CPU

S0 S1 Hot ng ca BUS d liu

0 0 Trng thi HALT

0 1 CPU ang thc hin thao tc WRITE

1 0 CPU ang thc hin thao tc READ

1 1 CPU ang thc hin thao tc nhn lnh Instruction fetch

RD (Read). Chn ra 3 trng thi. Nm trong nhm tn hiu iu khin. Tn hiu tch cc khi CPU tin hnh c d liu t b nh hoc t thit b ngoi vi. Trong ch HALT hoc DMA, chn ra ny trng thi high-z.

WR (Write). Chn ra 3 trng thi. Nm trong nhm tn hiu iu khin. Tn hiu tch cc khi CPU tin hnh ghi d liu vo b nh hoc a d liu ra thit b ngoi vi. Trong cc ch HALT hoc DMA, chn ra ny trng thi high-z.

IO/ M . Trng thi logic ca u ra ny cho bit CPU ang lm vic vi thit b ngoi vi hay vi b nh. Nu l logic "l", CPU ang truy cp thit b vo/ra, cn nu l "0", CPU ang truy cp b nh. Kt h vi hai u ra RD v WR to ra cc tn hiu , , I/OR I/OW RD , MEMR v MEMW trong trng hp s dng a ch tch bit i vi thit b vo/ra. Nm trong nhm tn hiu iu khin, nn IO/ M cng l u ra 3 trng thi.

Interrupts. P8085 c ngt a mc. C 5 chn ngt tt c: (INTR, RST5.5. RST6.5, RST7.5 v TRAP). Ngoi chn ngt khng che c l TRAP, cc chn khc u c th che hoc khng che nh lp trnh phn mm.

- INTR: Chn nhn yu cu ngt t bn ngoi, c p ng theo nguyn tc polling hoc vectoring thng qua lnh RST

- Cc yu cu ngt RST. C 3 u vo yu cu ngt vi cc mc u tin khc nhau l RST7.5, RST6.5 v RST5.5. Khi yu cu ngt xut hin ti cc chn ny, CPU t ng chuyn n cc vector ngt tng ng. C th nh sau:

RST5.5 l mc u tin thp nht, phn ng theo mc in p trn chn B mn K thut my tnh 19


yu cu ngt, a ch vector ngt ny nm nh c a ch 2CH.

RST6.5 Ngt u tin thp th 2, phn ng theo mc in p trn chn yu cu ngt, a ch vector ngt ny nm nh 34H.

RST7.5 Mc u tin cao nht. Phn ng theo sn ln ca xung yu cu ngt. Sn ln ca xung ny tc ng ln mt flip-flop, mch ny gi li yu cu ngt cho n khi c xo nh tn hiu nhn bit yu cu ngt Acknowledge. a ch ca vector ngt ny nm nh 3CH.

- TRAP: L chn nhn yu cu ngt khng che c (d nhin l n c mc u tin cao nht). a ch ca vector ngt ny nh 24H.

INTA . Tn hiu ra nhn bit yu cu ngt ti chn INTR. Cc yu cu ngt RST5.5, RST6.5, RST7.5 v TRAP khng tc ng n INTA .

HOLD. trng thi logic "1" chn ny l yu cu ca thao tc DMA.

Cc u ra RD, WR, IO/M v ALE s c a v trng thi high-z.

HLDA. Tn hiu nhn bit yu cu HOLD.

IN RESET . Logic thp "0" u vo ca chn ny yu cu ti khi ng h Vi x l. Do tc ng ca tn hiu RESET IN tch cc, gi tr ca thanh m chng trnh PC s c np li l 0000H cc mt n ngt v tn hiu HLDA cng c ti thit lp v gi tr mc nh.

RESET OUT. u ra nhn bit h Vi x l c ti khi ng. Dng tn hiu ny ti khi ng ton b h thng.

READY. Logic "1" u vo ny thng bo trng thi sn sng cung cp d liu cho CPU hoc nhn d liu t CPU ca cc thit b ngoi vi. SID (Serial Input Data). L cng vo ca d liu ni tip ca h Vi x l Bit hin din ti cng ny c c vo CPU nh lnh RIM, bit s c a vo bit cao ca Acc (MSB).

SOD (Serial Output Data). Bit cao (MSB) ca Acc c truyn ra ngoi chn ny khi s dng lnh SIM.

X1, X2. Li ni thch anh hoc mt mch dao ng to xung nhp cho CPU. C th s dng thch anh c tn s dao ng trong khong t 0.5 n 3MHz.

CLK. u ra ca xung nhp, c th lm xung nhp cho cc thnh phn chc nng khc trong h Vi x l.

Vcc, Vss. Li ni ngun +5V v GND cho P8085. Cng cn nhc li rng, P8085. ch cn mt ngun nui duy nht l +5V, kh nng cung cp dng ca ngun cn c thit k tu theo nhu cu ca ton h Vi x l.

II.1.2. Khi nim v bn cht vt l ca cc BUS trong h Vi x l

Hot ng ca mt h Vi x l thc cht l vic trao i v x l cc gi tr nh



phn gia cc thnh phn, cc khi v cc mch vi in t trong ton b h thng. Nh bit, cc gi tr nh phn (hoc "0" hoc "1") c th hin qua mc in p so vi mt chun nht nh. Gi tr "0" tng ng vi mc in p thp (t 0V n +0,8V) v gi tr "1" tng ng vi mc in p t khong +3V n +5V. biu din mt s liu nh phn, cc phn t mang thng tin c lin kt k nhau theo nhm (v d 1byte l 8 bits). m nhn cng vic di chuyn cc d liu ny trong ton b h thng, c cc ng dy truyn dn in chuyn dng c ghp song song thnh h thng, mi dy truyn dn dnh ring cho 1 bit. Tp cc ng truyn dn dnh ring cho cc tn hiu c cng chc danh (d liu, a ch, iu khin) c gi l BUS. Nh vy, trong mt h Vi x l, c ba loi BUS: BUS d liu, BUS a ch v BUS iu khin. Cc BUS ny hp li thnh BUS h thng.

T khi nim trn, d dng suy ra bn cht vt l ca cc BUS trong mt h Vi x l: l cc dng truyn dn in, c th di cc dng cp nhiu si, ng dn trong cc bng mch in v. v... Kh nng v cht lng dn in ca cc ng truyn dn ny ng vai tr quan trng v quyt nh i vi hot ng ca mt h Vi x l. ng truyn dn km, tr khng cao c th gy ra s suy gim ca tn hiu in dn n cc hin tng mt mt hoc sai d liu, rt nguy him.

BUS l ng dn in ni b m theo cc tn hiu c truyn t b phn ny n cc b phn khc trong h Vi x l. C 3 loi BUS trong mt h Vi x l cng nhu trong my tnh.

BUS d liu truyn d liu theo hai chiu gia b nh v trung tm Vi x l, gia cc thit b ngoi vi v Trung tm Vi x l

BUS a ch xc nh cc v tr nh trong b nh, cc thit b ngoi vi

BUS diu khin truyn cc tn hiu iu khin n cc b phn cn c iu khin

Cc BUS c xy dng bng cch s dng cc khe cng theo mt quy c cht ch i vi tng tip im. i vi cc khe cm, cc tip im tng ng s c ni vi nhau bng cc dy dn hoc ng dn song song trn mch in. Nh vy khi d liu c truyn i, tt c cc bit (8,16, 32, hay 64) u c truyn i ng thi, cng mt hng (truyn dn song song).

Cng cn ni thm rng, trong my PC, c 3 loi cu trc BUS thng gp l ISA (lndustrial Standard Architecture) EISA (Enhanced ISA) v PCI (Peripheral Component lnterconnect).

II.1.3. Cc mch 3 trng thi, mch cht v mch khuych i BUS 2 chiu

Trc tin, cng cn nhc li mt s linh kin in t s c bn s dng trong my vi tnh. Nh cng ngh cao, cc linh kin c tch hp ln v rt ln ra i, nhng



khng th khng nhn li mt s mch t hp thc hin nhng hm logic c bn nht.

a) Cc cng logic

K hiu cc mch c ch ra trn Hnh II.2, cng biu thc hm logic gm: mch m (bufer), mch o (NOT), mch v (AND), mch NAND, mch hoc (OR), mch NOR v mch XO

Hnh II. 2 ct s cng Logic thng dng

Cc loi mch ny thng c s dng to nn cc mch t hp logic thc hin cc chc nng lp m, gii m, dn knh v phn knh. Cng cn lu rng mt s mch chc nng nh gii m dn knh v phn knh c cc hng tch hp di dng cc mch MSI. Mt s mch c th k ra nh mch gii m 3/8 SN74138, mch dn knh 74151, mch cng, v mch nhn v.v...

b)Mch 3 trng thi (Tristate Component)

Trong h Vi x l, c nhiu khi chc nng cn thng tin, nhng ti mt thi im, bao gi cng ch c mt khi a tn hiu ra (d liu) v mt s hn ch cc khi thu nhn tn hiu. Thay v ni dy dn lin kt cc khi qua tng i phn t mt, cc tn hiu ny c a ln BUS. Vi cc cng logic thng thng, khng th ni trc tip chng ln cng mt ng dy v s xy ra tranh chp BUS v on mch. V d u ra ca phn t A l "1" trong lc u ra ca phn t B l "0". (Hnh II.3). Cc u ra ca loi mch ny u theo cu trc pull-up, ngha l c hai transistor c ni ni tip vi nhau (xem hnh v), emitter ca transistor ny qua mt diode ri n u ra, n collector ca transistor kia. Vi hai trng thi logic "1" v "0", tng ng s l T1 m, T2 ng v ngc li, T2 m v T1 ng. Trn hnh v II.2 hin tng nguy him xy ra khi li ra ca phn t logic A l "1", cc kho m hay ng tng ng vic transistor thng bo ho hay ngt, li ra chua phn t logic B l "0" v hin tng on mch xy ra.

trnh hin tng ny, mt loi cng logic gi l cng 3 trng thi (tri-state gate) c s dng cho li ra ca cc khi ni chung vo BUS. Hnh II.3a l mt phn t



o u ra 3 trng thi. Hnh II.3b l s tng ng ca trng thi high-z, tng ng vi trng hp u ra b tch khi BUS.

u ra Pull-up phn t logic Hnh II. 3a Hin tng on mch xy ra khi ni hai u

ra ca hai phn t trn cng mt ng dy ca BUS

Nh vy, trnh xung t trn BUS, cc phn t c u ra ni vi BUS cn phi a qua cng 3 trng thi.

Hnh II. 3b phn t o 3 trng thi v s

tng ng u ra ca phn t trng thi high-z

c) Mch cht, thanh ghi:

Mch cht l mt mch gm cc phn t c kh nng lu gi cc gi tr "0" hoc "1" li ra. C th dng D flip-flop lm mt mch cht vi tn hiu cht d liu ti u ra Q theo bng gi tr chn l sau:

Hnh II.4. Mch cht (hay phn t nh) D lip-Flop

Bit rng Qn+l = D vi tn hiu iu khin l s xut hin sn dng ca xung nhp CK. Nh vy, gi tr logic (0 hoc 1) ti D c chuyn sang u ra Q (cht). Nu CK gi nguyn trng thi bng "1", th trng thi u ra Q c gi nguyn. Nh vy, gi tr logic ca D c lu gi Q (nh).



Hnh II.5. Thanh ghi 4bits

Thanh ghi (Register) flip-flop c ni song song vi nhau, c th lu gi c cc s liu nh phn. Hnh II.5 l s mt thanh ghi lu gi s liu nh phn 4 bits c to t 4 phn t D flip-flop.

Mt s liu nh phn bt k t D3 n D0 s c cht sang cc li ra t Q3 n Q0 mi khi c mt sn ln ca Xung nhp CK c a ti li vo xung nhp. T nh phn ny c lu gi li ra cho n khi c d liu mi c a vo li D v c xut hin sn ln ca xung nhp CK.

d) Mch khuych i BUS 2 chiu

Trn c s ca cc mch 3 trng thi, cc mch khuych i BUS hai chiu c xy dng theo nguyn l sau:

Hai phn t 3 trng thi s c ghp ngc vi nhau (Hnh II.6) chn iu khin s dng tn hiu o ca tn hiu c RD. Khi xut hin tn hiu RD, d liu c php i t QD sang D0 ngc li, tn hiu ch c php i t D0 sang Q0 v cho php CPU a tn hiu ghi d liu ra ngoi.

Ghp ni s phn t cho tt c cc dy d liu, ta c mch khuych i BUS hai chiu. Trong thc t, mch c chc nng trn c tch hp theo chun ca TTL, c k hiu l 8228 hoc 8288 (Octal BUS Transceiver).

Hnh II.6 Phn t khuych i BUS hai chiu

II.1.4 Biu Timing thc hin lnh ca CPU P8085

Vic thc hin mt lnh trong P8085 thc t l mt chui cc thao tc READ v WRITE. Mi thao tc READ hay WRITE tng ng vi mt chu k my M). Mi lnh c thc hin qua 1 n 5 chu k my. Mi chu k my cn t 3 n 5 nhp ng h (hay cn gi l trng thi T)



chu k my th nht, CPU thc hin vic nhn m lnh (Instruction Code Fetch), Cn gi l chu k Opcode Fetch. Theo biu thi gian trn hnh II.8, thy rng vic thc hin chu k my M (chu k nhn lnh Opcode Fetch), CPU gi ra cc tn hiu IO/M, S1 v S0 (tng ng 0, 1, 1 trn biu thi gian) xc nh thao tc ca chu k.

Hnh II. 7 nh thi c s ca P8085 (Theo ti liu ca hng intel)

CPU cng ng thi gi 16 bit a ch ra chu k my u tin, ngay t nhp u tin (T1) xc nh nh hay thit b I/O. Ni dung PCL ch tn ti trong thi gian 1 nhp nn cn phi c cht li nh tn hiu ALE mc cao.

Khi D7 D0 - nh trn cc dy d liu, CPU gi tn hiu RD . Khi nhn c d liu, RD chuyn ln mc cao cm v tr nh hay thit b o

S lng chu k my v trng thi cn cho thc hin mt lnh l c nh, song s lng ny khc nhau i vi cc lnh khc nhau, tu theo di ca t lnh (l byte, 2 bytes, 3 bytes). S lng chu k my ph thuc vo s ln CPU phi lin lc vi cc phn t khc trong h thng, ch yu l vi cc chip khc.



Hnh II. 8 Biu thi gian ca cc tn hiu trong chu k my nhn lnh (Opcode Fetch)

II.1.5. Khi nim chu k BUS

Khong thi gian (tnh theo s lng chu k xung nhp) CPU (hoc n v lm ch BUS) thc hin hon thin mt thao tc di chuyn d liu t CPU n b nh, n thit b ngoi vi hoc theo chiu ngc li c gi l chu k BUS.

Mt chu k BUS c CPU hoc n v lm ch BUS thc hin trong hai giai on:

Giai on mt: CPU gi a ch v tr cn truy xut ( nh hoc thit b ngoi vi) ln BUS a ch, khong thi gian ny c gi l thi gian a ch (address time). a ch ch (destination - a ch ca mt nh hay a ch thanh ghi d liu ca thit b ngoi vi cn truy xut) c CPU (hoc n v lm ch BUS) gi ln BUS a ch cng cc tn hiu xc nh loi chu k BUS

- Giai on hai: CPU kim tra tn hiu sn sng (READY) ca n v cn truy xut (b nh hoc thit b ngoi vi) thc hin vic di chuyn v cht d liu. Khong thi gian ny c gi l thi gian d liu.

Tn ti 4 loi chu k BUS c bn:

a. Chu k BUS c d liu t b nh (Memory Read)

b. Chu k BUS ghi d liu vo b nh (Memory Write)

c. Chu k BUS c d liu t thit b ngoi vi (I/O Read)

d. Chu k BUS ghi liu vo thit b ngoi vi (I/O Write)



Hnh II.9 Biu thi gian ca cc tn hiu trong chu k

BUS c d liu t nh (Memory Read)

Ngoi ra, do s khc nhau v vn tc, kh nng x l v chun b, hon thin d liu, tn hiu READY cha mc tch cc, cc thao tc di chuyn d liu ca CPU phi to thm cc trng thi i (Wait State), do vy cc loi chu k BUS c di khc nhau.

II.1.6 Ngt (lnterrupt)

Trong thc t, tc x l d liu ca CPU cao hn rt nhiu so vi s ch bin d liu ca cc thit b I/O. V vy cn to ra mt c ch vo/ra hp l tng hiu sut lm vic ca CPU. Ngt trong h thng Vi x l nhm mc ch gii quyt s bt hp l do CPU phi ch i thit b ngoi vi. Thit b ngoi vi ch yu cu CPU phc v vic nhn hay chuyn giao d liu khi bn thn n sn sng. thc hin tt yu cu ny, c ch phc v ngt l hp l nht.

Ngt ngha l yu cu CPU tm thi dng cng vic hin ti trao i hay x l d liu khng thuc tun t ca chng trnh ang c thc hin. Ngt l mt hin tng xut hin ngu nhin v phng din thi im nhng c d on trc.

Ngt l hin tng mt tn hiu xut hin bo vi CPU rng c mt s kin xy ra yu cu CPU phi x l. Qu trnh x l ca CPU s b tm thi dng li thc hin mt thao tc khc phc v s kin c yu cu. Khi thao tc ny kt thc, qu trnh x l va b tm dng s c tip tc. Bn thn s kin thng thng l yu cu phc v ca thit b ngoi vi i vi CPU.

Trong thc t, ngt c s dng ch yu khi cc thit b ngoi vi (thng rt chm so vi tc x l ca CPU) cn trao i thng tin vi CPU.

Khi cn trao i thng tin, thit b ngoi vi gi tn hiu yu cu ngt (Interrupt Request) ti CPU. CPU s thc hin nt lnh hin ti v tr li bng tn hiu nhn bit



yu cu ngt ( INTA ). Chng trnh chnh lc ny b tm dng (ngt) v CPU chuyn sang thc hin chng trnh con phc v ngt, tc l chng trnh con trao i thng tin vi thit b ngoi vi yu cu ngt. Sau khi xong cng vic phc v ngt, CPU quay v thc hin tip chng trnh chnh k t lnh tip theo sau khi b ngt cc tn hiu yu cu phc v ngt t mt thit b ngoi vi bt k c gi ti chp nhn yu cu ngt ca CPU c th thng qua mt khi iu khin ngt, tu theo ngi lp trnh m yu cu ngt c c chuyn ti CPU hay khng. Trong trng hp yu cu ngt c gi ti CPU, x l ca CPU gm cc bc sau:

1. Thc hin nt lnh ang c x l

2. Pht tn hiu nhn bit yu cu ngt gi cho thit b yu cu phc v ngt qua chn INTA

3. Ct cc c trng thi hin ti vo ngn xp

4. Xo cc c IF (Interrupt Flag) v c TF (Trap Flag)

5. Ct a ch lnh tip theo trong tun t chng trnh ang thc hin vo ngn xp

6. Ly a ch ca chng trnh con phc v ngt trong bng vector ngt

7. Thc hin chng trnh con phc v ngt.

II.1.7. Truy nhp trc tip b nh (Direct Memory Access - DMA)

Trong nhiu trng hp, xy ra hin tng phi chuyn mt khi d liu t thit b ngoi vi vo mt vng nh hoc ngc li. Vi phng php vo/ra bng chng trnh, d liu no cng phi i qua CPU, do vy lm chm tc trao i d liu. khc phc tnh trng ny ta dng phng php trao i d liu gia mt vng nh vi thit b ngoi vi mt cch trc tip khng thng qua CPU, l phng php truy nhp trc tip b nh (DMA). Trong phng php ny, CPU giao quyn iu khin BUS d liu cho mt chip in t chuyn dng gi l chip DMAC (DMA Controller). Chip DMAC t to ra a ch, to cc tn hiu iu khin vic ghi c b nh, m s t d liu c ghi vo hoc c t b nh v s thng bo cho CPU khi thc hin xong vic trao i d liu vi b nh. Qu trnh c thc hin hon ton bng phn cng, trc tip gia thit b vo/ra v b nh nn tc trao i thng tin tng



i nhanh. CPU khng cn nhn lnh, gii m lnh v thc hin cc lnh di chuyn d liu.

Hnh II. 10 M t cc tn hiu iu khin trong qu trnh DMA

Khi c yu cu trao i d liu theo DMA, thit b ngoi vi gi tn hiu yu cu DRQ ti chip DMAC, chip ny gi tn hiu yu cu treo HRQ ti chn HOLD ca CPU. Nu yu cu c chp nhn, CPU s gi xung ghi nhn HLDA ti chn HACK ca chip DMAC v t treo cc BUS, cho php DMAC s dng BUS. DMAC gi tn hiu DACK ti thit b ngoi vi cho php thit b ny thc hin vic trao i d liu. Kt thc qu trnh trao i d liu chip DMAC chuyn trng thi ca tn hiu HRQ v mc thp thng bo cho CPU.

II.1.8 Vi chng trnh (Microprogram) v tp lnh ca P8085

a) n v iu khin CU - Conlrol Unit

CU - Control Unit l n v iu khin, iu phi mi hot ng ca cc b phn chc nng trong CPU thng qua Control BUS. C th coi CU l khi dch lnh ca CPU, n to ra cc tn hiu tng ng lm u vo cho Controller Unit iu khin hot ng ca cc khi chc nng. Cc tn hiu do CU to ra c th phn thnh 2 loi: Tn hiu nh thi v tn hiu iu hnh hot ng ca CPU. Cc tn hiu nh thi do CU to ra xc nh trng thi ca CPU lm vic:

- ang ch c d liu vo (Input mode)

- ang a d liu ra (Output mode)

- ang bt u mt hot tc khc (Beginning another operation).

Cc tn hiu trng thi ca CPU xc nh CPU ang:

- c d liu t b nh (Memory Read)

- Ghi d liu vo b nh (Memory Write)

- Nhn lnh (Instruction Fetch)



- c d liu t thit b ngoi vi (I/O Read)

- a d liu ra thit b ngoi vi (I/O Write)

Cng c th c nhng thao tc khng c nu y, nhng ch cc thao tc trn l quan trng nht.

Cn hiu rng mch Controller Logic to cc tn hiu iu khin da vo cc tn

hiu trng thi ca CPU v tn hiu nh thi, c ngha l to tn hiu g v vo thi im no.

hiu c kin trc khi CU, hy tm li gii p cho cu hi: Sau khi nhn lnh, CPU lm sao bit" phi thc hin nhng thao tc no thc hin lnh?

Tt c cc lnh u c biu din di dng m nh phn. Gi s lnh c biu din bng mt m 8 bits 01000111B (chuyn ni dung thanh ghi B sang thanh ghi A, k hiu l [A]


Hnh II.12 Nhn bit cc lnh t t hp m nh phn

D thc hin lnh, khi iu khin CU xc tin mi thao tc ngay bn trong CPU bng cch to ra cc tn hiu iu khin v cc xung nhp nh thi cho cc khi chc nng thc hin cc thao tc.

Sau khi nhn tn hiu t khi gii m lnh (Instruction Decoder), CU s to ra cc tn hiu iu khin v cc xung nhp. Tn hiu iu khin s cho php (Enable) khi chn thanh ghi (Reg Select) chn thanh ghi B v thit lp h thng ng truyn thng sut gia hai thanh ghi B v A. tip theo CU s to cc tn hiu tng ng vic truyn d liu gia hai thanh ghi c thc hin.

Tip theo, CU iu khin thanh m chng trnh PC tng ln 1 nhn tip lnh t b nh. V CU c nhim v gim st v iu khin mi thao tc ca cc thnh phn chc nng trong CPU, nn cc dy iu khin phi c ni trc tip t CU ti mi khi chc nng trong CPU nh trn hnh.

II.l3a. Cng cn nhn thc rng, lnh c CPU ly t b nh. Trong thc t, d liu x l cng c th xut pht t b nh, v cc thanh ghi cng c th c chn bt k ngoi tr thanh ghi lnh IR v thanh m chng trnh PC.

Nh vy, li cn thm mt thanh ghi lin lc vi BUS d liu c nhim v truy

nhp c vo b nh. Thanh ghi ny lm trung gian gia BUS d liu bn ngoi v



cc thanh ghi a nng khc, v n c lin lc vi nhau thng qua BUS d liu ni b (Internal Data BUS) - mt BUS m cc thanh ghi c truy xut trc tip. CU phi lm nhim v xc nh thanh ghi no c truy xut qua BUS d liu ni b ti thi im . Cng v BUS d liu ni b ca CPU truy xut n BUS d liu.h thng, nn cn phi c mt cch thc hoc cch ly chng khi cn thit, hoc cho php ghp ni, nn cn thit phi c thm thanh ghi m d liu hai chiu. V nh vy, CU phi lm nhim v iu khin hng di chuyn ca d liu khi i qua thanh ghi m (xem hnh II.13b).

b) Vi chng trnh

Gi thit rng li ra ca khi gii m lnh v to cc tn hiu iu khin phi to ra 12 tn hiu ti cc ca G1 G12, 2 tn hiu iu khin b nh v 5 tn hiu xung nhp kch hot cc thanh ghi PC (thanh m chng trnh), MAR (thanh ghi m a ch, MSR (thanh ghi m b nh), Do (thanh ghi d liu) v IR (thanh ghi lnh) iu khin qu trnh nhn v thc hin lnh ADD. Cc tn hiu ny c gi ti iu khin hot ng ca cc thnh phn khc nhau trong CPU. Mt chu trnh thc hin lnh trn s c thi hnh.

Thc t trong CPU ca my tnh c t 64 n hn 200 cc tn hiu iu khin nh th. S khc nhau quan trng gia cc lnh v vi lnh l ch vi lnh c nhiu trng hn. Tm bc trong bng trn l mt vi chng trnh dch mt giai on nhn lnh (OPCODE FETCH) c thc thi sau lnh cng ADD. Nh vy mt lnh c dch thnh mt chui cc vi lnh, hay ni cch khc, mi m lnh c mt vi chng trnh.



C th thy rng, khi gii m lnh v to cc tn hiu iu khin:

+ "Bit" phi thc hin lnh "nh th no", mt khi lnh t IR (Instruction Register) c chuyn ti.

+ Gii quyt vic thc hin mt lnh bng cch iu khin cc khi chc nng lin quan thc hin cc phn vic.

T cch nhn nhn trn, d dng nhn ra rng khi gii m lnh v to cc tn hiu iu khin l b no thc th ca CPU. C th coi khi ny l mt my tnh c dng (Special-purpose Computer)(*) bn trong CPU. N l ht nhn c bn nht dnh ring cho vic thc hin mt lnh. thit k v xy dng c khi ny, cn phi c mt "chng trnh" (program)(*) tht chi tit Chng trnh dng xy dng nn khi ny cn phi c nhng th tc tuyt i chnh xc nhm mc ch thc hin cc lnh.

Chng trnh c gi l Vi chng trnh (Microprogram) v c ch to nh l mt phn tch hp cng bn trong CPU, ngi lp trnh khng th thay th cng nh khng th truy nhp vo c.



i vi cc loi p dng bit-slice microprocessor, Vi chng trnh hon ton do ngi s dng xy dng.

b) Tp lnh ca P8085

Tp lnh ca P8085 c th chia thnh nhiu nhm lnh nh tu theo tng cch tip cn. Theo phng thc x l v kt qu ca vic x l d liu, cc lnh trong tp lnh c chia thnh 4 nhm chnh:

1. Nhm lnh chuyn d liu: cc lnh trong nhm ny thc hin vic di chuyn d liu gia cc thanh ghi vi nhau, gia thanh ghi vi b nh v ngc li, cc lnh vo/ra d liu v.v...

2. Nhm lnh s hc v logic: cc lnh trong nhm ny thc hin cc php tnh s hc c bn l cng v tr 2 ton hng, cc lnh tng gim, hay so snh ni dung thanh ghi, cc php tnh logic trong s sc nh phn, cc php dch tri, phi d liu trong thanh ghi, lnh quay vng tri phi v.v...

3. Nhm lnh iu khin: Bao gm cc nhm lnh r nhnh c iu kin v khng iu kin, cc lnh gi chng trnh con

4. Nhm lnh c bit: Nhm lnh c bit bao gm cc lnh ly b 1 ca s liu trong ni dung thanh ghi, lnh thit lp v xo cc c, lnh hiu chnh thp phn mt s liu Hexa v lnh vo/ra d liu ni tip.

II.1.9. Vi nt v lp trnh cho 8085

Pht trin phn mm (lp trnh) v cc k thut lin quan ng vai tr quan trng bc nht trong cc ng dng t n gin n phc tp ca cc h Vi x l v my vi tnh. i vi cc h Vi x l, mi ng dng u c pht trin nh vo mt "cng c' pht trin phn mm hon chnh: Lp trnh hp ng.

Qu trnh pht trin mt chng trnh (phn mm ng dng) cho mt h Vi x l, k t khi xc nh nhim v cn thc hin cho n khi chng trnh c ci t hon chnh vo h thng c th chia ra nm bc c bn sau y:

a) t vn (xc nhn vn ): Trc khi gii quyt vn , ngi lp trnh cn xc nh xem, liu vn c th c gii quyt nh mt chng trnh trong mt h Vi x l hay khng. Phi thy rng khng phi h Vi x l vn nng" n mc c (h gii quyt tt c mi vn ny sinh trong thc tin, thm ch i khi cn lm cho s vic cng thm phc tp.

b) Xc nh phng php gii quyt vn : y chnh l bc tm thut gii (Algorithm) ti u cho vn c t ra. Ngi lp trnh phi tm v la chn c t nhiu gii php mt gii php tt nht, nhng kinh t nht thc hin. Khng ch tm gii thut tt nht m cn phi tm ngn ng lp trnh ph hp nht gii quyt vn .



c) Thc hin gii php: Phng php gii quyt vn thng c xc nhn qua tng bc theo mt lu . Lu l cch th hin tng minh cc bc thc hin chng trnh trong h thng, ng thi n gip ngi lp trnh nh hng tt khi vit chng trnh.

d) Vit chng trnh: Bn thn lu cho thy r gii php gii quyt vn theo quan im lp trnh. Vic chuyn t lu sang ngn ng chng trnh l bc d dng hn rt nhiu so vi cch vit chng trnh khng c lu . y ch l bc c th ha lu nh tun t thc hin cc lnh, v l bc thc t ha gii php thc hin vn .

e) Kim tra v g ri: Sau khi ci t vic kim tra tnh chnh xc l v cng quan trng. Nhng sai st phi c pht hin v hiu chnh, i khi l t chnh thut gii. Vic g ri chng trnh tc l thc hin tng bc chng trnh, pht hin cc sai st n, hiu chnh cc sai st ny.

thc hin c tt cc cc bc trn ngi lp trnh phi c k thut lp trnh hon thin thit k chng trnh, phi c cc cng c lp trnh tt.

II.1.10. H hiu hnh ca P8085

Cc lnh ca P8085 c thng k trong bng II.1

Mnemonic Instruction Code

D7 D6 D5 D4 D3 D2 D1 D0 M t nhim v

MOVE, LOAD, AND STORE MOV r1, r2 0 1 D D D S S S Move Register To Register MOV M, r 0 1 1 1 0 S S S Move Register To Memory MOV r, M 0 1 D D D 1 1 0 Move Register To Register MVI r 0 0 D D D 1 1 0 Move Immediate Register MVI M 0 0 1 1 0 1 1 0 Move Immediate Memory LXI B 0 0 0 0 0 0 0 0 Load Immediate Register Pair B LXI D 0 0 0 1 0 0 0 1 Load Immediate Register Pair D LXI H 0 0 1 0 0 0 0 1 Load Immediate Register Pair H STAX B 0 0 0 1 0 0 1 0 Store A indirect STAX B 0 0 0 0 1 0 1 0 Store A indirect LDAX B 0 0 0 1 0 0 1 0 Load A indirect LDAX D 0 0 0 1 1 0 1 0 Load A indirect STA 0 0 1 1 0 0 1 0 Store A direct LDA 0 0 1 1 1 0 1 0 Load A direct SHLD 0 0 1 0 0 0 1 0 Store H & L direct LHLD 0 0 1 0 1 0 1 0 Load H & L direct XCHG 1 1 1 0 1 0 1 1 Exchange D & E. H & L Register



STACK OPS PUSH B 1 1 0 0 0 1 0 1 Push Register Pair B & C on PUSH D 1 1 0 1 0 1 0 1 Push Register Pair D & E on PUSH H 1 1 1 0 0 1 0 1 Push Register Pair H & L on PUSH PSW 1 1 1 1 0 1 0 1 Push A ang Flags on stack POP B 1 1 0 0 0 0 0 1 Pop Register Pair B & C off stack POP D 1 1 0 1 0 0 0 1 Pop Register Pair D & E off stack POP H 1 1 1 0 0 0 0 1 Pop Register Pair H & L off stack POP PSW 1 1 1 1 0 0 0 1 Pop A ang Flags off stack XTHL 1 1 1 0 0 0 1 1 Exchange Register pair H & L, too SPHL 1 1 1 1 1 0 0 1 H & L to stack pointer LXI SP 0 0 1 1 0 0 0 1 Load immediate stack pointer INX SP 0 0 1 1 0 0 1 1 increment stack pointer DCX SP 0 0 1 1 1 0 1 1 Decrement stack pointer JUMP JMP 1 1 0 0 0 0 1 1 Jump uncoditional JC 1 1 0 1 1 0 1 0 Jump on carrv JNC 1 1 0 1 0 0 1 0 Jump on no carrv JZ 1 1 0 0 1 0 1 0 Jump on zero JNZ 1 1 0 0 0 0 1 0 Jump on no zero JP 1 1 1 1 0 0 1 0 Jump on positive JM 1 1 1 1 1 0 1 0 Jump on minus JPE 1 1 1 0 1 0 1 0 Jump on parity even JPO 1 1 1 0 0 0 1 0 Jump on parity odd PCHL 1 1 1 0 1 0 0 1 H & L to program counter CALL CALL 1 1 0 0 1 1 0 1 Call uncoditional CC 1 1 0 1 1 1 0 0 Call on carry CNC 1 1 0 1 0 1 0 0 Call on no carry CZ 1 1 0 0 1 1 0 0 Call on zero CNZ 1 1 0 0 0 1 0 0 Call on no zero CP 1 1 1 1 0 1 0 0 Call on positive Cm 1 1 1 1 1 1 0 0 Call on minus CPE 1 1 1 0 1 1 0 0 Call on parity even CPO 1 1 1 0 0 1 0 0 Call on parity odd RETURN RET 1 1 0 0 1 0 0 1 Return RC 1 1 0 1 1 0 0 0 Return on carry



RNC 1 1 0 1 0 0 0 0 Return on no carry RZ 1 1 0 0 1 0 0 0 Return on zero RNZ 1 1 0 0 0 0 0 0 Return on no zero RP 1 1 1 1 0 0 0 0 Return on positive RM 1 1 1 1 1 0 0 0 Return on minus RPE 1 1 1 0 1 0 0 0 Return on parity even RPO 1 1 1 0 0 0 0 0 Return on parity odd RESTART RST 1 1 A A A 1 1 1 Restart INPUT/UOTPUT IN 1 1 0 1 1 0 1 1 Input OUT 1 1 0 1 0 0 1 1 Output RIM 0 0 1 0 0 0 0 0 Read interrupt mask SIM 0 0 1 1 0 0 0 0 Set interrupt mask INCREMENT AND DECREMENT INR r 0 0 D D D 1 0 1 Increment register DCR R 0 0 D D D 1 0 1 Decrement register INR M 0 0 1 1 0 1 0 0 Increment Memory DCR M 0 0 1 1 0 1 0 1 Decrement Memory INX B 0 0 0 0 0 0 1 1 Increment B&C register INX D 0 0 0 1 0 0 1 1 Increment D&E register INX H 0 0 1 0 0 0 1 1 Increment H&L register DCX B 0 0 0 0 1 0 1 1 Decrement B&C register DCX D 0 0 0 1 1 0 1 1 Decrement D&E register DCX H 0 0 1 0 1 0 1 1 Decrement H&L register ADD ADD r 1 0 0 0 0 S S S Add register to A ADC r 1 0 0 0 1 S S S Add register to A with carry ADD M 1 0 0 0 0 1 1 0 Add memory to A ADC M 1 0 0 0 1 1 1 0 Add memory to A with carry ADI 1 1 0 0 1 1 1 0 Add immediate to A ACI 1 1 0 0 1 1 1 0 Add immediate to A with carry DAD B 0 0 0 0 1 0 0 1 Add B&C to H&L DAD D 0 0 0 1 1 0 0 1 Add D&E to H&L DAD H 0 0 1 0 1 0 0 1 Add H&L to H&L DAD SP 0 0 1 1 1 0 0 1 Add SP to H&L SUBTRACT SUB r 1 0 0 1 0 S S S Subtract register from A



SBB r 1 0 0 1 1 S S S Subtract register from A with SUB M 1 0 0 1 0 1 1 0 Subtract memory from A SBB M 1 0 0 1 1 1 1 0 Subtract memory from A with SUI 1 1 0 1 0 1 1 0 Subtract immediate from A SBI 1 1 0 1 1 1 1 0 Subtract immediate from A with LOGICAL ANA r 1 0 1 0 0 S S S And register with A XRA r 1 0 1 0 1 S S S Exclusive OR register with A ORA r 1 0 1 1 0 S S S OR register with A CMP r 1 0 1 1 1 S S S Compare register with A ANA M 1 0 1 0 0 1 1 0 And memory with A XRA M 1 0 1 0 1 1 1 0 Exclusive memory with A ORA M 1 0 1 1 0 1 1 0 OR memory with A CMP M 1 0 1 1 1 1 1 0 Compare memory with A ANI 1 1 1 0 0 1 1 0 And immediate with A XRI 1 1 1 0 1 1 1 0 Exclusive immediate with A ORI 1 1 1 1 0 1 1 0 OR immediate with A CPI 1 1 1 1 1 1 1 0 Compare immediate with A ROTATE RLC 0 0 0 0 0 1 1 1 Rotate A left RRC 0 0 0 0 1 1 1 1 Rotate A right RAL 0 0 0 1 0 1 1 1 Rotate A left through carry RAR 0 0 0 1 1 1 1 1 Rotate A right through carry SPECIALS CMA 0 0 1 0 1 1 1 1 Complement A STC 0 0 1 1 0 1 1 1 Set carry CMC 0 0 1 1 1 1 1 1 Complement carry DAA 0 0 1 0 0 1 1 1 Decimal adjust A CONTROL EI 1 1 1 1 1 0 1 1 Enable interrupt DI 1 1 1 1 0 0 1 1 Disable interrupt NOP 0 0 0 0 0 0 0 0 No-operation HLT 0 1 1 1 1 1 1 0 Halt



II.1.1. M t chn ca P8086 v cc tn hiu

P8086 c ch to theo cng ngh HMOS, ng v CerDIP 40 chn. L loi Vi x l c kh nng x l trc tip d liu 8 hoc 16 bit. V tp 1nh, P8086 hon ton tng thch vi tp lnh ca IAPX 86/10 v v phn cng, hon ton tng thch vi cc mch ngoi vi ca cc trung tm 8080/8085 ca Intel.

Hnh II.14 S ni chn trung tm Vi x l 8086

P8086 c th hot ng mt trong hai ch :

- Ch MIN: CPU t to ra cc tn hiu iu khin hot ng ca BUS (cc chn t 24 n 34).

- Ch MAX: CPU ch a ra cc tn hiu trng thi, cn thm mt chip iu khin BUS (BUS controller 8288) v chip ny s thng dch cc tn hiu trng thi thnh cc tn hiu iu khin BUS tng thch vi cu trc MULTIBUSTM, cch ny m bo hot ng c s liu n nh hn.

Hnh II. 11 l s ni chn ca P8086

+ AD15 AD0: BUS dn knh d liu v a ch 16 bits

+ A19 - A16/S6 - S3: 4 bits a ch cao hoc 4 tn hiu trng thi hot ng hin ti ca CPU

S4 S3 Thanh ghi c truy xut..

0 0 ES

0 1 SS

1 0 CS

1 1 DS

S5 ch trng thi c ngt

S6 lun lun bng 0

+ BHE /S7: Tn hiu ny kt hp vi chn a ch A0 cho ch th cc trng thi sau:



BHE A0

0 0 Mt t c truyn qua Di5 - Do

0 1 Mt Byte trn D15 - D8 c truy xut ti mt a ch Byte l

1 0 Mt Byte trn D7 D0 c truy xut ti mt a ch Byte chn

1 1 cha xc nh

+ RD : Nu bng "l" ang c b nh (hoc thit b vo/ra)

Nu bng "0" ang ghi ra b nh (hoc thit b vo/ra)

+ READY: nu b nh (hoc thit b vo/ra) cn truy nhp hon tt vic chuyn d liu n (hoc i) chng cn pht ra tn hiu READY mc "1" ti chn CPU, ch khi y CPU mi c s liu vo hoc a d liu ra.

+ INTR: CPU kim tra trng thi chn ny sau khi thc hin xong mi lnh xt xem c yu cu ngt t phn cng n hay khng, nu mc "1", CPU s chuyn sang phc v ngt. Thao tc kim tra ny c th "chr" c nh dng mt n che ngt.

+ TEST : Li vo ny ca CPU lun lun c kim tra trong lnh WAIT. Nu bng "0" CPU tip tc thc hin chng trnh, nu bng "1", CPU chy cc chu trnh gi cho ti khi TEST = "0".

+ NMI: Chn ngt theo sn ln ca xung, khng che c.

+ RESET: Chn nhn tn hiu ti khi ng h thng. Nu c s thy i t "0" ln "1" v tn ti ti thiu trong 4 nhp ng h th h thng s t khi ng li.

+ CLK: Li vo ca xung nhp ng h

+ Vcc: Ngun nui +5V

+ GND: Chn ni t (0V)

+ MN/ MX : Khi c ni vi Vcc, P8086 hot ng ch MIN, nu ni vi GND, hot ng ch MAX

+ S2 , S1 , S0 : ch MAX, chip iu khin BUS s dng 3 tn hiu trng.thi ny pht ra cc tn hiu iu khin truy xut b nh v thit b vo ra. T hp c ngha nh sau:

S2 S1 S0

0 0 0 yu cu ngt cng qua chn 1NTR c chp nhn 0 0 1 c thit b vo/ra 0 1 0 Ghi thit b vo/ra 0 1 1 CPU b treo 1 0 0 np m chng trnh vo hng nhn lnh 1 0 1 c b nh



1 1 0 ghi vo b nh 1 1 1 trng thi th ng

+ RQ / GT 0, RQ / GT 1: Tn hiu phc v vic chuyn mch BUS cc b (Local BUS) gia cc n v lm ch BUS (BUS master). BUS cc b l BUS gia cc n v x l (khng phi l BUS ni vi cc thit b ngoi vi). n v lm ch BUS l P8086 hoc mt chip iu khin no (v d DMAC) hin ang nm quyn iu khin BUS cc b.

+ LOCK : nu bng "0" n v lm ch BUS khng nhng quyn lm ch BUS cc b

+ QS1, QS0 ch th trng thi ca hng nhn lnh trc PQ

0 0 khng hot ng

0 1 byte 1 ca m ton trong PQ c x l

1 0 hng i lnh c xo

1 1 byte 2 ca m ton trong PQ c x l

II.1.2 Cu trc Trung tm Vi x l h 80x86

Cc P h 80x86 c pht trin trn c s cng ngh VLSI vi cc phn t c bn l cc transistor trng MOS c tiu hao cng sut rt nh. S khi chc nng ca P8086 c th hin trn hnh II. 15, gm hai thnh phn ch yu l n v ghp ni BUS (BIU), n v thc hin lnh (EU). Tt c cc thanh ghi v ng truyn d liu trong EU u c di 16 bits. BIU thc hin tt cc cc nhim v v BUS cho EU: thit lp khu lin kt vi BUS d liu, BUS a ch v BUS iu khin. D liu c trao i gia CPU vi b nh khi EU c yu cu, song khng c truyn trc tip ti EU m thng qua mt vng nh RAM dung lng nh (6 bytes) c gi l hng nhn lnh trc (lnstruction Stream Byte Quere PQ - Prefetch Quere) ri mi c truyn cho h thng iu khin EU (Execution Ung Control System).

Khi EU ang thc hin mt lnh th BIU tm v ly lnh sau t sn vo PQ. y l c ch ng ng (pipeline), mt k thut tng tc cho CPU

K thut ng ng s dng mt vng nh RAM cc nhanh, lm tng ng k tc ca b Vi x l thng qua vic truy tm lnh t b nh chng trnh thay cho s lin h gia CPU vi b nh chng trnh. Ring vi b x l Pentium, c hai ng ng, mt cho cc lnh v mt cho cc d liu.

Bng sau cho ta vi thng s k thut c bn ca cc trung tm Vi x l h 80x86



Loi p di thanh

ghi

rng BUS a

ch

rng BUS d

liu

Khng gian a

ch

Tn s cc i

8088 16 bits 20 bits 8 bits 1 MByte 10 MHZ 8086 16 bits 20 bits 16 bits 1 Mbyte 10 MHZ 80188 16 bits 20 bits 8 bits 1 Mbyte 10 MHZ 80186 16 bits 20 bits 16 bits 1 Mbyte 10 MHZ 80286 16 bits 24 bits 1 e bits 16Mbytes 16 MHZ 80386SX 32 bits 24 bits 16 bits 16Mbytes 20MHZ 80386DX 32 bits 32 bits 32 bits 4Gbytes 40 MHZ i486 32 bits 32 bits 32 bits 4Gbytes 66 MHZ i486SX 32 bits 32 bits 32 bits 4Gbytes 25 MHZ Pentium (Phin bn u) 32 bits 32 bits 64 bits 4Gbytes 66 MHZ

Hnh II.15 Cu trc cc khi chc nng P8086

II.1.3 H thng thanh ghi trong cc P80x86

C th coi cc thanh ghi ca cc trung tm Vi x l nh mt b nh c t ngay bn trong CPU, c tc truy cp cc k nhanh, c dng lu gi cc d liu v cc kt qu tm thi ca cc qu trnh tnh ton, x l. Cc thanh ghi trong h P80x86 c di khc nhau, 16 bits vi cc trung tm 8088/86, 80188/86 v 80286,



32 bits vi cc trung tm 80386/486 tr i v c m t trn Hnh II. 13.

EU ca P8086 c 8 thanh ghi a nng vi tn gi l AH, AL, BH, BL, CH, CL, DH, DL. Nhng thanh ghi ny c th s dng ring r cho vic lu gi cc d liu nh phn 8 bits. Cng c th s dng chng thnh tng cp thanh ghi c tn gi l AX (AH-AL), BX (BH-BL), CX (CH-CL), v DX (DH-DL) lu gi cc d liu nh phn 16 bits.

Hnh II.16 Cc thanh ghi trong cc trung tm Vi x l h 80x86

1. Cc thanh ghi a nng:

u im ca vic s dng cc thanh ghi ny lu gi tm thi cc d liu l tc truy cp ca CPU vi chng nhanh hn rt nhiu so vi vic s dng cc nh.

2. Cc thanh ghi on:

CPU a ra BUS a ch 20 bts qun l mt khng gian nh 1Mbyte (l.048.576 Bytes) b nh vt l Tuy nhin, cc thanh ghi trong CPU li ch c di 16 bits, do vy, khng gian nh c chia thnh tng on (segment), mi on di 64kbytes, a ch ca Byte u tin c ly lm a ch on. Hai on nh k cn cch nhau ti thiu l 16 Bytes. Mi Byte nh trong on s c xc nh bi lch (offset), tc l khong cch tnh t Byte nh n u on.



Hnh II.17 V khi nim a ch on v a ch offsel

Nh vy, mi mt cp thng s bao gm a ch on v lch (segment offset) s xc nh a ch logic ca mt Byte nh vt l trong b nh. Thanh ghi on (Segment Register) cha 16 bits cao, thanh ghi lch (dng thanh ghi a nng hoc cc thanh ghi ch s, con tr) cha 16 bit thp ca 20 bits a ch. a ch vt l ca mt v tr nh do vy s c BIU tnh theo cng thc:

a ch vt l = (Segment) x 10H + (offset)

P8086 s dng 4 thanh ghi on ring bit l: Thanh ghi on m lnh CS (Code Segment), thanh ghi on ngn xp SS (Stack Segment), thanh ghi on m rng ES (Extra Segment) v thanh ghi on d liu DS (Data Segment).

- Thanh ghi on m lnh CS l thanh ghi cha a ch bt u ca on chng trnh hin hnh trong b nh

- Thanh ghi on d liu DS l thanh ghi a cha ch bt u ca on cha s liu hin hnh trong b nh, hay cn gi l ni cha cc bin ca chng trnh

- Thanh ghi on ngn xp SS l thanh ghi a cha ch bt u ca on ngn xp (Stack) trong b nh ( nh do thanh ghi ny ch n cn c gi l y ngn xp), ni lu gi a ch v d liu khi thc hin cc chng trnh con, lnh gi chng trnh con hoc th tc

- Thanh ghi on m rng ES l thanh ghi a cha ch bt u ca on cha cc d liu Chui, xu k t

- Ngoi ra, trong cc trung tm i386/1486 cn c hai thanh ghi on FS v GS.

Cc on trong b nh c th tch bit nhau, nhng cng c th gi chng ln nhau, nhng bao gi cng cch nhau ti thiu 16 Bytes. lch 16Bytes ny thc cht do 4 bit thp nht ca a ch t A3 trn A0 cha c xc nh. Khi b cng trong n v a ch tnh a ch vt l a ra BUS a ch, n ly ni dung thanh ghi on chn thm 4 s 0000B cho 4 bits thp nht ca 20 bits a ch ri mi cng vi 16 bits ca phn a ch offset. iu ny l gii cng thc tng trng nu trn. Phn a ch bt u ca on c lu gi trong thanh ghi on cng thng c gi l a ch c s hay a ch nn.

Hnh II. 18 M t cch tnh a ch vt l ca mt v tr nh

3. Thanh ghi c FLAG:



Ch c 9 trong s 16 bits ca thanh ghi c (trong cc b vi x l P8086 - P80286) v 11 trong s 32 bits. ca thanh ghi c (trong cc b x l i386/1486) c s dng. Mi c c th c lp (= "1") hay xo (="0) biu th trng thi kt qu ca mt php x l,trc hoc trng thi hin ti ca CPU. Cc c IOP, N, R v V lin quan n ch bo v trong cc b x l 80286 v i386/1486. Chn c cn li gm 6 c ch trng thi v 3 c iu khin.

Hnh II. 19 Vi tr cc c trong thanh ghi c ca h Vi x / 80x86

Cc c trng thi gm:

- C nh CF (cany flag) c lp nu mt thao tc xy, ra hin tng carry hoc borrow i vi ton hng ch. CF c th lp bi lnh STC v xo bi lnh CLC.

- C chn l PF (parity flag) c lp nu kt qu ca mt php x l c s bit bng "1" l s chn.

- C mang ph AF (auxiliary flag) c dng cho x l cc m BCD v c lp nu thao tc x l gy hin tng carry hoc borrow cho 4 bits thp ca ton hng

- C zero ZF (zero flag) c lp nu kt qu x l s liu c kt qu bng 0

- C du SF (Sign flag) du tng ng vi MSB ca kt qu php ton, c lp vi kt qu dng v xo vi kt qu m

- C trn OF (Overflow flag) nu kt qu php ton l qu ln cho ton hng ch.

Cc c iu khin gm:

- C hng DF (direction flag) xc nh hng ca php ton x l xu, chui l t, nu c lp, xu, chui s c x l t a ch cao ti a ch thp v ngc li. C c lp bi lnh STD v xo bng lnh CLD

- C ngt IF (Interupt enable flag) nu c lp, CPU s chp nhn yu cu ngt cng v phc v ngt. Dc lp bi lnh STI v xo bng lnh CLI

- C by TF (Trao flag) Dng trong g ri chng trnh (Debuger) Khng th lp hay xo trc tip bi lnh ca my.

4. Thanh ghi con tr lnh IP

Thanh ghi con tr lnh IP (Instruction Pointer) - thanh ghi 16 bts dng lu gi



phn offset ca a ch lnh k tip s c thc hin trong tun t thc hin chng trnh. Kt hp vi CS, IP ging nh thanh m chng trnh PC trong P8085, mi ln t lnh c c ra t b nh, BIU s thay i gi tr IP tu theo di ca t lnh (s bytes ca t lnh) sao cho n ch n t lnh k tip trong b nh chng trnh. Cng cn ni thm rng khi gp cc lnh r nhnh hoc lnh gi chng trnh con, gi th tc..., cc gi tr ca CS:IP s thay i t ngt khng theo quy lut trn. Cc gi tr mi ca CS:IP do ngi lp trnh cung cp thng qua a ch ca cc nhn (Label) trong chng trnh hoc gi tr c th.

5. Cc thanh ghi d 1iu

C 4 thanh ghi d liu:

- Thanh ghi tch lu AX (Accummulator register) thng dng lu gi cc kt qu x l

- Thanh ghi c s BX (Base register) thng dng ch a ch c s (y) ca mt vng nh trong b nh

- Thanh ghi m CX (Counter register) thng dng khai bo s ln mt thao tc no phi c thc hin trong cc vng lp, php dch, php quay..., Gi tr ca ni dung thanh ghi CX s gim i mt sau mi thao tc

- Thanh ghi s liu DX. (Data register) thng dng lu gi s liu dng lm thng s chuyn giao cho mt chng trnh. DX l thanh ghi duy nht c dng cha a ch ca cc thit b vo/ra

6) Cc thanh ghi con tr v ch s

C 2 thanh ghi con tr v 2 thanh ghi ch s:

- Thanh ghi con tr ngn xp SP (Stack Pointer) cha a ch nh ngn xp (vng nh c bit, hot ng theo nguyn tc LIFO - Last In First Out - vo sau ra trc) s dng cho vic lu gi tm thi cc d liu hay a ch khi gi chng trnh con, khi phc v ngt v.v...gi tr ni dung ca SP lun lun l phn offset ca a ch ngn xp k tip.

- Thanh ghi con tr c s BP (Base Pointer) c chc nng cha gi tr offset tnh t a ch SS nhng cn c s dng truy cp d liu bn trong ngn xp

- Cc thanh ghi ch s ngun DI v thanh ghi ch s ch SI (Destination Index v Source Index) c dng lu gi cc thnh phn offset i vi nhng vng d liu c ct trong on d liu. Hai ni dung ca hai thanh ghi ny lin kt vi ni dung thanh ghi on DS to ra a ch ngun v a ch ch ca vng nh.

II.1.4 Cc ch lm vic MIN/MAX

P8086 c hai ch lm vic. ch MIN v ch MAX. Chn s 33 ca



P8086 c coi nh l chn by (trap pin) cho P8086 trong vic nh ngha ch lm vic. Nhng mch ph tr cn thit cho hai ch lm vic khng th tho mn vi h thng 40 chn ca CPU loi ny, v vy mt s chn s m nhim nhng chc nng khc khi c xc nh cho mt ch ph thuc vo cch ni chn MN/ MX . Khi, c ni vi GND (mc in p OV), P8086 chuyn i cc chn t 24 n 3 1 sang ch MAX. Mt mch ph iu khin BUS 8288 s gii m cc tn hiu trng thi S0 , S1 , S2 to ra cc tn hiu nh thi v cc tn hiu iu khin tng thch vi cu trc MULTIBUSTM trong cc h thng my tnh. Khi c ni ln mc in p ngun nui (mc Vcc +5V) t P8086 to cc tn hiu iu khin BUS trn cc chn t 24 n 31 nh c ghi trong ngoc Hnh II. 14.

II.1.5 Phng thc qun l b nh, cc mode a ch

a. Phng thc qun l b nh.

BUS a ch ca P8086 c di 20 bits, do vy c th qun l c 220 = 1M nh (Mi t hp "0" hoc "1" ca cc bit trong 20 bits a ch xc nh v tr ca mt nh). V mt nh trong h Vi x l l 1 Byte, nn ni cch khc, khng gian nh m P8086 qun l c l 1Mbyte..

Cc thanh ghi ca P8086 ch c di 16 bits, nn nu dng mt thanh ghi nh a ch th ch qun l c 216 nh, tc l 64KB. gii quyt vn qun l 1MByte, tc l 1.048.576 Bytes, P8086 s dng BUS a ch c rng 20 bits thng qua ni dung ca hai thanh ghi 16 bits nh a ch ca b nh theo phng thc sau:

Hnh II.20 Cch chia on nh trong P8086

Bng cch lp chng trnh, khng gian a ch c chia thnh cc on (segment) nh vi kch thc c nh l 64kbytes gi l mt n v logic ca b nh. Mi on gm cc nh lin tip, c lp v c nh v tch ri nhau. Mi on c ngi lp trnh gn cho mt a ch on, l a ch nh u tin ca on , cn c gi l a ch nn. Gi tr ca cc a ch on lin k cch nhau ti thiu l 16 Bytes. Cc on c th k cn, tch ri ph lp nhau. Bn trong on s s, dng cc gi tr lch (offset), tc l khong cch t a ch on n nh nm trong on. B mn K thut my tnh 47


Mt cp gi tr a ch on v gi tr lch, [segment]:[offset], c gi l a ch logic. a ch logic cho php nh v chnh xc mt Byte nh trong khng gian a ch. a ch on c cha trong cc thanh ghi on, gi tr dch chuyn c cha trong cc thanh ghi a nng, con tr hoc ch s.

V bn cht, thanh ghi on cha 16 bits cao ca 20 bits a ch, gi tr dch chuyn l 16 bit thp, v s lch nhau 4 bits c n v a ch ca BIU gii quyt nh trnh by trong hnh II. 18: Dch tri thanh ghi on 4 bits (tng ng php nhn vi 16, cng vi gi tr dch chuyn offset trong thanh ghi a nng tnh a ch vt l ca nh. Cng thc tng ng php "dch tri v cng" c th trnh by nh sau:

a ch vt l = 10H x (segment) + (offset)

Thanh ghi on l mt thanh ghi 16 bits c nhim v xc

nh on ca nh, cn thanh ghi a nng cng l mt thanh ghi 16 bits. Vy thanh ghi on c th nh c 216 = 65.536 n v (64K) on nh v mi on c 64kbytes. vy Vi x l P8086 c th nh a ch ti 64K x 64kbytes - 4Gbytes nh.

Thanh ghi on m CS xc nh on nh chng trnh m lnh k tip s c ly thc hin, thanh ghi con tr IP cha a ch offset ca lnh k tip Cp CS:IP to nn a ch logic ca lnh.k tip trong tun t thc hin chng trnh. Cc t lnh ca h 80x86 c th c di t 1 byte n ti a l 15 bytes. Khi lnh c thc hin, gi tr ca con tr IP do vy s tng ln ng bng s Bytes ca t lnh. Cn nh rng ni dung ca thanh ghi con tr lnh IP cng vi ni dung thanh ghi on CS xc nh a ch ca nh lnh tip theo trong tun t thc hin chng trnh.

b. Cc mode nh a ch

1. nh v thanh ghi (register addressing): Ton hng c truy xut nm ngay trong thanh ghi ca CPU.

Th d MOV AX,BX ;chuyn ni dung ca ton hng ngun (ni dung ca thanh ghi) BX vo ton hng ch AX. Ni dung thanh ghi BX vn c gi nguyn.

2. nh v tc thi (immedate addressing): Ton hng tc thi l d liu 8 hay 16 bits nm ngay trong lnh, c th dng lm ton hng ngun hay hng s. Ton hng tc thi c lu gi ngay trong on m ca b nh, ngay sau m lnh, n c ly



ra cng vi lnh v ghi vo hng i lnh PQ, do vy c truy xut nhanh hn so vi truy xut ton hng t b nh. Th d MOV AL, 12H; np s 12H vo thanh ghi AL

3. Cc kiu nh v b nh

Khc vi hai kiu nh v trn, ton hng trong on nh d liu c CPU truy xut qua BUS d liu. Bit rng, a ch vt l ca nh c tnh t ni dung thanh ghi on v offset theo cch trnh by trong Hnh II. 18. Gi tr offset m n v thc hin lnh EU tnh cho mt ton hng trong on nh c gi l a ch hiu dng EA (effective address) ca ton hng. n v thc hin lnh c th tnh EA da vo cch m t a ch trong phn ton hng ngun ca lnh. Ngoi gi tr trc tip, hoc ni dung thanh ghi c s hay thanh ghi ch s, khi cn cn c th c mt gi tr s c di 8 bits hay 16 bits c cng thm vo gi l gi tr dch chuyn d (displacement). Xem Hnh II.21

Hnh II.2 1 M t cch xc nh a ch vt l ca nh cn truy xut

C th nh sau:

- nh v trc tip (direct addressing): Ton hng cha a ch l mt s nm ngay trong lnh. a ch on hin ti nm trong thanh ghi on DS.

Th d MOV CX,[1435H] ;chuyn ni dung nh c a ch offset bng 1435H trong on s liu hin ti vo thanh ghi CX

- nh v gin tip thanh ghi (register indirect): a ch hiu dng EA l ni dung ca mt trong cc thanh ghi BX, BP, SI hoc DI

Th d MOV AX, [SI] ; chuyn ni dung ca nh trong on s liu hin ti c a ch offset l ni dung thanh ghi SI



- nh v c s (based addressing): EA l tng ca ni dung thanh ghi BX hoc BP v gi tr dch chuyn dp nu c

Th d MOV [BXI + dp, AL; chuyn ni dung thanh ghi AL v nh c a ch offset bng tng ca ni dung thanh ghi BX v gi tr dch chuyn dp

- nh v ch s (indexed addressing): EA l tng ca ni dung thanh ghi SI hoc DI v gi tr dch chuyn dp nu c

Th d MOV AL,[SI] + dp ;Chuyn ni dung nh c a ch offset bng tng ca ni dung thanh ghi SI v gi tr dch chuyn dp vo thanh ghi AL

- nh v ch s v c s (indexed addressing): EA l tng ca ni dung cc thanh ghi c s, thanh ghi ch s v gi tr dch chuyn dp nu c

Th d MOV AH,[BX][SI] + dp, chuyn ni dung nh c a ch offset bng tng ca ni dung thanh ghi BX, thanh ghi SI v gi tr dch chuyn d vo thanh ghi AH

- nh v chui (string addressing): dng ring cho x l chui. CPU s t ng s dng cc thanh ghi ch s ngun SI v thanh ghi ch s ch DI ch n cc byte k tip

Th d MOVS ;di chuyn chui, ngun ti vng nh c a ch u l DS: SI, ch l vng nh c a ch u DS: DI.

II.1.6. Phng thc nh a ch thit b ngoi vi

C hai phng thc c bn nh a ch thit b ngoi vi:

nh a ch tch bit (isolated I/O address): Cc tn hiu iu khin phi c phn bit i vi cc thao tc ghi/c b nh v ghi/c thit b ngoi vi. Trong h Vi x l P8085, t hp cc tn hiu RD , RW v IO/ M s c gii m to ra cc tn hiu c ghi ring cho b nh ( MEMR v MEMW ) v ring cho thit b ngoi vi ( I/OR v /OWI ). i vi h 80x86, l vic s dng cho iu khin BUS (BUS



Controllel 82.88) gii m t hp cc tn hiu nhp ng h CLK, cc tn hiu trm S2, S1 v S0 trong ch MAX thnh cc tn hiu MRDC , MWTC , IORC v IOWC . Cc mch logic ph tr iu khin truy nhp thit b ngoi vi trong h Vi x l c nhim v pht hin cc tn hiu IORC v IOWC thc hin cc thao tc vo/ra d liu. Mch logic ny c nhim v gii m a ch thit b ngoi vi to ra cc tn hiu cho php truy nhp ti thit b c th (thng c gi l mch gii m a ch thit b ngoi vi). Cng cn ni thm rng a ch thit b ngoi vi thc t l a ch ca mt thanh ghi trong thit b ngoi vi. Nh vy, vic trao i d liu gia CPU v thit b ngoi vi thc cht l trao i d liu gia CPU v thanh ghi trong khng gian thit b ngoi vi. Cc P80x86 dnh 16 dy a ch thp (A15 A0) qun l mt khng gian 64K thit b ngoi vi.

nh a ch tuyn tnh (Linear Addresing I/O), cng cn gi l nh a ch thit b ngoi vi theo bn nh (Memory-Mapped I/O): Thanh ghi trong thit b ngoi vi c coi nh mt v tr nh trong khng gian nh, do vy khng s dng n cc tn hiu iu khin ring cho vic trao i d liu gia CPU vi thit b ngoi vi, m s dng hon ton chung cho b nh cng nh cho thit b ngoi vi. i vi P8085, tn hiu phn bt O/M khng cn thit na, cng nh khng cn gi m cc t hp tn hiu S2 ,S1v S0 i vi cc trung tm 80x86. Mi thao tc trao i d liu gia CPU v cc thanh ghi thit b ngoi vi u c tin hnh nh vi mt nh trong b nh.

II.1.7 Cc mch Multiplexer, mch Decoder, mch PLA

Cc mch Multiplexer, mch Decoder hay mch PLA l nhng mch ph tr khng th thiu ca mt h Vi x l. Thng thng, cc mch Decoder v mch PLA (Programmable Logic Array) c thit k sn trn mt chip, c s dng nhiu trong cc mch gii m cc tn hiu iu khin, gii m a ch ca vng nh hay a ch thit b ngoi vi.

- Cc mch Multiplexer (hoc Coder)

Mch Multiplexer (cn gi l mch Coder)thng c xy dng theo mc ch s dng, c khi rt phc tp. Mt trong nhng v d l mch thu nhn v m ho bn phm (keyboard), c xy dng trn c s mt chip Vi x l chuyn dng, bao gm c phn cng ln chng trnh. S khi chc nng ca mt mch Multiplexer c th hin trn Hnh II.17. Cc tn hiu vo ring r x1, x2, x3 xn, qua x l s to ra mt t hp nh phn u ra {ymym-1y0}. Phn chuyn i t mt tn hiu vo xi thnh t hp ra {ymym-1 y0} c thc hin nh mch t hp logic hoc kt hp vi phn mm chuyn dng.



Hnh II. 23 S khi mt mch Multiplexer (coder)

- Mch gii m (Decoder)

Cc mch gii m thng thng 1/4, 1/8 c xy dng nh mt chip ph tr trong cc h Vi x l. C th k n nh mch gii m 1/16 SN74154, mch gii m 1/8 74138 v.v... Bng chn l ca mch gii m 1/8 nh sau:

E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

1 0 0 0 0 0 0 1 1 1 1 1 1 1

1 0 0 0 0 1 1 0 1 1 1 1 1 1

1 0 0 0 1 0 1 1 0 1 1 1 1 1

1 0 0 0 1 1 1 1 1 0 1 1 1 1

1 0 0 1 0 0 1 1 1 1 0 1 1 1

1 0 0 1 0 1 1 1 1 1 1 0 1 1

1 0 0 1 1 0 1 1 1 1 1 1 0 1

1 0 0 1 1 1 1 1 1 1 1 1 1 0

0 x x x x x 1 1 1 1 1 1 1 1

x 1 x x x x 1 1 1 1 1 1 1 1

x x 1 x x x 1 1 1 1 1 1 1 1

Hnh II.25 S ni chn mch gii m nh phn 1/8 v bng chn l

Vi mch gii m nh phn 1/8 c s ni chn nh Hnh II. 18. Khi vi mch gii m c "Enable", ng vi t hp cc gi tr E3E2E1 = 100, v vi bt k t hp no ca cc gi tr A2A1A0 u c mt li ra c gi tr LOW. ng vi li ra ny s l mt v tr hoc mt vng nh c chn, hoc mt thit b ngoi vi. i vi cc vi mch c chn CS (chip select), y l tn hiu chn v

thch hp.

- Mch PLA (Programmable Logic Array)

Mch PLA thc cht l mt chip nh ROM c ghi sn theo mt quy lut no



theo phng thc gii m mt t hp nh phn u vo. C ngha l ng vi mt nh l mt t hp gi tr theo mt quy lut gii m u vo, m u vo y chnh l a ch ca nh . Cc mch PLA thch hp vi nhng ni cn s dng b gii m vi s lng u vo ln hn 3.

II.1.8 Vi nt v lp trnh hp ng

Hp ng (Assembler) l mt cng c rt mnh c s dng trong vic pht trin m lnh ca cc h Vi x l v my vi tnh. Hp ng l chng trnh dch cc lnh gi nh (Mnemonics) v cc k hiu (symbols) thnh m my cho cc h vi x l v my vi tnh thc hin. Cn phn bit rng hp ng l mt chng trnh, ch khng phi l mt phn ca phn cng.

D liu vo ca hp ng l tp cc lnh gi nh, v d liu ra ca hp ng chnh l cc tp cc byte m my nh phn, m thc thi c nh a ch chnh xc trong khng gian nh chng trnh.

D liu vo c gi l m ngun (source code), d liu ra c gi l m thc thi hoc m i tng (object code). Qu trnh m ngun c dch thnh m i tng c gi l assembly. Cng c phn mm thc hin qu trnh ny gi l hp ng (assembler). C th thy rt d dng rng: vit mt lnh MOV A,M d nh hn rt nhiu so vi m hexa ca lnh ny: 7EH hoc m nh phn 01111110B

Hin c hai loi chng trnh hp ng ang c s dng rng ri: Hp ng thng tr (Resident Assemblers) - c ci t ngay trong h thng, v hp ng chuyn i (Cross Assemblers) khng c ci t ngay trong h thng, m l trong mt my ch khc. M chng trnh do my ch to ra t hp ng khng th chy c trn my ch.

Ngoi ra cn tn ti hai loi hp ng khc l hp ng tuyt i (Abssolute Assembler), v hp ng ti nh v (Relocatable Assemblers), s c gii thiu trong cc trnh hc hp ng sau ny.

II.3 Cu trc v tnh nng ca mt s chip V x l hin i.

Tri qua my thp k pht trin, cng ngh ch to cc chip Vi x l c nhng bc tin v bo. xut hin nhiu kiu cu trc chip Vi x l nh CISC (Complete Instruction-set Computer), RISC (Reduced Instruction- Set Computer), b x l scalar hay superscalar, Vi x l VLIW (Very Long Instruction Word), Vi x l Superpipelined, Vi x l Vector, v Vi x l biu tng (Symbolic P), nhm p ng nhu cu to nn nhng my tnh cc mnh, nhng siu my tnh, mainfram phc v nhng cng vic tnh ton ln hay to ra cc my tnh x l song song.

i vi h x86, c cc trung tm i486 vi cu trc RISC, tp lnh rt gn vi tc x l tng nhanh ng k. l nhng trung tm x l 32 bits thc s. Khng gian a ch vt l v khng gian b nh o c qun l bi 32 bits a ch, ln n



4Gbytes. Ngoi ra, cc b ng x l ton cng c tch hp to nn sc mnh ng k. Cc trung tm ny c s dng to nn nhng my tnh x l song song.vi cu trc hin i v kh nng tnh ton ln cho php gii nhng bi ton rt phc tp.

Nm 1992, chip x l Pentium MMX ra i, trong cu trc c ti hai ng ng song song (superscalar), hai khi s hc v logic (ALU) cho php thi hnh hai lnh my trong mt chu k. BUS ni b ca Pentium MMX l BUS 64 bits v 128 bits, tc trao i d liu vi b nh do vy c nng cao ng k. c bit, chip Pentium c mt vng nh gi l vng m ch r nhnh BTB (Branch Target Buffer) i vi 256 lnh r nhnh mi. Pentium cng c tch hp mt b ng x ton hc (Mathematical Coprocessor) vi hiu sut rt cao nh gii thut nhnh hn. D l loi Vi x l CISC, nhng Pentium ng dng ging nh cc loi Vi x l RISC tc cao: x l ng ng, cu trc superscalar v d on r nhnh.

Nm 1999, chip Pentium PIII ra i vi cu trc c thm 70 lnh cho truyn thng a phng tin, tc xung nhp vt qua ngng 1 GHZ. Tip theo l cc chip Pentium PIV vi tc cao hn hn v cu trc a phn lung.

IBM cho bit h ang p dng nhng phng php sn xut mi nhm cho php thit b x l dnh cho my ch Power6 c th chy nhanh gp hai ln so vi hin nay nhng vn m bo yu cu v nhit .

Theo thng tin t Gim c k thut ca IBM, h khng ch thu nh kch c cc bng bn dn (transistor) m cn thay i phng thc hot ng ca silicon khi t lp cch in pha di mt lp silicon gm khong 500 nguyn t.

Nhng ci tin khin Power6, sn xut theo ng ngh 65 tm v d nh ra mt gia nm 2007, t xung nhp ti 4 - 5 GHZ. IBM khng nh Power6 s cnh tranh trc tip vi sn phm ca cc i th th lntel, AMD v Sun Microsystems.

Ngay khi lntel gii thiu cng ngh 90 nm nm 2003, ngi ta nhn thy n gy ra tnh trng tht thot nng lng nghim trng hn nhng phng php sn xut trc , khin chip ta nhit ngay

c khi chng khng chy ht cng sut. Mt trong nhng bin php khc phc l tch hp 2 li x l trn mt chip n v gim xung nhp hot ng tng kh nng vn hnh cng nh trnh rc ri do nhit cao. Ngc li, Power6 c xy dng hot ng xung nhp cao cha tng thy nhng vn tiu th in nng hiu qu.

Hin nay, lntel cng ang nghin cu hai k thut sn xut v thit k mi nhm gim lng in tiu th trn bng mch h thng. Phng php th nht cung cp ngun in p cho c CPU v b nh m (ca che) cn cch th hai s tch hp b



iu ha in p trn cc transistor.

Th t, 21/6/2006, 10:04 GMT+7 C~JC~ IBM Pht trin chia 500 GHZ

"Big Blue" v Cng ty Georgia Tech cng ch to mt chip c xung nhp cao hn 100 ln so vi k lc ca thit b x l my tnh hin nay, vi iu kin n phi hot ng nhit nghe c v phi thc t - 268,50C.

nhit trong phng, chip ny vn t tc 350 GHZ, tng ng 350 t vng/giy, nhanh hn nhiu so vi thit b x l my tnh ti thi im ny (dao ng t 1,8 GHZ n 3,8 GHZ).

y l mt phn d n khm ph tc ti a ca cc chip silicon-germani (SiGe). SiGe cng ging nh cng ngh chip silicon khc nhng c tng cng nguyn t germani nng hiu sut v gim lng in tiu th. Trn l thuyt, SiGe c th m rng tc ln 1 terahertz (THZ), tc mt nghn t vng mi giy.

Tuy nhin thm thnh phn germani ng ngha vi chi ph sn xut tm wafer tng cao, do SiGe rt kn chn th trng. IBM bn ra hng trm triu chip ny t nm 1998, nhng cha th ch ni khi so vi con s hng t chip silicon mi nm nh sn lng in thoi di ng.

Chip SiGe hiu sut ln s c ng dng trong cc h thng phng th, phng tin khm ph v tr v thit b cm ng t xa.

II.3.1 Cu trc chip Vi x l Pentium

Pentium l loi n v x l trung tm 32 bit v l loi n v x l trung tm u tin s dng k thut ILP (lnstruction Level Pararellism), k thut x l lnh song song.

K thut ng ng v k thut x l lnh song song ILP

Mt lnh thng c x l qua nm giai on:

1. Nhp lnh (FI Fetch the Instruction)

2. Gii m lnh (DI Decode the Instruction)

3. To a ch ton hng (GOA Generate Operand Address)

4. Nhp ton hng (FO Fetch Operands)

5. Thc hin lnh (EI Execute Instruction)

Vi k thut x l lnh thng thng, n v x l trung tm phi tun t thc hin xong tt c cc giai on thc hin mt lnh, thng l sau 5 chu k my, ri mi chuyn sang nhp v thc hin lnh tip theo. D tng tc x l lnh m khng nht thit phi tng tn s nhp ca my, ngi ta s dng cc k thut khc nh k thut



x l lnh kiu ng ng (Pipeline) v k thut x l lnh song song (ILP).

K thut x l lnh kiu ng ng (Pipeline) K thut x l lnh kiu ng ng c s dng trong cc n v x l trung tm

t i n v x l trung tm Intel 8086.

Chu k my

ng ng tng t nh dy chuyn sn xut nhiu cng on. dy chuyn sn

xut, mi cng on thc hin mt thao tc sn xut. Sn phm c c chuyn v hnh thnh dn sau mi cng on sn xut, cho n khi c hon thnh cng on cui cng. Trong k thut x l lnh theo kiu ng ng, vic thc hin lnh cng c thc hin qua 5 thao tc, mi thao tc c thc hin trong mt giai on, giai on n tip sau giai on kia, cho n khi thc hin song lnh. Vi mt ng ng 5-giai on, ti mi chu k my c 5 b d liu thuc 5 giai on x l c gi vo ng ng v 5 thao tc c thc hin ng thi, nh vy m sau mi chu k my li c mt lnh c hon thnh v mt lnh mi c nhp. K thut ng ng vi ng ng 5-giai on cho php tng tc thc hin lnh ln gp 5 ln. K thut ILP (x l lnh song song)

K thut ILP l k thut thit k n v x l trung tm v chng trnh dch nhm lm tng tc cc thao tc my (nh ghi-c b nh) v thc hin cc php tnh. Trong cc k thut ILP c k thut superscalar, trong ti mt chu k my nhiu lnh c nhp v c thc hin ng thi trn nhiu ng ng khc nhau.

Pentium l loi n v x l trung tm c thit k theo k thut superscalar, trong hai lnh c nhp v gii m ng thi. Pentium c hai ng ng thc hin lnh song song U v V. Qu trnh thc hin lnh c m t nh sau:



Hnh II. 26 Cu trc trung tm Vi x l Pentium

Pentium l n v x l trung tm loi 32bit v l n v x l trung tm loi CISC (Complex Instruction St Computer) vi c im: h lnh phc tp, nhiu kiu xc nh a ch, nhiu khun dng lnh v nhiu kch thc lnh khc nhau.

Pentium c BUS a ch trong v ngoi 32 bit, BUS d liu trong v ngoi 64 bit. Pentium c hai cache 8 Kbyte c lp: mt cache 8 Kbyte 2 cng dnh cho d liu v mt cache 8 Kbyte cha lnh. Pentium c hai ng ng thc hin lnh song song U v V, v 2 n v s hc-logic ALU. Pentium c mt ng ng ring thc hin cc lnh du phy ng v mt b ng x l du phy ng FPU c tch hp trong chip.

Pentium c cc thanh ghi sau:

Cc thanh ghi h thng:

- Cc thanh ghi iu khin 32 bit: CR0, CR1, CR2, CR3

- Cc thanh ghi h thng qun l b nh:

GDTR: Thanh ghi bng m t ton cc (Global Descriptor Table Register)

LDTR: Thanh ghi bng m t cc b (Local Descriptor Table Register)

IDTR: Thanh ghi bng m t ngt (Interrupt Descriptor Table Register)

TR: Thanh ghi nhim v (Task Register)



- Cc thanh ghi on 16 bit:



II.3.2 Cu trc RISC, CISC

RISC: (Reduced Instruction-set Computer)

CISC: (Complete Instruction-set Computer)



Cch n gin nht c th kho st nhng u nhc im ca kin trc IUSC l so snh vic thc hin mt php ton i vi loi kin trc CISC trc y. Gi s ta phi thc hin mt lnh nhn hai ton hng c lu gi trong b nh.

Hnh II.... m t t chc ca mt my tnh. B nh c to t cc nh t 1: 1 (hng 1: ct 1) n 6:4 (hng 6: ct 4). Khi thc hin lnh c nhim v thc hin cc lnh tnh ton x (nhn),: (chia), + (cng) v - (tr). Tt nhin, khi thc hin tnh ton ch c th lm vic vi cc d liu (ton hng) c cha sn mt trong cc thanh ghi A, B, C, D, E hoc F. Gi s ta phi tm tch 2 s, s th nht c cha 2:3 v s th hai 5:2, kt qu s c lu li vo 2:3. By gi ta s tip cn cch gii quyt vn trn hai loi CPU, CISC v RISC.

Trn CPU CISC: u tin hng u ca loi CPU ny l hon thin mt cng vic vi t lnh nht c th. iu ny c th thc hin nh vo vic xy dng mt phn cng CPU c kh nng hiu c v thc hin c mt chui cc tc nghip. Trong trng hp c th ny, CISC s c mt lnh xc nh duy nht, tm gi l MULT, m khi thc hin, lnh s np hai gi tr ton hng vo 2 thanh ghi sau thc hin php nhn ri ghi kt qu vo mt thanh ghi tng ng. Nh vy cng vic s c th hin bng mt lnh nh sau:

MULT 2:3,5:2

Lnh MULT l mt lnh hon thin (complex). Lnh lm vic trc tip trn bng nh ca my tnh, ch khng cn ngi lp trnh phi dng lnh gi hay np ni dung, ghi ni dung vo nh. Lnh rt gn vi ngn ng bc cao. Gi s ta gi "a" l gi tr ca ton hng trong nh 2:3 v "b" l gi tr ton hng trong nh 5:2, th lnh tng ng trong ngn ng C l "a = a * b u im ln nht ca h thng CISC l chng trnh dch phi lm rt t vic khi dch mt chng trnh, hay mt lnh ca ngn ng bc cao sang ngn ng my. V di ca m lnh rt nh, nn h thng cng cn t RAM hn ghi nh lnh. D nhin, vic thit k cu trc loi CISC c bit s phi tch hp cc lnh hon thin bng phn cng.

Trn CPU RISC: Cc CPU loi RISC ch s dng cc lnh (lnstruction) c th thc hin c trong mt chu k xung nhp. Nh vy lnh MULT c m t phn trn phi c chia thnh 3 lnh nh hn. LOAD chuyn d liu (ton hng) t nh vo thanh ghi; PROD" thc hin php nhn hai ton hng c lu gi trong cc thanh ghi, v lnh "STORE" s thc hin vic chuyn kt qu tnh ton ghi vo nh. thc hin c php nhn hai ton hng, ngi lp trnh phi m ho thnh 4 lnh nh sau: LOAD A, 2:3

LOAD B, 5:2

PROD A, B

STORE 2:3, A



C th thy rng vi cu trc RISC, khng thun li lm cho hon thnh php ton nhn hai s v phi vit nhiu dng lnh hn, cn nhiu RAM hn lu gi cc lnh mc assembly. Chng trnh dch cng phi phc hin nhiu vic hn chuyn i cc lnh ca ngn ng bc cao sang m my. Th nhng, chin lc RISC mang n nhiu thun li quan trng. V mi lnh ch cn mt chu k xung nhp thc hin, ton b chng trnh cng s ch cn s chu k xung nhp nh khi thc hin lnh MULT h thng CISC. Nhng kin trc RISC vi h lnh rt gn cn t linh kin v khng gian cho mch tch hp, b qua c cc thanh ghi a nng. Hn na, mi lnh ch thc thi trong mt chu k xung nhp nn vic t chc ng ng cng n gin hn nhiu.

Vic tch lnh "LOAD" v lnh "STO

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