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Kingtron Electronics Co.,Ltd.晶強電子股份有限公司
COF Presentation (I)COF Presentation (I)
1.Address: No.32,Kuang Fu North 1.Address: No.32,Kuang Fu North Road,HuRoad,Hu Kou,Kou,ShinShin--ChuChu Industrial Industrial Park,ShinPark,Shin--Chu,TaiwanChu,Taiwan R.O.C.R.O.C.新竹工業區光復北路新竹工業區光復北路3232號號
Tape Structure 3 layer tape G 2 layer tape EFlex structure Flex slit required Flexible by itself. No flex slit required. Patterning under die with flying lead G No flying lead and no pattern shape limit for design E
Fine patterningup to45 um min.Limit at 40 um with 15 um copper
GUp to 30 um. (8 um copper)Limit at 25 um.
E
Chip shrink up to 45 um pad pitch G Less than 30 um pad pitch is possible E
Tape shrink Tends to become larger as parallelpattern run at flex slit.
GFlexible patterning allowed as SEC's gate driver.Fanning out of pattern throughout the tape face isallowed. These will results saving tape size.
E
Tolerance+-0.09% due to residual stress inlamination.
G +-0.05% for stress-free process for non-lamination. E
Lead breaking at flexSn-void and/ir attack to copper for platingafter SR coating. (Preplating is available.)
G No worry for preplating process. E
Bending strength 50 times (S-C-Flex) G 80 or more times; can be bend at 180o small angel EOverall realibility Field proven for years. E Equal or more to TCP. E
Package design being standard in the industry. GLighter, thinner, smaller design than of TCP ispossible.
E
Mother board connection ACF or soldering connection. E ACF connection. Soldering will be difficult. G
Singluation (stamping) 75 um (PI) + 18 (15) um (Cu) E New stamping technology can be implemented byuser for 38 um (PI) with 8 um (Cu) tape.
G
Tape feed 75 um (PI) + 18 (15) um (Cu) EA new feeding technology required for 38 um (PI)with 8 um (Cu) tape. It can be implemented easlily.
G
Tape TAT 2 Wks G 1 Wk E
Tooling charge Device hole tooling is required. G No device hole tooling. (samples, photo mask and SR setup.) No alignment hole required. E
Application Matured products E Big growth up in Japan and Korea ECost impact for fine pitch Fine pitch tape is more expensive. F There will be no big impact to price for finer pitch. E
Flexibility : Need slit hole Bending no limit Curve bending ---Multi-layers : One layer One or Two layer 2~4 layer Multi-layersFlying Lead : OK --- OK ---Fine pitch : 45um 30um 150~200um 150~200umFormat : Reel Reel or Piece Piece Piece
Substrate : Substrate : TAB TAB COF COF FPC FPC PCB PCB _ _ Finish Plating : Finish Plating : Tin Tin TinTin or Ni/Au Solder or Ni/Au Solder or or Ni/Au Solder or Ni/Au Solder or Ni/AuNi/Au
Flexibility Flexibility : Need slit hole Bending no limit Curve bending : Need slit hole Bending no limit Curve bending ------MultiMulti--layers : One layer One or Two layer 2~4 layers : One layer One or Two layer 2~4 layer Multilayer Multi--layerslayersFlying Lead : OK Flying Lead : OK ------ OK OK ------Fine pitchFine pitch : 45um 30um : 45um 30um 150~200um 150~200um 150~200um150~200umFormat : Reel Format : Reel ReelReel or Piece or Piece PiecePiece PiecePiece
TAB Eutectic bonding
TAB Eutectic bonding
TAB ACF bondingbonding
TAB + FPC soldering
TAB + FPC soldering
TAB ACF
COF SMT assembly
COF SMT assemblyFPC SMT
assemblyFPC SMT assembly FPC + COF
solderingsolderingFPC + COF
COF Eutectic (or ACF) bonding
COF Eutectic (or ACF) bonding
COF ACF bonding
COF ACF bonding
COG ACF bonding
COG ACF bonding
COF + PCB soldering (or
ACF bonding)
COF + PCB soldering (or
ACF bonding)
Power IC
Memory IC
Passive
Driver IC
Driver IC
COG
COF
COF (30um)
TCP (45um)
Low Cost solutions for LCD driver IC Low Cost solutions for LCD driver IC
SoC solutionsolutionSoCSoC solution整合數顆周邊IC,降低IC總成本 IC 變大
Driver ICDriver IC
Fine line solutionFine line solutionFine line solution使用細線路製造,增加每片晶圓的IC產生量,降低每顆IC成本
IC 變小線路變密
Low Cost and Short Lead timeLow Cost and Short Lead time
Alignment hole
Flexible to 2-layer COF
設計重點:
1. 1. No alignment holeNo alignment hole→ 能夠不設計alignment hole最佳(利用Tape透光的
特性,設計無實孔的孔環),可省模具費(~NT20萬)及縮短交期(10~14天)
2. 2. Tin Plating instead of Gold platingTin Plating instead of Gold plating→ 鍍錫為化學錫,不需拉導線及切導線,易於線
路設計縮小tape面積,可省鍍金成本及二次衝孔的模具費用並可縮短交期。
→ 若考慮面板及PCB端需鍍金及信賴性考量而無法避免二次衝孔,建議使用選擇性鍍金鍍錫板
3. 3. Eutectic bonding for ILBEutectic bonding for ILB→ 採用錫金共晶的方式,產品信賴度高且省去使
用昂貴的ACF材料成本,尤其對於大面積的SoC 晶片,效果驚人。
4. 4. Fine line/Fine pitch/Flexible designFine line/Fine pitch/Flexible design→ 多利用COF的製程能力特性,將線路設計於
Min. Pitch:Min. Pitch: Line Width/Line SpaceLine Width/Line Space/Etch Factor/Etch Factor
T
H
B
Line Space (L/S )
Line Width (L/W)
Cu
PI film
Etch Factor = 2H/(B-T)
H
T
B
1. Min. Pitch = 30 μm (for copper = 8 μm)(Line Width = 15 μm,Line Space = 15 μm)
2. Min. Line Width = 5 μm (Line Top)
3. Min. Line Space = 15 μm (On PI film)
4. Etching Factor > 2.5
1. Min. Pitch = 30 μm (for copper = 8 μm)(Line Width = 15 μm,Line Space = 15 μm)
2. Min. Line Width = 5 μm (Line Top)
3. Min. Line Space = 15 μm (On PI film)
4. Etching Factor > 2.5
COF tape for Car TV COF tape for Car TV –– 38um pitch38um pitch
2
1
34,5,6
7
Key Items:[1] Total Pitch Tolerance (1,2,3) [2] Inner lead pitch capability (4) [3] Solder Resist position and bleeding control (5) [4] Tin plating – tie coat treatment (6) [5] Sprocket hole pitch and deformation (7) [6] Yield rate improvement
Key Items:Key Items:[1] Total Pitch Tolerance (1,2,3) [2] Inner lead pitch capability (4) [3] Solder Resist position and bleeding control (5) [4] Tin plating – tie coat treatment (6) [5] Sprocket hole pitch and deformation (7) [6] Yield rate improvement
Inner Lead and Solder ResistInner Lead and Solder Resist----(38um pitch)(38um pitch)