K K i i n n g g F F a a h h d d U U n n i i v v e e r r s s i i t t y y o o f f P P e e t t r r o o l l e e u u m m & & M M i i n n e e r r a a l l s s College of Computer Sciences and Engineering Department of Computer Engineering L L A A B B M M a a n n u u a a l l : : C C O O E E 2 2 0 0 3 3 : : D D i i g g i i t t a a l l L L o o g g i i c c L L a a b b o o r r a a t t o o r r y y ( ( 0 0 - - 3 3 - - 1 1 ) )
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Review of Digital Logic Design: Design of Combinational Circuits, and Design of Sequential Circuits. Logic implementation using discrete logic components (TTL, CMOS), and programmable logic devices. Introduction to Field Programmable Logic Arrays (FPGAs). The basic design flow: design capture (schematic capture, HDL design entry, design verification and test, implementation (including some of its practical aspects), and debugging. Design of data path and control unit.
Grading Policy:
Lab Work 75% Reports 25%
Lab Work Grading Details (out of 100):
Integrating the design: 40 Timing Simulation: 20 Compiling, Bit-file Generation: 05 Verifying on the board: 10 Lab Report*: 25
* Students are recommended to refer to the writing skills improvement material (provided below as links) early in the semester so as to effectively implement suggested improvements in their reports.
CCOOEE 220033 SSyyllllaabbuuss
COE 203 Syllabus
Page 2 COE 203 Syllabus
Course Objectives:
After successfully completing the course, students will be able to:
1. Design combinational and sequential circuits using discrete components and FPGAs to meet certain specifications.
2. Design and conduct experiments related to digital systems and to analyze their outcomes.
Course Learning Outcomes and Indicators:
Course Learning Outcomes
Outcome Indicators and Details Assessment
Methods and Metrics
Min. Weight
O2. Ability to design and conduct experiments related to digital systems and to analyze their outcomes.
Design & conduct experiments on ripple carry adders, ALU, data & control unit, and learn how to implement on FPGAs.
Lab work 5%
O4. Ability to function as an effective team member
Working in a team to design a digital system and learn how to fast prototype using FPGAs.
Lab work & project
5%
O6. Ability to use design tools for Implementing digital circuits on FPGAs
Ability to use tools and discrete components, FPGAs, to model, simulate and implement digital circuits.
Lab work 5%
Weekly Breakdown of Lecture Course Material
Week Topics
1 Lab Introduction, bread boards, FPGA boards, policies, overview of experiments, reporting, team-work, attendance, grading, etc.
2
(Experiment 1) Introduction • Introduction to Boolean Logic and Gates • ICs and IC pins (Input, Output, I/O, Vcc/Vdd, Vss/GND • Truth tables of Inverter, AND, OR, XOR • Tools and equipment • BreadBoard and verification of Truth Table of above gates
Writing Skills Presentation to be delivered in the Lab. (Based on Instructor Discretion 1 presentation is to be selected out of 3 provided below as links)- Talk will last for roughly 30 minutes
COE 203 Syllabus
Page 3 COE 203 Syllabus
3
(Experiment 2) Prototyping of Logic Circuits using Discrete Components • Binary addition and Full adder Circuit Truth Table (Bread boarding) • Building 4-bit adders using 4 cascaded Full adders (Concept, no Bread
boarding) • ALU operation/capabilities • Verification of 4-bit adder operation using the ALU (Bread boarding) • 8-bit Full adder by cascading two ALUs
4
(Experiment 3) Introduction to FPGA • Introduction to FPGAs & Capabilities • Synthesis Flow in FPGAs and Demos for the tools to be used, e.g. schematic
capture &Simulation • Half adder experiment on FPGA board
5 No LAB PROBLEM SOLVING SESSION (Major 1 Week)
6
(Experiment 4) Creating and Using Symbols • Use FPGA tools to build:
a. Half-Adder b. Full adder using 2 HA’s + OR gate c. 4-bit Adder using 4 full adders
• Simulation should be performed and circuit downloaded and tested after developing each macro/symbol
7
(Experiment 5) Introduction to Sequential Circuits • Introduction to sequential circuit • Mod-16 counter • Use of push button for manual clock and bouncing problem. • Solution of bouncing problem. Introduction of debouncing Verilog
code/block • Introduction to LCD files. Use the LCD display to display counter contents (2
Digits)
8
(Experiment 6) Clock and Clock Frequency • Concept of clock and clock frequency • Counters as frequency dividers • Use Oscilloscopes to watch input frequency (on-board 50 MHz and the four
outputs of the counter) • Counter cascading to obtain larger counts • Choose a suitable (divide by x) counter to Generate a ≈ 1 Hz clock • Connect 3-LEDs to output of a 2x4 decoder whose input comes from a 2-bit
counter clocked by: a. The ≈0.75 Hz clock b. A ≈3 Hz clock c. A ≈20 Hz clock
COE 203 Syllabus
Page 4 COE 203 Syllabus
9
(Experiment 7) Building a Timer Circuit • Learn the difference between synchronous and asynchronous counters • Learn how to use count enable and carry-out signals • Build synch/asynch Modulo-10 counter • Build Modulo-6, Modulo-12 and Modulo-60 counter • Build 1Hz and 1 KHz pulse generator • Build hours, minutes, seconds timer • Use of LCD to display timer
10 No LAB PROBLEM SOLVING SESSION (Major 2 Week)
11
(Experiment 8) Reaction Timer Part 1 –Generating Random Delay • MSI parts: flip-flop, register, shift register, down counter • Use the datapath and control unit design method • Use frequency dividers to count time units • Generate random numbers using Linear Feedback Shift Register (LFSR)
12 (Experiment 9) Reaction Timer Part 2–Response Time • Saturating BCD counter • Comparing BCD numbers
13
(Experiment 10) Reaction Timer Part 3–The Control Unit and Integration • States and finite state machines (FSM) • Design a control unit as an FSM • Integrate the design to a full reaction timer
14 (Experiment 11) Reaction Timer Part 4–Challenging The Player • MSI parts: decoder, encoder and priority encoder • Extending the datapath without affecting the control unit • Managing different inputs and outputs
15 No LAB PROBLEM SOLVING SESSION (Final Week)
ABET Curricular Action to improve
the Writing
Skills
The Lab instructor is kindly requested to carry out the following actions: 1. Inform the students that their English Writing Skills will be given
10%
2. Request the students to follow the below attached template.
of overall Lab grades based on returned lab assignments and lab project reports.
1. Template for Lab assignments 2. Template for Project Report
3. Request the students follow the below listed writing skills guidelines:
ALU (Arithmetic Logic Unit) operation/capabilities
Verification of 4-bit adder operation using ALU
Building 8-bit adder using 2 cascaded 4-bit adders (2 ALUs)
Material Required
ICs – 7408, 7432, 7486, 74181
Wires
Wire Stripper
Prototyping board with power and ground connections
IC Tester
Design Specifications
You will construct a full adder circuit. The full adder is a common circuit used in many
designs both small and large (including processors). The function of the full adder is quite
simple – add three, one-bit numbers. This may seem like a simple process, but the full
adder is designed to be cascaded to compute addition on (arbitrarily) larger numbers.
Your circuit must have three inputs, A, B, and Cin and two outputs, Sum and Cout. The
block diagram is shown in Figure 2.1 below:
EExxppeerriimmeenntt 22::
Full
Adder
Sum
Cout
A
B
Cin
Figure 2.1: Block diagram of the Full adder circuit
Experiment 2: Prototyping of Logic Circuits using Discrete Components
Page 2 Experiment 2
Following is the truth table of Full adder circuit:
A B Cin Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Table 2.1: Truth Table of Full Adder
By simplifying the two outputs Sum and Cout using any minimization scheme (K-Maps, Boolean algebra, etc), you will get:
Sum= A ⊕ B ⊕ Cin
Cout = AB + ACin + BCin
Now implement the above two simplified Boolean equations on the breadboard using discrete components. The circuit diagram will be as follows:
Figure 2.2: Circuit diagram of the Full adder circuit
Experiment 2: Prototyping of Logic Circuits using Discrete Components
Page 3 Experiment 2
Procedure
This experiment will be developed in 2 main parts plus one bonus• In part 1, a 1-bit full adder circuit will be implemented.
part:
• In part 2, a 4-bit adder circuit will be built using an ALU. • In part 3 (bonus), an 8-bit adder circuit will be built by cascading two ALUs.
Part I – In this part, a 1-bit full adder circuit will be built. • Get the proper ICs (AND, OR, XOR) from the shelves. • Test the ICs on the IC tester. • Place the chips on the breadboard carefully. • Connect the Vcc pins of the chips to the +5V on the board. • Connect the GND pins of the chips to the GND on the board. • Build your logic diagram by making appropriate connections as shown in Figure 2.2 • Use 3 switches for the 3 inputs A, B, and Cin. • Connect the two outputs Sum and Cout to 2 LEDs. • Use the switches on the board to verify your circuit.
The circuit of a Full adder can be cascaded to build a 4-bit adder as shown (below) in Figure 2.3.
Part II– In this part, a 4-bit adder circuit will be built using an ALU. To avoid too many wiring, we will use the 4-bit adder as one of the available functions of ready made 4-bit ALU.
• Now use 74181 ALU on the breadboard. • Connect Vcc and Gnd of 74181 to +5V and GND of the board respectively. • Connect the four As (A3 A2 A1 A0) of 74181 to four switches. • Connect the four Bs (B3 B2 B1 B0) of 74181 to other four switches. • Connect M (mode) to the Gnd of the board. • Connect CR to the Vcc of the board. • Connect the four outputs F3 F2 F1 F0 of 74181 to the four LEDs. • Connect C (Carry out) to another LED. • Check the addition operation of 74181 ALU by making the select lines S3 S2 S1 S0
as 1 0 0 1 (fix these values by connecting S3 and S0 to +5V while S2 and S1 to GND)
• Change the values of the A and B switches and verify the result on the LEDs.
Figure 2.3: Block diagram of a 4-bit adder circuit.
C4 C3 C1 C2
Full Adder
Full Adder
Full Adder
Full Adder
A3 B3 A2 B2 A1 B1 A0 B0 C0
S0 S1 S2 S3
Experiment 2: Prototyping of Logic Circuits using Discrete Components
Page 4 Experiment 2
Part III (Bonus) – In this part, an 8-bit adder circuit will be built by cascading two ALUs.
• Extend your design to 8 bit adder circuit by cascading two 74181 chips and connecting the carry out (C) of the first to carry in (CR) of the second ALU. Join select lines and M of both chips together.
• Fix the select lines of both ALUs S3 S2 S1 S0 to 1 0 0 1 for addition function and M to Gnd of the board as in Part II.
• The first ALU will serve as lower nibble (half byte 4 3 2 1) and second ALU will serve as higher nibble (half byte 7 6 5 4).
• Due to limited number of switches, connect eight As (A7 A6 A5 A4 A3 A2 A1 A0) to eight switches.
• Connect eight Bs (B7 B6 B5 B4 B3 B2 B1 B0) to fix values (by connecting +5V and GND) like 00110011.
• Connect the eight outputs F7 F6 F5 F4 F3 F2 F1 F0 of 74181 to the eight LEDs. Leave the carry out (C) of second ALU unconnected as no LED will be left.
• Change the values of As switches and verify the result on the LEDs.
Table 2.2: Function Table of 4-bit ALU (74181)
Lab Report
Print the lab report format and write a complete lab report on this printed document about this experiment as mentioned in the document.
Experiment 2: Prototyping of Logic Circuits using Discrete Components
Page 5 Experiment 2
181 4-Bit ALU
Experiment 3: Introduction to FPGA
Page 1
Experiment 3
IInnttrroodduuccttiioonn ttoo FFPPGGAA
Objectives
In this experiment, you will:
Get introduced to FPGA board
Get familiar with the ISE design suite and the ISim simulator
Learn how to make design entry and bind I/O board switches and LEDS
Design, simulate, and verify simple logic gates on board
Material Required
Spartan 3A board
ISE design suite software
Design Specifications
In this experiment, you will be familiarized with the FPGA boards available in the lab. FPGA
stands for Field Programmable Gate Array, which is a programmable chip that allows you
to test and run, complicated logic designs.
The FPGA board used in this lab is the Xilinx Spartan3A board. The design process starts
with design preparation of the required logic circuit. Using ISE Design Suite, you will be
able to:
enter the design using schematic drawing
simulate the design to verify its functionality
download the configuration bits file of the verified design to the FPGA
verify the design on board
In this lab, you will make a design entry of a Half Adder. Then you will verify its functionality
using the behavioral simulator ISim. Finally, you will assign the I/O (Input/Output) of the
design to physical switches and LEDs of the board and program it.
EExxppeerriimmeenntt 33::
Experiment 3: Introduction to FPGA
Page 2
Experiment 3
Procedure
The procedure of this lab will be developed in 7 main parts;
1. In part 1, you will create and setup the project files and parameters in ISE design
suite software.
2. In part 2, you will enter the design using Schematic drawing.
3. In part 3, you will simulate the design and verify its functionality.
4. In part 4, you will connect the inputs and outputs of the circuit to input and output
pins in the FPGA board.
5. In part 5, you will generate the configuration bits file of the design.
6. In part 6, you will generate and analyze the post-place and route timing report.
7. In part 7, you will download the design configuration bits file to the FPGA board.
1. Create a New Project
The objective here is to setup the project files and parameters. A project in ISE is a
collection of all the files needed to create and download a design to the selected FPGA
device. The project will be adapted to use the FPGA available on our board. The project
allows us to draw a schematic as the main way of entering the design. Here are the steps
for creating a new project:
1. Launch Xilinix ISE design Suite software
2. Select File, New Project.
3. In the New Project Wizard dialog box, type the desired location in the Project
Location field, or browse to the directory under which you want to create your new
project directory using the browse button next to the Project Location field.
4. Enter “lab3” in the Project Name field. When you enter “lab3” in the Project Name
field, a lab3 subdirectory is automatically created in the directory path in the Project
Location field.
5. Use the pull-down arrow to select Schematic from the Top-Level Source Type field.
Click in the field to access the pull-down list.
6. Click Next.
7. In the New Project Wizard Device and Design Flow dialog box, use the pull-down
arrow to select the Value for each Property Name. Click in the field to access the pull-
down list. Make sure the values are as follows:
● Device Family: Spartan3A and 3AN
● Device: XC3S700A
● Package: fg484
● Speed Grade: -4
● Top-Level Module Type: Schematic
● Synthesis Tool: XST
● Simulator: ISim
● Preferred language: VHDL
8. When the table is complete, your project properties should look like Figure 1.
Experiment 3: Introduction to FPGA
Page 3
Experiment 3
Figure 1: Project Properties
9. Click Next.
10. Click Finish to create the project. A summary of the project will be shown as in Figure 2.
A new project called lab3 is created and is shown on the left side panel under
implementation tab.
Figure 2: Summary of the Project
11. Right click on lab3 project and choose New Source. Select Schematic from the box on
the left and type in a file name for your project such as “halfadder”. Click Next. Click
Finish. A new Schematic file is created, click on symbol tab to show different symbols
and logic gates
Experiment 3: Introduction to FPGA
Page 4
Experiment 3
2. Schematic Design Entry
The objective here is to enter the design using Schematic drawing. You will design a simple
half-adder using AND and XOR gates as follows,
1. Add a 2 input AND gate as follows,
● From the toolbar go to Add, click on Symbol. Or click the Add Symbol icon in the
vertical toolbar to the left of the workspace (Looks like a gate with a resistor below
it). Or simply click on symbols tab in the bottom of the design panel
● Select Logic from the list of Categories
● Select and2 from the list of Symbols
● Place one AND gate on the schematic. Click the left mouse button to place the gate
on the schematic where the cursor sits
● Press Esc to exit Add Symbol mode and restore your select tool
2. Add a 2 input XOR gate as follows,
● Select Logic from the list of Categories.
● Select xor2 from the list of Symbols.
● Place one XOR gate next to the AND gate on the schematic. Click the left mouse
button to place the gate on the schematic where the cursor sits.
● Press Esc to exit Add Symbol mode and restore your select tool
3. Adjust your view using the Zoom option (View, Zoom, In) and the scroll bars in the
schematic window
4. Add I/O Markers:
I/O markers are needed by the design tool to synthesize the design. They give a logical
connection for the synthesis tool to understand that the internal signal will be passed
outside either the chip or schematic. It is very important that the correct type of I/O
marker be used. Putting an input I/O marker on an output pin will cause an error.
Fortunately, ISE will automatically decide if the maker is input or output when it is
connected to the pin.
● Select Add, I/O Marker. Or click the Add I/O Marker icon from the vertical menu
bar
● Add input markers to the AND and XOR gates as follows,
○ Place the cursor, which now displays the input graphic, at the end of the input
wire
○ To rename the I/O Marker, double click on the I/O marker and chose Nets from
the left side. Type the name of the marker in the Value of the Name attribute. Or
Right Click and choose Rename port
○ Name the input markers of the AND gate A and B
○ The input graphic is added to the end of the wire, around the net name
● Wire the inputs of the AND gate to the inputs of the XOR gate
○ Select Add Wires from the vertical menu bar, and connect input I/O markers to
the XOR gate as shown in Figure 3
Experiment 3: Introduction to FPGA
Page 5
Experiment 3
● Add an output marker to the output of the AND gate and another to the output of
the XOR gates
○ Select the Add an output marker radio button on the Options tab.
○ Place the cursor, which now displays the output graphic, at the end of
the output wire.
○ Name the output marker of the AND gate C and the output of the XOR
gate S
Figure 3
Your schematic is complete. Save the schematic diagram using File -> Save or press on the
Save icon on the toolbar.
3. Behavioral Simulation
The objective here is to simulate the design to verify its functionality. ISE provides an
integrated simulation flow with the ISim simulator that allows simulations to be run from
the Xilinx Project Navigator GUI. We introduce the concept of simulation and how to verify
the function of a circuit through behavioral simulation.
1. In the project navigator to the left, click on the Design tab, then click on your
schematic file. Change to the simulation mode by selecting the Simulation radio
button as shown in Figure 4.
Figure 4
Experiment 3: Introduction to FPGA
Page 6
Experiment 3
2. Press on the + mark in front of ISim Simulator to expand the list. Right click on the
Simulate Behavioral Model and choose Process Properties to change simulation
attributes. Uncheck the mark in front of Run for Specified Time. This will not limit
the simulation for a specific run time. Press OK.
3. To run the simulation, double click on Simulate Behavioral Model, or right click
and press Run.
4. ISE will launch ISim in a separate window. If it didn’t, refer to the lab manual to
check the error logs and how to correct them. Note that the simulation will fail to
run if a current process of ISim is working, close any instance of ISim before running
any simulation.
5. ISim will launch automatically. The wave window displays the signals, buses and
their waveforms. Note that there are four signals shown; A, B, S, and C.
Figure 5
6. Right click on input A in the objects window, and choose Force clock. Add the
following values:
a) Leading Edge Value: 0
b) Trailing Edge Value: 1
c) Period: 1 us
7. Alternatively, you can write the following Tcl command in the console window:
a) isim force add A 0 -value 1 -time 500 ns -repeat 1 us
8. Similarly, right click on input B in the objects window and choose Force clock. Add
the following values:
9. Alternatively, you can write the Tcl command in the console window,
a) Leading Edge Value: 0
Experiment 3: Introduction to FPGA
Page 7
Experiment 3
b) Trailing Edge Value: 1
c) Period: 0.5 us
10. Alternatively, you can write the Tcl command in the console window,
isim force add B 0 -value 1 -radix bin -time 250 ns -value 0 -radix bin -time 500 ns -
value 1 -time 750 ns -repeat 1us
11. Enter 1 us inside the simulation time toolbox in the toolbar, and then press Run for
the Time Specified in the Toolbar icon. Or type the following Tcl command in the
console window.
Run 1 us
12. The simulator will show the behavior of the gates according to the specified input
signals, press in Zoom to Full View in the toolbar to show the entire simulation
period.
13. The simulator will show the behavior of the gates according to the specified input
signals, press in Zoom to Full View in the toolbar to show the entire simulation
period. You can Zoom in and Zoom out using the icons in the toolbar. Your signals
should look like the following:
Figure 6
14. To restart the simulation, press on Restart icon on the toolbar. Note that restarting
the simulation will also remove the force clock values. You have to apply force clock
to the input signals before running the simulation again.
15. Verify that the circuit is working correctly by checking the time diagram (waveform)
as shown in Figure 6.
16. Close ISim and return to ISE.
Experiment 3: Introduction to FPGA
Page 8
Experiment 3
4. Package Pins Assignment
The objective here is to connect the inputs of the circuit (A & B) to 2 of the input pins of
the FPGA chip which are connected to board switches. Likewise, we want to connect the
output of the circuit (S & C) to 2 of the output pins of FPGA chip which are connected to
board LEDs. This will allow us to manually test the circuit on the board. Switches and LEDs
on the FPGA board are connected as follows:
1. Choose input and output pins on your Digital Logic Board. See appendix A in the Lab
Guide for the pins diagram. Refer to Appendix B in the Lab Guide to find which pins of
the chip FPGA are connected to the board switches and LEDs. Pick two switches (inputs)
and two LEDs (outputs).
2. In the project navigator to the left, click on the Design tab. Then click on your schematic
file. Change to implementation mode by selecting the Implementation radio button
on top.
3. Click on I/O Pin Planning (Plan Ahead) – Post-Synthesis under User Constraints. This will
launch PlanAhead.
4. In PlanAhead, select the I/O Ports tab in the left panel, expand Scalar ports. You will find
a list of the I/Os of your schematic design, i.e., {A, B, S, and C}.
5. Decide the site number of the switch(es) and LED(s) for inputs and outputs on your
board (represented by a small code on the board). In this guide, we are using SW0,
SW1, LD0, and LD1 which have the sites v8, u10, r20, and t19, respectively.
6. Click on the I/O port, then click the column under Site on front of the I/O port and
choose the corresponding site from the drop down list. Do it for A, B, S, and C.
Figure 7
7. Once the pins are locked down, select File → Save Design. The changes made in
PlanAhead are saved in the lab3.ucf file in your current working directory.
8. Exit PlanAhead.
Experiment 3: Introduction to FPGA
Page 9
Experiment 3
5. Design Implementation
The objective here is to generate the configuration bits-file which, when downloaded to the
FPGA chip, configures it to implement our specific design. Note: For more information
about implementing a design, see ISE Help. Select Help, ISE Help Contents, expand either
the FPGA or CPLD hierarchy in the left pane and expand the Implementing Design
hierarchy.
1. Click on your schematic file in the project navigator.
2. Double-click on Generate Programming File in the Processes window. This runs all
processes and creates the configuration bits file of this design. Be patient – this takes a
while!
3. The BitGen program creates the (halfadder.bit bitstream file. The bitstream file contains
the actual configuration data.
4. A check on the Processes for Source window denotes a process that was run
successfully. An exclamation sign indicates that the process was run and that there is a
warning for the process. More information about warnings can be obtained in the
Transcript window.
6. Timing Analysis
The objective here is to analyze the time report of the implemented design. To see the
timing report, go to Tools->Timing Analyzer->Post-Place & Route. The timing
report will be shown in the right window similar to Figure 8
Figure 8
Programming the Spartan Board
Experiment 3: Introduction to FPGA
Page 10
Experiment 3
7. Board Programming
The objective here is to download the design configuration bits file to the FPGA board. The
detailed procedure is as follows,
1. Turn on your Xilnix Spartan-3AN Board and make sure that the board cable is properly
connected to the PC.
2. Double-click Generate Programming File to create a bitstream of your design
3. The BitGen program creates the halfadder.bit (a bitstream file). The bitstream file
contains the actual configuration data.
4. Click on Configure Device to expand the list, then double click on Generate Target
PROM/ACE File. A pop-up window will appear, click OK.
5. ISE will automatically run iMPACT. Double-click on Boundary Scan Mode in the
iMPACT Flows box on the left.
6. Right-click in the middle of the white window to initialize new JTAG chain. Choose
Initialize Chain. This will create and show a device chain. Click Yes if it asks to continue
and assign configuration files.
7. Choose the halfadder.bit file you generated in the proper directory. Click Open. Click
No to attach SPI or BPI PROM.
8. A window will appear “Add PROM File”, choose Cancel.
9. Another window will open, this time click Bypass. Then click OK.
10. A window will appear “Device Programming Properties”, click OK.
11. Right-click on the first chip, named xc3s700a, and choose Program. When the program
operation completes, a blue message with “Program Succeeded” appears.
12. Congratulation, your design is programmed in the Xilnix board. Go and have fun with it.
You should be able to verify the design of the circuit using switches and LEDs.
13. Show your design to the lab instructor.
14. When you close the program, it will ask you to “Save current project before exiting ISE
IMPACT”. Click NO.
15. Turn off your Xilnix Spartan-3A board after showing it to the instructor.
16. Follow the same steps that you have done with the instructor and make a 1-bit full
adder circuit. Simulate it using ISim and test it on FPGA board.
Lab Report
Print the lab report format and write a complete lab report on this printed document about
this experiment as mentioned in the document. Submit the printed circuit diagram of full
adder, simulation screen shot and timing report as an attachment with the lab report.
Experiment 4: Creating and Using Symbols
Page 1
Experiment 4
CCrreeaattiinngg aanndd UUssiinngg SSyymmbboollss
Objectives
In this experiment, you will:
Get more familiar with FPGA and design tool
Learn about symbols and hierarchical design
Build Half-Adder and define it as a symbol
Use the Half-Adder symbol to build a Full-Adder, and define a symbol for it
Build a 4-bit adder using Full-Adder symbols
Material Required
Xilnix FPGA board
ISE design suite
Design Specifications
In experiment 2, you have constructed a full-adder using IC circuits and verified it using a
prototype board. This week, you will use FPGA board to design, simulate and verify
different circuits. First, you will build a Half-Adder (HA). The function of the Half-Adder is to
add 2 input bits. Thus, the half-adder has only two inputs and two outputs. The circuit
diagram and the truth table of the half-adder are shown in figure 1 and figure 2. You will
create a symbol of this circuit and name it as “HalfAdder”.
Figure 1: Logic diagram of half-adder
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Table 1: Truth table of half-adder
EExxppeerriimmeenntt 44::
Experiment 4: Creating and Using Symbols
Page 2
Experiment 4
Then you will design a full-adder (FA) using the symbol you created. You might already
know that full-adder adds three bits and produces two output bits. Figure 2 shows the
circuit diagram of the full-adder. Note that you need two half-adders and one 2-input OR-
gate. Similarly, you will create a symbol for the full adder to be used as one unit and call it
“FullAdder”.
Figure 2: Logic diagram of a 1-bit full-adder
Finally, using N full-adders, you can create a circuit that adds two N-bit numbers. The carry-
in of each Full Adder is the carry-out of the previous Full Adder. This type of adder is called
a ripple carry adder (RCA). In this lab, you will build a 4-bit binary adder using the four 1-bit
full-adder symbols you have created previously. The logic diagram of the 4-bit adder is
shown in Figure 3.
Procedure
The procedure of this lab is divided into 5 main parts as follows,
1. In part I, you will build and verify a Half-Adder circuit
2. In part II, you will build a symbol of Half-Adder
3. In part III, you will build a Full-Adder using Half-Adder symbols
4. In part IV, you will build a Full-Adder symbol
5. In part V, you will build a 4-bit adder using Full-Adder symbols
Note: you may refer to the lab guide for detailed step-by-step procedure
C4
C3 C1 C2
Full
Adder
Full
Adder
Full
Adder
Full
Adder
A3 B3 A2 B2 A1 B1 A0 B0 C0
S0 S1 S2 S3
Figure 3: Logic diagram of a four-bit adder
Experiment 4: Creating and Using Symbols
Page 3
Experiment 4
Part I
Objective: Build and verify the operation of the H.A. circuit
1. Start ISE Design Suite, Create a new project. Choose Schematic as Top-level source
type and set project settings properly (Section II part 1 in lab guide).
2. Create a new source of type Schematic and name it “HalfAdder”
3. Draw the logic diagram of the half-adder in the schematic editor window as shown
in Figure 1
4. Append I/O markers properly. Name the inputs A and B, and the outputs, S and C
5. When you finish, save and run the behavioral simulator Isim
6. Use the following Tcl commands to add force clock to the inputs (or do it through
“Force Clock” method as you have done before in previous experiment).
● isim force add {/HalfAdder/A} 0 -radix bin -value 1 -radix bin -time 500 ns -repeat 1 us
● isim force add {/HalfAdder/B} 0 -radix bin -value 1 -radix bin -time 250 ns -repeat 500 ns
7. Run the simulation for 1 us, then verify the output signals. Close ISim if your design
entry simulation is correct. Otherwise, go back and correct the mistakes, if any.
8. Choose any of the board switches and LEDs and note down their site numbers.
Using PlanAhead, assign I/O ports in your design entry to the selected switches and
LEDs.
9. Generate Bit file, and Program your board.
10. Verify half-adder functionality on the board.
Part II
Objective: Define a higher level symbol of the H.A.
1. To create a symbol of your half-adder, in ISE Schematic Editor, go to Tools-
>Symbol Wizard
2. Click on Using schematic options and choose your schematic file from the
dropdown list. Click Next.
3. Edit Symbol name, name it “HalfAdder”. Make sure that all pin definitions are
correct. Click Next.
4. Click Next on the layout page, then Finish in the Preview page
5. Now your symbol is already added to the symbol library in your project. You can
find it under categories (will have the long path of your file) or simple type its name
in Symbol name filter.
Experiment 4: Creating and Using Symbols
Page 4
Experiment 4
Part III
Objective: Build a F.A. using H.A. symbol
1. Create a new source (of type Schematic) and name it “FullAdder”.
2. Draw the logic diagram of the full-adder in the schematic editor window, as shown
in Figure 2, using the H.A symbol created in Part II.
3. Append I/O markers properly. Name the inputs A, B, and Cin, and the outputs, S
and Cout.
4. When you finish, save and run the behavioral simulator Isim.
5. Use the following Tcl commands to add force clock to the inputs (or do it through
“Force Clock” method as you have done before in previous experiment).
isim force add {/FullAdder/A} 0 -radix bin -value 1 -radix bin -time 1000 ns -repeat 2 us
isim force add {/FullAdder/B} 0 -radix bin -value 1 -radix bin -time 500 ns -repeat 1 us
isim force add {/FullAdder/Cin} 0 -radix bin -value 1 -radix bin -time 250 ns -repeat 500 ns
6. Run the simulation for 1 us and then verify the output signals. Close ISim if your
design entry simulation is correct. Otherwise, go back to your design entry and
correct any mistakes.
7. Choose any of the board switches and LEDs and note down their site numbers.
Using PlanAhead, assign I/O ports in your design entry to the selected switches
and LEDs.
8. Generate Bit file, and Program your board.
9. Verify full-adder functionality on the board.
Part IV
Objective- Define a F.A. symbol
1. To create a symbol of your full-adder, in ISE Schematic Editor, go to Tools-
>Symbol Wizard
2. Click on Using schematic options and choose your schematic file from the
dropdown list. Click Next.
3. Edit Symbol name, name it “FullAdder”. Make sure that all pins definitions are
correct. Click Next.
4. Click Next on the layout page, then Finish in the Preview page
5. Now your symbol is already added to the symbol library in your project. You can
find it under categories (will have the long path of your file) or simple type its name
in Symbol name filter.
Experiment 4: Creating and Using Symbols
Page 5
Experiment 4
Part V
Objective: Build a 4-bit adder using F.A. symbols
1. Create a new source of type Schematic and name it “fourBitAdder”
2. Draw the logic diagram of 4-bit adder in the schematic editor window, as shown in
Figure 3, using F.A symbol created in Part IV
3. Append I/O markers properly. Name the inputs A0, A1, A2, A3, B0, B1, B2, and B3
accordingly. Name the outputs S0, S1, S2, S3, and Cout.
4. Connect the first carry in C0 to ground (gnd) to make it permanently zero.
5. When you finish, save and run the behavioral simulator Isim
6. Verify the simulation results using proper input signals. You should test different
input signals to ensure correct functionality of the adder.
7. Choose any of the board switches and LEDs and note down their site numbers.
Using PlanAhead, assign I/O ports in your design entry to the selected switches
and LEDs
8. Generate Bit file, and Program your board.
9. Verify 4-bit full-adder functionality on the board.
Lab Report
Print the lab report format and write a complete lab report on this printed document about
this experiment as mentioned in the document. Attach all the three simulation snapshots
Introduction: <Don't copy-paste from the lab manual>
• List the objectives of the experiment and the circuit to be designed to achieve each objective.
Circuit: /65 Report: /25 Neatness: /5
Teamwork: /5
Total: /100
2 Design:
Describe the following: 1. The design of your circuit. 2. The procedures followed in the design. 3. Mention if there were any design alternatives? If yes, which of these alternatives
did you adopt? Justify your choice.
3 Testing & Troubleshooting: Describe the procedures followed in testing your design. Don't simply write "we tried it and it worked,"
• The test configuration
but instead describe
• Applied test data • Output verification <Discuss how did you conclude that it was working correctly>
For each problem faced, describe:
• The problem • Cause of the problem • How did you troubleshoot the problem • Describe your solution and whether it has fixed the problem.
• Summarize the work accomplished. • Summarize what have you learned from this experiment. Attachments (give list): • Simulation results (Images / Tabulations).
Introduction: <Don't copy-paste from the lab manual>
• List the objectives of the experiment and the circuit to be designed to achieve each objective.
Circuit: /65 Report: /25 Neatness: /5
Teamwork: /5
Total: /100
2 Design:
Describe the following: 1. The design of your circuit. 2. The procedures followed in the design. 3. Mention if there were any design alternatives? If yes, which of these alternatives
did you adopt? Justify your choice.
3 Testing & Troubleshooting: Describe the procedures followed in testing your design. Don't simply write "we tried it and it worked,"
• The test configuration
but instead describe
• Applied test data • Output verification <Discuss how did you conclude that it was working correctly>
For each problem faced, describe:
• The problem • Cause of the problem • How did you troubleshoot the problem • Describe your solution and whether it has fixed the problem.
4 Answer the questions which are asked in the lab manual for this experiment. Write the question first and then the answer.
• Summarize the work accomplished. • Summarize what have you learned from this experiment. Attachments (give list): • Simulation results (Images / Tabulations).