Kevin Pitts February 24, 2000 XTRP Review slide - 1 XTRP Review Agenda: äIntroduction/OverviewK. Pitts10’ äBoard StatusM. Kasten25’ äDAQ/Interface/Test.

Kevin Pitts February 24, 2000

XTRP Review slide - 1

XTRP Review

Agenda: Introduction/Overview K. Pitts 10’Board Status M. Kasten 25’DAQ/Interface/Test Software N. Eddy 15’Map Generation/Implementation H. Kim 15’Schedule/Summary Pitts/Kasten

XTRP Group:

Nathan Eddy, Lee Holloway, Mike Kasten,

Hyunsoo Kim, Kevin Pitts

Documentation: http://web.hep.uiuc.edu/Engin/CDF/XTRP/



People Involved

Mike Kasten lead engineer: board design/fab/testing

Nathan Eddypostdoc: DAQ/testing software, Java-man

Hyunsoo Kimpostdoc: map generation/implementation; interface with

database and front end; offline simulation

Kevin Pittsspiritual guidance: Spirit? Maybe. Guidance? Not much.

Knowledge? None.

Plan to add a grad student very soon



Trigger

XTRP is the interface between tracks in the COT (XFT) and the remainder of the Level 1 trigger.

XFT data input to the XTRP Output info to:

L1 calorimeter (extrapolate) L1 muon (extrapolate) Track Trigger (pass) Global L1 & L2 (pass) SVT (pass)



XTRP Overview

XTRP system:1 clock/control board1 clock/control transition module12 data boards12 data board transition modules

Entire system: one VME crateVIPA-style (not CDF-style)P2 not bussed location: 2nd floor trigger room



XTRP System

Data board (x12)Clock/controlboard

Clock/controltransition module

Data boa rdtransition module(x12)

CDF clock

Data boards(duplicates)

2 XFTlinkers

L1muon

L1calorimetry

Level1 R equest

132 ns + 33nsclocks

SVTL2 trigger

12 data boards

30° (2 wedges)

The XTRP SystemXTR P I/O

Inte rnal c omm unication

Track Data



XTRP Boards

Clock/control board (1) from CDF clock, generates four phases of 132ns clockalso generates 33ns clockcontrols: SYNC, RESET, HOLDputs all ECL on backplane

Clock/control board transition moduleSVT, PreFRED, and L2 I/O through this board

Data board transition module (12) receives track data from XFTdrives info out to Muon,Cal,etc.all XFT,CAL,MUON I/O through this board



XTRP Data Board

One board per two 15o wedges12 boards total (2 XFT linkers -> 1 XTRP data board)on board: two wedges denoted “A” and “B”

Functionality latch XFT data every 33nsdemux and pipe (FPGA) [also buffer for L1,L2] lookup RAMshandle duplicate tracksdrive data out to CAL and Muon



Recent History

dates whatJun-Sept ’99 data board tests at UIUCJul-Aug ’99 clock board tests at UIUCAug ’99 -> present test/control/readout software development

(in CDF framework…standalone software done)Sept ’99 -> present map software developmentSept ‘99 data board transition module tests at UIUCNov ’99 -> present clock, data and TM testing at FNAL

(linker output/ linker tester)Feb ’00 order production data boards



Test Setup (WH 14)

XTRP crate test clock XTRP clock/control board data board data board transition module

XFT linker crate 2 XFT linkers XFT “linker tester”

- data blaster/buffer board

Clock/control board

Data board



Today

Mike Kastenboard status tests, test resultsplans

Nathan Eddy test and readout software package

Hyunsoo Kimmap generationdownload software



Schedule

dates whatnow -> Apr ‘00 continue to test data board at WH 141-Apr-00 1st loaded data board returnsApr ‘00 test data board at UIUC/ test board at FNAL15-Apr ‘00 XTRP from WH -> B0 (depends on where we test

DIRAC and MUON interfaces)1-May-00 release remaining boardsMay ‘00 track trigger layout resumesJun/Jul ‘00 integration tests (4 wedges) at B0Jun ‘00 remaining data boards in UrbanaJul ‘00 all data boards at FNAL/full system testing



Manpower

Current:Kasten 100%, Eddy 75%, Kim 100%

Future:Kim will play a larger roll in hardware when maps are doneadd at least one grad student soon

Track Trigger:Kasten, Pitts, studentmore UIUC engineering support if needed

- Mike Haney largely done with CLEO-III trigger

- also get an EE grad student

Kevin Pitts February 24, 2000 XTRP Review slide - 1 XTRP Review Agenda: äIntroduction/OverviewK. Pitts10’ äBoard StatusM. Kasten25’ äDAQ/Interface/Test.

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