“DESIGN AND IMPLEMENTATION OF ALU USING FPGA” A Synopsis Report Submitted in partial fulfillment of the requirement for the award of degree ofMaster of Technology [VLSI !SI"#$ Submitted To RA%IV "A#&I 'R()*("I+I VIS&,AVI*ALA*A- .&('AL /M0'01 Submitted by +A'IL "()R[2324!533MT36$ )nder the super7ision of")I! #AM! epartment of !lectronics 8 5ommunicati on !ngineering R+9 Institute of Science 8 Technology- .hopal
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TodayCs world requires faster processor for the computation purposes to meet the application
demand of the digital systems. (ith the constant growth of computer applications in e0ery fieldof engineering such as signal processing* communications and neural networks* fast arithmetic
logic units ,A)%/ are increasingly required. The A)% of any processor perform many functionssuch as Addition* Subtraction* -ultiplication* !i0ision and )ogical 6omparison etc. Thesearithmetic operations produce carry propagation chains. The speed of operations depends on the
implementation of arithmetic algorithms.
A)% can be designed using ripple carry or carry look ahead adder. +ut in case of ripple carry
adder the delay will be more as the carry should be propagated entire bit width. So speed will be
reduced. 6arry look ahead adders are faster than ripple carry adders but the comple4ity of the
circuitry increases as the number of bits increases.
A)% is a building block of se0eral circuits. %nderstanding how an A)% is designed and how it
works is essential to building any ad0anced logic circuits. %sing this knowledge and e4perience*
we can mo0e on to designing more comple4 integrated circuits. (hen designing the A)% we
will follow the principle D!i0ide and 6onquerD in order to use a modular design that consists of
smaller* more manageable blocks* some of which can be re?used. Instead of designing the >?bit
A)% as one circuit we will first design a one?bit A)%* also called a bit?slice. These bit?slices can
then be put together to make a >?bit A)%.
The A)% is the part of a microprocessor or a microcontroller that handles all +oolean and
mathematical operations. It is a fundamental building block of the central processing unit of a
computer. -icroprocessor has traditionally been design around these essential unit like decoding
unit* A)% ,arithmetic and logic unit/* timing and control unit. Arithmetic and logically related
operation in microprocessor perform by A)% unit. 6ontents of many different circuits put on a
single chip* makes an integrated circuit. (ith introduction of the integrated circuit* all the
peripheral de0ices and microprocessor was put on a single de0ice. This led to de0elopment of a
microcontroller. A microcontroller differs from microprocessor in many ways. -ost important
aspect is with the functionality. In order for a microprocessor to be functional* other componentsas memory or components for recei0ing and sending data must be added to it. In short
microprocessor is the 0ery heart of the computer. $n the other hand* microcontroller is designed
to be all of that in one. o other e4ternal components are needed for its application as all
necessary components are built to it. Thus we sa0e the time and space needed to construct
de0ices. -icrocontroller also performs arithmetic and logical operation with the help of A)%.
-icrocontroller identified as basic registers* A)%* memory* control and timing unit. !ual?A)%s
are used to e4ecute instructions concurrently for fine?grained parallelism. %p to three
instructions can be e4ecuted simultaneously by 6RIS6. "ere* 6RIS6 architecture design
considerations and instruction cache scheme are in0estigated . The combination of logic styles
and low power E$R gates is used F7. !ouble edge?triggered flip?flops are used to reduce the
A programmable arithmetic logic unit for performing high speed bit sliced* pipelined
computations at 0ery low power is fabricated as an )SI component. It is micro programmable
and operates in con3unction with a fast micro program store program memory and controller.!ual input ports which supply data from eight sources are latched and operated on while new
data is simultaneously fetched. The A)% is a digital function that implements basic micro?
operations on the information stored in registers. The full adder design has been implemented
using 6-$S in0erters. The A)% has four stages* each stage consisting of three partsH a/ input
multiple4ers b/ full adder and c/ output multiple4ers. The A)% performs the following four
arithmetic operations* A!!* and S%+TRA6T* I6R5-5T and !56R5-5T. The four
logical operations performed are 5E?$R* 5E?$R* A! and $R. The input and output sections
consist of > to 7 and 8 to 7 multiple4ers. A set of three select signals has been incorporated in the
design to determine the operation being performed and the inputs and outputs being selected.
The full adder design has been implemented using 6-$S in0erters.
A)% with the 6ARR& bit cascading all the way from first stage to fourth stage. The A)% design
consisting of eight > to 7 multiple4ers* eight 8 to 7 multiple4ers and four full adders. The >?bit
A)% was designed using .78 micron technology. This chapter e4plains in detail the >?bit A)%
design. All of the multiple4ers ha0e been implemented using pass transistors* and the full adder
alone has been designed. 5ach stage is discussed in detail in the further sections of this chapter.
The full adder is configured as ripple carry adder. (e ha0e used this ripple carry adder ,R6A/
configuration in our A)% design. In R6A* the 6ARR& bit ripples all the way from first stage to
nth stage. 1igure ; shows the block diagram of a four?bit ripple carry adder. The delay in a R6A
depends on the number of stages cascaded and also the input bitsC patterns.
1or certain input patterns* a 6ARR& is neither generated nor propagated. This way the 6ARR&
bit need not ripple through the stages. This effecti0ely reduces the delay in the circuit. $n the
other hand* certain input patterns generate carry bit in the first stage itself* which might ha0e toripple through all the stages. This definitely increases the delay in the circuit. The propagation
delay of such a case* also called critical path* is defined as worst?case delay o0er all possible
input patterns. 1igure ;H +lock diagram of a >?bit ripple carry adder. In a ripple carry adder* the
worst?case delay occurs when a carry bit propagates all the way from least significant bit
position to most significant bit position. The total delay of the adder would be an addition of
delay of a S%- bit and delay of a 6ARR& bit multiplied by number of bits minus one in the
input word* gi0en by 5q. ,=.@/ F7=.
Tadder E /#>31 Tcarry F Tsum /?0D1
(here is number of bits in input word* Tcarry and Tsum are propagation delays from one stage to
another. 1or an efficient ripple carry adder* it is important to reduce T carry than Tsum as the former
influences the total adder delay more.
9igure GC .loc diagram of a 4>bit ripple carry adder0
A)% can be designed using ripple carry or carry look ahead adder. +ut in case of ripple carry
adder the delay will be more as the carry should be propagated entire bit width. So speed will bereduced. 6arry look ahead adders are faster than ripple carry adders but the comple4ity of the
circuitry increases as the number of bits increases. %se of non?con0entional number systems in
designing A)% is gaining attention in recent years because of their facility to pro0ide carry freeaddition thus enhancing the achie0able processing speed. 1or making the processing faster a
carry free addition technique is adopted by using Redundant +inary umber System F7F8F;.
The property of carry propagation chain elimination tends to make the processing faster.
In this paper* the R+S! based arithmetic and logical unit is designed using V"!) and its RT)
0iew is generated by its 1#GA implementation. The 1#GA Implementation is done in
54ampleH 6arry M1ree addition using redundant signed radi4 8
In con0entional binary number system radi4 8 number digit set contains <* 7. The number of
digits equal to radi4.54ampleH umber 9 can be represented in binary as below
< 7 7 <
umber > can be represented as below< 7 < <
In case of redundant Signed radi4 8 number digit set contains Q?7*<*7. The number of digits
present in the digit set will be more than the radi4. So each number can be represented in many
ways.54ampleH umber 9 in decimal can be represented in redundant binery as follows.
< 7 7 < ??????? 9
7 < ?7 < ??????? 9 umber > can be represented in redundant binary as follows
< 7 < < ?????????? >
7 ?7 < < ?????????? >
In case of con0entional binary addition there will be carry propagation. 6arry will be propagated
till the end.
Addition in case of R+S! is carry free.
In case of R+S! addition the two operands will be added to get the position sum,pi/. Then the position sum will be di0ided into interim sum ,wi/ and transfer digit,ti/. Then interim sum and
transfer digit is added to get the final sum.
In case of con0entional binary there is no such step.)et the two operanads be Ei K < 7 7 < and &i K < 7 < 7
Ei K < 7 7 < ??????? , 9/7<
&i K < 7 < 7 ??????? ,@/7<The final sum should be , 77/7<
Adding these two numbers using binary.
< 7 7 < ???? Ei
< 7 < 7 ???? &i
? 5(#5L)SI(# 8 9)T)R! S5('!
This section includes conclusion drawn on basis of functional simulation results as well asimplementation of A)%. +y using V"!) we design A)% and we can perform arithmetic and
logical operation. It is a fundamental building block of the central processing unit of a
computer.A)% is a building block of se0eral circuits. %nderstanding how an A)% is designed and
how it works is essential to building any ad0anced logic circuits. !esign consists of different kind of
logicRipple carry adder* full adder* A!* $R* $R* !11* -%E. Simply* to operate on k?bit