K87-MLB_051-8561_820-2877_C00.pdf - informaticanapoli

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TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

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8 7 6 5 4 2 1

12

APPDCK

DESCRIPTION OF REVISION

04/26/2010

Schematic / PCB #’s

SCRATCHOSCHEM MLB_LDO K87

1 OF 76

0000897412C

051-8561

C.0.0

1 OF 109

PRODUCTION RELEASED 2010-04-26

52

38 MASTER MASTERK87 SMBus Connections

51

37 (T27_MLB) (12/15/2009)LPC+SPI Debug Connector

50

36 (T27_MLB) (10/27/2009)SMC Support

49

35 T27_MLB 02/16/2010SMC

46

34 (K84_MLB) (10/03/2009)External USB Connectors

45

33 MASTER MASTERSATA Connectors

39

32 MASTER MASTERETHERNET CONNECTOR

37

31 MASTER MASTEREthernet PHY (RTL8211CL)

34

30 MASTER MASTERX16 WIRELESS CONNECTOR

33

29 T27_MLB 02/16/2010FSB/DDR3 Vref Margining

32

28 MASTER MASTERSO-DIMM Pinswaps

31

27 T27_MLB 02/16/2010DDR3 SO-DIMM Connector B

29

26 T27_MLB 02/16/2010DDR3 SO-DIMM Connector A

28

25 (T27_MLB) (10/07/2009)SB Misc

26

24 T27_MLB 02/16/2010MCP Graphics Support

25

23 (T27_MLB) (11/16/2009)MCP Standard Decoupling

24

22 T27_MLB 12/15/2009MCP89 GFX Core Rail Gating

23

21 K6_MLB 02/16/2010MCP89 Memory Rail Gating

20

20 T27_MLB 02/16/2010MCP Power & Ground

19

19 T27_MLB 02/16/2010MCP HDA, LPC & MISC

18

18 T27_MLB 02/16/2010MCP SATA, USB & Ethernet

17

17 T27_MLB 02/16/2010MCP Graphics

16

16 T27_MLB 02/16/2010MCP PCIe Interfaces

15

15 T27_MLB 02/16/2010MCP Memory Interface

14

14 T27_MLB 02/16/2010MCP CPU Interface

13

13 (K84_MLB) (02/25/2009)eXtended Debug Port(MiniXDP)

12

12 T27_MLB 02/16/2010CPU Decoupling

11

11 T27_MLB 02/16/2010CPU Power & Ground

10

10 T27_MLB 02/16/2010CPU FSB

9

9 (K84_MLB) (02/04/2009)SIGNAL ALIAS

8

8 MASTER MASTERPower Aliases

7

7 MASTER MASTERFUNC TEST

6

6 MASTER MASTERRevision History

5

5 MASTER MASTERRevision History

4

4 (K84_MLB) (01/19/2009)BOM Configuration

3

3 MASTER MASTERPower Block Diagram

2

2 MASTER MASTERSystem Block Diagram

109

K87 RULE DEFINITIONS MASTERMASTER76

108

K87 SPECIFIC CONSTRAINTS MASTERMASTER75

106

SMC Constraints 02/16/2010T27_MLB74

104

Ethernet Constraints MASTERMASTER73

103

MCP Constraints 2 02/16/2010T27_MLB72

102

MCP Constraints 1 02/16/2010T27_MLB71

101

Memory Constraints 02/16/2010T27_MLB70

100

CPU/FSB Constraints 02/16/2010T27_MLB69

98

LCD Backlight Support (10/19/2009)(K84_MLB)68

97

LCD Backlight Driver (MC34845) MASTERMASTER67

94

DisplayPort Connector MASTERMASTER66

93

DISPLAYPORT SUPPORT 02/16/2010K6_MLB65

90

LVDS CONNECTOR (10/19/2009)(K84_MLB)64

79

POWER FETS MASTERMASTER63

78

Power Sequencing (10/27/2009)(T27_MLB)62

77

Misc Power Supplies MASTERMASTER61

76

CPU VTT(1.05V) SUPPLY (02/04/2009)(K84_MLB)60

75

MCP VCore Regulator (10/27/2009)(K6_MLB)59

74

IMVP6 CPU VCore Regulator (11/18/2009)(K84_MLB)58

73

1.5V/0.75V DDR3 SUPPLY (11/06/2009)(K6_MLB)57

72

5V/3.3V SUPPLY (10/27/2009)(K6_MLB)56

70

PBus Supply & Battery Charger (11/06/2009)(K6_MLB)55

69

DC-In & Battery Connectors MASTERMASTER54

68

AUDIO: JACK TRANSLATORS 02/16/2010AUDIO53

67

AUDIO: JACK 02/16/2010AUDIO52

66

AUDI0: SPEAKER AMP 02/16/2010AUDIO51

65

AUDIO: HEADPHONE FILTER 02/16/2010AUDIO50

63

AUDIO: LINE INPUT FILTER 02/16/2010AUDIO49

62

AUDIO: CODEC/REGULATOR 02/16/2010AUDIO48

61

SPI ROM 02/16/2010T27_MLB47

60

DEBUG SENSORS AND ADC MASTERMASTER46

59

SMS MASTERMASTER45

58

WELLSPRING 2 MASTERMASTER44

57

WELLSPRING 1 02/16/2010T27_MLB43

56

Fan Connector 02/16/2010T27_MLB42

55

Thermal Sensors MASTERMASTER41

54

Current Sensing 02/02/2010T27_MLB40

Sync(.csa)

DateContentsPage1

1 NA NATable of Contents53

Voltage Sensing 02/16/2010T27_MLB39

PCBF,MLB_LDO,K87820-2877 1 PCB CRITICAL

DatePage Contents(.csa)

Sync

1 SCHEM,MLB_LDO,K87051-8561 CRITICALSCH

SCHEM,MLB_LDO,SCRATCHO,K87

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:


36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PG 18

HALL EFFECT CONN

INTEL CPU

K86K872.4GHZ 1.2GHZ

CULVPENRYN

AMPS

GPIOs

PG 90

DISPLAY PORT

PG 94

SMBPG 19

AUDIOCODEC

PG 62

PG 63

LINE IN

FILTER FILTER

HEADPHONE

PG 65

CONNSPG 67

J6701,J6702,J6703,J6704

AUDIO

U6201

SPEAKER

U6610, U6620, U6630

PG 66

CONN

PG 32

E-NET

U3700

J3900

PG 37

10/100/1000 E-NETGIGABIT

PG 34

CONN

PCI

J5100

PG 51

PG 70-79

LPC+SPI CONN

POWER SUPPLY

U5535,U5515

SMS

PG 69

PG 59

PG 69,70

PG 55

PG 53,54

PG 56

DC/BATT

TEMP SENSORS

VOLTAGE AND CURRNET SENSING POWER SENSE

FAN CONN

J6950

U5920

J6950,U7000

J5601

J3100J2900

DIMM

PG 29,30

MINI XDP CONN

DDR3-1067/1333MHZ

J1300

PG 13

2 UDIMMs

PG 15

MEMORY

MAIN

FSB

1067/1333 MHz

PrtSerFanADC

J4600, J4610

PG 46

CAMERA

B,0BSB

SMCPG 49

SMSLIDU4900

CONNPG 58

SPI

PG 61

J5800

J9000U5701

PG 90PG 57

TRACKPAD/KEYBOARD

BLUETOOTH

PG 34

U6100

MISC

PG 19

CTRL

PWR

PG 19

PG 18

LPC

J3401

11

10

98

76

45

12

0

J1300

MINI XDP CONNPG 13

HDAPG 19

FSB INTERFACE

NVIDIA

U1400

U1000

PG 10

PG 14PG 19

MCP

PG 18

SATA

DP OUT

HDMI OUT

20 LANES3UP TO

PCI-E

PG 45

CONN

J4500

LVDS

J9000

SATA

ODD

AIR PORT

CONN

J3401

J9400

PG 17

MACRGMII

PG 16

LANPG 17

64-Bit

USB

CONN

TRACKPAD

BOOT ROMSPI

PG 17

3

(UP TO 12 DEVICES)

CONNEXTERNAL USB

DVI OUT

RGB OUT

TMDS OUT

1.05V/3GHZ.

PG 45

SATACONN

HD

J4501

1.05V/3GHZ.

LVDS OUT

RTL8251CA

SYNC_DATE=MASTERSYNC_MASTER=MASTER

System Block Diagram

2 OF 109

C.0.0

051-8561

2 OF 76




36

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REVISION

DRAWING NUMBER SIZE

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SHEET

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C

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2 1


Apple Inc.

PAGE


A

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C

345678

D

B

8 7 5 4 2 1

PP5V_S0_FETQ7948

P3V3S0_EN

U7840

P5V3V3_PGOOD

PP0V9_ENET_FET

ISL8009B

VOUT

VIN

1.05V

TPS51125

PPBUS_G3H

SLP_S4_L(P94)SLP_S4_L

SMC_BATT_ISENSE

U7100

PGOOD

(8A MAX CURRENT)

U2850

PP4V5_AUDIO_ANALOG

ALL_SYS_PWRGD

RSMRST_PWRGD

SMC_ONOFF_L

U7750

P5VS3_EN_L

PM_SLP_RMGT_L

09

PPVBAT_G3H_CONN

09-3

DELAY

MCP89

SMC_CPU_VSENSE

CPUVTTS0_PGOOD

TPS51117

SMC_CPU_ISENSE

27

02

Q5315PBUS_G3H_VSENSE

CPUVTT

RN5VD30A-F

U5010LT3470

CPU VCORE

SMC

ISL9563AU7500

U7300TPS51116

U9700MC34845

0.75V

1.5VS5

S3

ISL88042U7870

PPMCPCORE_S0_REG

VOUT2

VIN

99ms DLY

SMC_RESET_L

PLT_RST*

RSMRST_OUT(P15)

PWRGOOD

Q7910

U6200

(25A MAX CURRENT)

1.5V

PP1V8_S0_REGP0V9_ENET_EN

P0V9S5_EN

15-2P3V3S0_EN

PM_SLP_S3_L

BKLT_EN

BKLT_ENENA

Q7890,Q7891

VIN

VOUT1

U6990

CHGR_EN

PBUS SUPPLY/

CPUVTTS0_EN(S0)

6A FUSE

R7020

ENABLES

BATTERY CHARGER

02

IMVP_VR_ON_R

24

VOUT

PP1V05_S0

PGOOD

F704002

PPDCIN_G3H_OR_PBUS

(1.05V)

EN_PSV

U7600

VIN

VOUT 21

VIN

PM_SLP_RMGT_L

12

02

10

09-2

J6950

PM_SLP_S4_L

R7050

TPS62202

U7760

Q7920

AP_PWR_EN

(9 TO 12.6V)

U1400

PBUSVSENS_EN

EN

1.8V

PP1V5_S0_FET

1.05VTPS74701

S0PGOOD_RST_LPP1V05_S0_MCP_PLL_OR

P3V3S3_EN

VOUTPPVOUT_SW_LCDBKLT

02

5V(RT)

PGOOD1,2

VOUT

CURRENT)

12

11

PP1V05_S0_REGNCP1529

Q7930

3.3V

VREG3

P5VS3_EN_L

P3V3S5_EN_L

Q7960

U7710

VOUT1

04

FDC638P

PP3V3_S0_FET

19

17

04 04P60

U7740

PP1V05_S0

PP1V5_S0

PP3V3_S0

V2

V3

V1

RST*

20

MCPPLLDO_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

MCPCORES0_EN

SMC_ADAPTER_EN

MCP_CORE

ENVOUT

PPMCPCORE_S0_R R7525

Q7890

PM_WLAN_EN_L 15

Q7930

17

PP3V3S0_EN

10(S5)

EN2

EN1

VIN

U7201

06

28

MCP_PS_PWRGD

U1000

CPU

PWRGD

U1400

MCP89

CPU_RESET#

PWRBTN*

PLTRST*

RESET*

CPUPWRGD(GPIO49)

RSMRST*

FSB_CPURST_L

29

LPC_RESET_L

CPU_PWRGD

30

08-1

PM_RSMRST_L

PWR_BUTTON(P90)

RSMRST_IN(P13)

21

=DDRREG_EN

RC

=DDTVTT_EN

04-1

VIN

01

A

VR_ON

PPVBAT_G3H_CHGR_RQ7055

U7000ISL6259

SMC

25

3.425V G3HOT

DELAY

09-1

PWRGD(P12)

IMVP_VR_ON(P16)

18-2

15-1

PM_SLP_S3_L

IMVP_VR_ON_R24

PM_PWRBTN_L

23

08

09

PP1V5R1V35_SW_MCP

PP1V5_S3_REG

(1A MAX CURRENT)

(12A MAX CURRENT)13

VOUT2

15-1

15-6

P5VS0_EN

15-5

15-4

15-3

MCPCORES0_ENDELAY

RC

DELAY

RC

DELAY

DELAY

RC

RC P1V8S0_EN

CPUVTTS0_EN

P1V5S0_EN

DDRVTT_EN

3S2P

RC

DELAYRC

(S0)

(S0)

02

VIN

02

ADAPTERAC

IN

DCIN(16.5V)

F6905

01

A VIN

(S5)

PP18V5_DCIN_CONN

PPVBAT_G3H_CHGR_REG

Q7085

Q7080

8A FUSE

ISL9504B

SLP_S5_L

SLP_S3_LSLP_S3_L(P93)

SLP_S5_L(P95)

U4900

PPBUS_G3HV

ENABLE

VOUT

PP3V42_G3H_REG 03 SMC PWRGD 04

RST*

P17(BTN_OUT)

SMC_DCIN_ISENSE

CHGR_BGATE

U4900

Q3450

P3V3ENET_EN_L

VOUT

MAX8840

EN

4.5V AUDIO

18

18

11

PP5V_S3_REG(13A MAX CURRENT)

PP3V3_S5_REG(5.5A MAX

SMC_PM_G2_EN

P16

22

PP0V75_S0_REG

(44A MAX CURRENT)

PPVCORE_S0_CPU

V

PP3V3_S3_FET

P3V3_S3_WLAN

16

P5VS0_EN

PP0V9_S5_REG07

K86/K87 POWER SYSTEM ARCHITECTURE

VR_PWRGOOD_DELAY

P3V3S3_EN

PM_SLP_S3_L14

DDRREG_EN

P5V3V3_PGOOD

31

PBUS_VSENSE

SYNC_MASTER=MASTER SYNC_DATE=MASTER

Power Block Diagram

3 OF 109

C.0.0

051-8561

3 OF 76

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1




TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Alternate Parts

514-0704 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0692 PART FOR RJ45 CONNECTOR

BOM Groups (always-present)

BOM Groups (project phase-dependent)

SIGNAL(High Speed)

GROUND

SIGNAL(High Speed)

6

SIGNAL

GROUND

GROUND

POWER

5

BOTTOM

3

8

9

2

4

7

10

11

TOP

K86/K87 BOARD STACK-UP

SIGNAL

GROUND

SIGNAL(High Speed)

SIGNAL(High Speed)

Bar Code Labels / EEE #’s

Part Substitutions (differences with K6/K69)

Development BOM

BOM Variants

POWER

LOCKED BOOTROM APN IS 341S2488 (QL: old info?)

Module Parts

353S2718 IS NEW INTERSIL PART FOR FIXING B4 DONGLE ISSUE

514-0705 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0689 PART FOR USB CONNECTORS

514-0706 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0691 PART FOR MINI DP CONNECTOR

Programmable Parts

514-0718 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0694 PART FOR AUDIO CONNECTOR

ZS0912,ZS0913,ZS0914,ZS0915,ZS0919 CRITICAL870-1939 5 POGO PIN,TALL,NOISE-IMPROVED,SILVER,K87

152S0685152S0796 ALL CYNTEC AS ALTERNATE

ALL DALE/VISHAY AS ALTERNATE104S0018 104S0023

152S0778 DALE/VISHAY, MAGLAYERS AS ALTERNATEALL

ALL DELTA AS ALTERNATE

ALL152S0874 MAGLAYERS AS ALTERNATE

ALL152S0847 MAGLAYERS AS ALTERNATE

114S0125 1 LED:K86_K87R5714RES,MTL FILM,1/16W,113 OHM,1,0402,SMD,LF

1 CRITICAL826-4393 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_DD19] EEEE:DD19

826-4393 1 [EEEE_DD17] EEEE:DD17CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1826-4393 [EEEE_DD16] EEEE:DD16

DEVELOPMENT_BOM1085-1632 CRITICALDEVELK87 MLB_LDO DEVELOPMENT BOM

1 CDC,SLGYW,PRQ,1.2,10W,800,R0,1M,BGA U1000 CRITICAL CPU:1.2GHZ

ZS0900,ZS0901,ZS0902,ZS09034 CRITICAL870-1940 POGO PIN,MED,NOISE-IMPROVED,SILVER,K87

CRITICALZS0917,ZS0918,ZS0916870-1938 3 POGO PIN,THIN,NOISE-IMPROVED,SILVER,K87

U49001 SUBASSY, IC, SMC, K87 CRITICAL341T0252 SMC:PROG_K87

CRITICAL1338S0563 U4900 SMC:BLANK

U4900SUBASSY, IC, SMC, K86 CRITICAL341T0250 1 SMC:PROG_K86

335S0610 1 U6100 CRITICAL BOOTROM:BLANK

U6100 CRITICAL341T0251 1 BOOTROM:PROG

IC,WELLSPRING CONTROLLER,K87 U5701 CRITICAL1 WELLSPRING:PROG

337S2983 U57011 CRITICAL WELLSPRING:BLANK

KEMET AS ALTERNATEALL

353S1832 ALL NEW IMPROVED INTERSIL PART AS ALTERNATE

ALL MURATA AS ALTERNATE

SCREW1,SCREW2,SCREW3,SCREW44 CRITICAL452-1708 SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97

MOLEX_DDR_CONNCRITICAL516-0213 1 J2900CONN,204P,SODIMM,P=0.6MM

CRITICALU1400337S3866 1 MCP89M:A02IC,MCP89M-A02,31X31MM,BGA1168

337S3680 PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA CRITICALU1000 CPU:2.4GHZ1

DEBUG_ADC,LPCPLUS_CON,S0PGOOD_ISL,EFI_DEBUG,MCPPLL_LDO,EXT1V05,XDP_CON,LPCPLUS

870-1939 5 ZS0904,ZS0905,ZS0906,ZS0907,ZS0910 CRITICALPOGO PIN,TALL,NOISE-IMPROVED,SILVER,K87

ZS0908,ZS0909,ZS0911870-1940 3 CRITICALPOGO PIN,MED,NOISE-IMPROVED,SILVER,K87

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA516S0790 MOLEX_DDR_CONNJ3100 CRITICAL1

516-0201 FOX_DDR_CONNCRITICAL1 J2900CONN,204P,SODIMM,P=0.6MM

J3100CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA FOX_DDR_CONN1 CRITICAL

CRITICAL1 U1400 MCP83MIC,MCP83M-A02,31X31MM,BGA1168

U1400337S3797 CRITICAL MCP89M:A01IC,MCP89M-A01,31X31MM,BGA11681

K86_K87_COMMON

K86_K87_DEBUG:DEV

K86_K87_DEVELOPMENT_PVT

K86_K87_DEBUG:PRODPROJECT_PHASE:PROD

DEVELOPMENT_BOM

K86_SPECIFIC

K87_SPECIFIC CPU:2.4GHZ,IMVP6:2PHASE,SMC:PROG_K87,MCP89M:A02

K86_K87_COMMON1

SYNC_MASTER=(K84_MLB)

BOM ConfigurationSYNC_DATE=(01/19/2009)

CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM826-4393 1 EEEE:DD18[EEEE_DD18]

085-1799 K86_K87_DEVELOPMENT_PVTK87 MLB_LDO DEVELOPMENT BOM

K86_K87_COMMON,K87_SPECIFIC,MOLEX_DDR_CONN,EEEE:DD17PCBA,MLB_LDO,MOLEX,K87639-1116

639-1115 K86_K87_COMMON,K87_SPECIFIC,FOX_DDR_CONN,EEEE:DD16PCBA,MLB_LDO,FOXCONN,K87

128S0093

152S0693

138S0602138S0603

353S2811

152S0516

128S0218

PROJECT_PHASE:DEV

LPCPLUS_CON,XDP_CON,VREFMRGN:YES,LPCPLUS

VREFMRGN:NO,BMON:PROD,BKLT:PROD,SENS_R:PROD,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES

VREFMRGN:YES,BMON:ENG,BKLT:ENG,SENS_R:ENG

K86_K87_COMMON1,PROJECT_PHASE:PROD,COMMON,ALTERNATE,BOOTROM:PROG,WELLSPRING:PROG,MCP_T_DIODE_SENSOR

DP_ESD,MIKEY,MCPPLL_R:REG,ENET1V05:INT,LED:K86_K87,S0PGOOD_BJT,ENET_ESD,VFRQ:SLPS3,SMC_DEBUG:YES,SPI:25MHZ,XDP,OLD_AUDIO_SWITCH

CPU:1.2GHZ,IMVP6:1PHASE,SMC:PROG_K86,MCP83M

337S3792

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

IC,SMC,HS8/2117,9X9MM,TLP,HF

157S0055157S0058

152S0586

K86_K87_DEBUG:PROD

K86_K87_DEVELOPMENT_ONLY

337S3876

516S0706

341S2677

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

SUBASSY, IC, BOOT ROM, K86/K87

353S2988 353S2987 ALL MIC5365 AS ALTERNATE

ALL376S0634376S0908 TOSHIBA AS ALTERNATE

ALL376S0634376S0907

ALL

FAIRCHILD AS ALTERNATE

376S0868376S0912 ONSEMI(NEW SPEC) AS ALTERNATE 4 OF 109

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Changed C7428 from 0.47uF => 0.33uF (132S0101) per Intersil

T27: Changed USB_RBIAS from 931-ohms to 887-ohms per DG v1.3 (pg. 18). <radar:7459260 > Design Guide v1.3 updates

2010-04-1: A.9.0

Added ONsemi new spec part(376S0912) as an alternate to Q2300(376S0868).

2010-04-14: C.0.0CSA 4: Added Toshiba(376S0908), Fairchild(376S0907) as an alternate to 376S0634.

2010-04-14: B.0.0rdar://7822714

CSA 77: Deleted U7740 1.05V LDO circuit to free space for U2592 and current mirror circuit.

Reverted the changes and synced back to A.0.0Per <rdar://7783507> K87: Add cap to DDC line to avoid DDC line glitch issue

CSA 93: Added C9303 3300pF cap on DP_CA_DET.

CSA 4: Added Alternate part for U2592 LDO. 353S2987(TI), 353S2988(Micrel) to 353S2986(Intersil).

Reverted the changes and synced back to A.2.0.

CSA 25,49,50: Changed Q2592 gate control pin to SMC_P24 from SMC_P10.

CSA 25: Added R2600 0ohm resistor to help layout change.

CSA 25: Changed R2600 refdes to R2550 to match with page#.

CSA 69: R6905 kept same 1ohm. C6900 changed to 2.2uF. 138S0592. CSA 4: Devel BOM# changed to 085-1799. And BOM OPTIONS to K86_K87_DEVELOPMENT_PVT.

2010-04-1: A.10.0

Added IMVP6:2PHASE to R7413 per Intersil

Cosmetic cleanupcsa 90: Deleted net properties for =PP5V_S3_CAMERA

csa 108: Added NET_PHYSICAL property to SATA_HDD_D2R_FILT_P and _Ncsa 98: Deleted net properties for =PPBUS_S0_LCDBKLT

2009-12-09: 1.5.0multiple: Added parentheses for SYNC_DATE property on all pages that have broken sync.csa 4: Deleted entry in Module Parts table for R6612, R6617, R6630, R6633 since they were removed when we switched from piezo to dynamic speakerscsa 69: Changed J6955 symbol to K87 Hall effect assembly (339S0114)

csa 74: Changed 1PHASE BOM table to correctly call out 132S0080 (0.22uF) instead of 0.022uF

csa 54: Began syncing from T27 per <radar:7432091 > BATT_ISENSE filter change to address lower max sink current on ISL6259 BMON pin (K17 auto-shutdown issue)

2010-03-30: A.7.0

2010-03-31: A.8.0

CSA 25: Added R2591,R2594 for LDO:ADJ option. Changed U2592 to LDO:FIXED option.

LDO:FIXED, MCPHVDD:P2V5 added in bom table.

csa 72: Changed L7220 from 152S0693 to 152S0778 per <rdar://problem/7347216> K69 L7260 combo footprint

C5490 changed from CAP_402-0.022UF,10%,16V,CERM-X5R to CAP_402-0.022UF,20%,16V,CERM

csa 29,31: Began syncing from T27 per <radar:7424246 > BOM: K87 needs omit on J3100 and J2900 from T27

csa 18: T27: Swapped USB_EXTB and USB_EXTD for NVRN-612340 (pg. 18). <radar:7416825> Ensure USB_EXTB is on ports 8-11 (NVRN-612340)

LDO:FIXED, MCPHVDD:P2V5 added in bom table.

Changed J5100 BOMOPTION from LPCPLUS to LPCPLUS_CON to unstuff connector at DVT

R7416 added to BOM Table, 16.9K, (APN 114S0336)

*** Started syncing with K6

CSA 25: Changed U2594 power to 3V3_S0 from 3V42_G3H.

Per <rdar://7783507> K87: Add cap to DDC line to avoid DDC line glitch issue

CSA 4: Added MCPHVDD:P2V5, LDO:FIXED, HTOL_SENSE:YES to BOM Group K86_K87_DEBUG:PROD Added =PP3V3_S0_OPA330 alias to power U2593

CSA 8: Added =PP3V42_G3H_OPA330 alias to power U2594

CSA 93: Added C9303 3300pF cap on DP_CA_DET.

2010-03-22: A.4.0

csa 37: Per <rdar://problem/7548726> K86/K87 Ethernet series R’s need to be 0 ohmed

C7413 = 100pF 5% (131S1027)

2010-03-22: A.2.0

CSA 50: Removed SMC alias to TP for SMC_NB_MISC_ISENSE to enable sense circuitry connection to SMC

Changed BOMOPTION names from LDO:YES and LDO:NO to MCPHVDD:P2V5 and MCPHVDD:P3V3 Added R2594 and R2591 with LDO:ADJ BOMOPTION

Added C2599, R2597, R2596, U2593, Q2592, R2599, C2594, U2594, R2598, C2598 with BOMOPTION HTOL_SENSE:YES

Added BOM TABLE with LDO:FIXED, LDO:ADJ, and HTOL_SENSE:NO stuffing options

Removed SMC_P10 alias to TP_SMC_P10

2010-01-15: 2.3.0

csa 51: (Per <rdar://problem/7540522> K86/K87: Production Debug Components)

Added LPCPLUS_CON to K87_DEVEL_ENG (does not change BOM for DVT) Changed all instances of K87_DEBUG_xxxx to K87_DEBUG:xxxx

IMVP6:1PHASE BOM Table:

Changed description for 337S3876 to "IC,MCP83M-A02,31X31MM,BGA1168"

VREFMRGN:YES ==> VREFMRGN:NO

Changed 085-1093 to call out K87_DEVEL_PVT instead of K87_DEVEL_ENG

csa 4: Cosmetic: changed text sizes and alignment2010-01-13: 2.2.0

Changed C4585, C4586 to 131S4713 (47pF, 5%)

Updated APN text note

Added the following functional test points under the J5100 LPC+SPI CONN FUNC_TEST group

Changed text note to say "HALL EFFECT ASSEMBLY"

Changed R3440 color to green, deleted WF text note about needing PU

Per <rdar://problem/7495072> K87: Call out LED:K86_K87 BOMOPTION in the K87_MISC BOM group

Removed table entry that says 376S0868 is an alternate for 376S0624

Created SMC:PROG_K86 pointing to 341T0250 (SUBASSY, IC, SMC, K86)

Deleted BOM table for Hall effect assembly

Syncing with K6 to pick up new symbols for Q2355 and Q2356

Switching from Engineering to Production BOM should only require changing PROJECT_PHASE:DEV to PROJECT_PHASE:PROD

Per <rdar://7542674 > K86/K87 Text note change

csa 45: Added PLACEMENT_NOTE for passive deemphasis circuit.

Changed K87_MCP BOM group to call out MCP89-A02csa 34: Changed U3440 from AP002 part to AP016 (343S0511) per <radar:7459498> BOM: APN updates for FPF1009 and SAK parts

Changed BOOTROM:PROG to call out 341T0251 (SUBASSY, IC, BOOT ROM, K86/K87)

Keeping K86 and K87 pgs identical for CSA 74, modifying BOM table for IMVP 1 phase on K87’s schematic to reflect changes for K86.

CSA 25: U2590 added, APN 353S2971. R2592 of 10K and C2592 of 1UF, C2593 of 1UF added.Nets MCP_PLL_LDO_EN and PP3V3_S0_LDO_R added.

2010-03-22: A.3.0

CSA 25: Copied from K62010-03-22: A.1.0

Summary of changes for MLB_LDO:

csa 74, csa 79:

Removed OMIT from R4585, R4586

2010-01-06: 1.11.0

2010-02-25: 2.19.0, 2.20.0

2010-03-04: B.0.0

CSA 74: Changed C7434 from 0.033uF to 0.047uF (APN 132S0189) per Liang

CSA 12: C1200, C1204, C1207, C1209, C1211, C1219, C1202, C1216 NOSTUFFEDPer <rdar://7488543> K87/K86 Task Measure each power supply in mlb.

CSA 69: C6970, C6971, C6972 of 1000pF (APN 131S0222) addedPer <rdar://7678515> K87:EMC:ESD: System hangs on air/contact discharge to MPM connector

CSA 4: MOLEX_DDR_CONN added to Module Parts, removed from Alternate table. Added second 639 and EEEE # to BOM table

2010-03-09: 0.8.0

** MLB_LDO branch

2010-02-26: 2.21.0

2010-02-25: 2.18.0

CSA 67: J6700 changed from APN 514-0718 to 514-0750

CSA 12: C1233, C1230, C1237, C1234 changed from NOSTUFF to STUFFED.

2010-02-15: 2.10.0

2010-02-18: 2.12.0

CSA 74: For K86 only: C7434 = 0.1uF added, R7417 changed to 8.25Kohm

2010-02-16: 2.11.0

2010-02-15: 2.9.0

2010-02-02: 2.8.0*** Resynced with T27 and K6 (no differences)*** Resynced Audio pages with the following changes:

csa 97: Changed R9710 from 7.32K 0402 1% to 7.68K (APN 114S0304) to support old K84 panelcsa 4: Added OLD_AUDIO_SWITCH BOM OPTION to K86_K87_COMMON1

csa 54: Broke sync with T27. Per <rdar://problem/7605797> K69/K86/K87 sensor IN1C unreliable U5400 changed from OPA348 to OPA330. C5434 changed to NOSTUFF

CSA 74: R7417 changed to 5.90K, C7428 changed to 0.47uF, C7434 changed to 0.033uF

csa 4: Added BOM entry under Module Parts table to include CULV processor (337S3779) to minimize delta on this page between K86 and K87 per Diana

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

csa 2: Updated CPU block text to include CPU description for both K86 and K87

Changed C9706 from 120pF to 220pF (131S2225) Changed C9705 from 8.2nF to 33nF (132S0131)

-pg. 67, no stuffed R6712 and R6713

*** Resynced Audio pages with the following changes:

Added L4530, L4531 (APN 155S0137) to SIL connector pinscsa 97: Per <rdar://problem/7589365> K86/k87: Compensation settings change to provide more phase margin, reduce ripple

-pg. 62, changed R6211 to 22 Ohms

csa 37: Per <rdar://problem/7554342> K86/K87: Change L3720 to 152S1182 Changed L3720 to 152S1182 (IND,PWR,SHD,4.7UH,20%,0.91A,31X31X12MM) for lower ESR

LPC_SERIRQ

Added text note with part numbers for components of the assembly

csa 69: Per <rdar://problem/7494087> K87: remove OMIT from J6955 and delete BOM table Changed K87_PROGPARTS BOM group to point to SMC:PROG_K87

- MCO: 056-3515

Created SMC:PROG_K87 pointing to 341T0252 (SUBASSY, IC, SMC, K87)

2009-12-16: 1.8.0

csa 25: T27: Removed R2575 & R2580 per DG v1.3 (pg. 25). per <radar:7459260 > Design Guide v1.3 updates

*** Started syncing the following pages:

T27: Added gain note for U5402 and SMC_BATT_ISENSE (pg. 54).

*** Other changes

Changed component color to Green

=PP3V3_S0_DPCONN’

csa 45: Added passive deemphasis to SATA HDD D2R lines:

2009-12-10: 1.6.0

=PP1V05_S0_MCP_AVDD_UF’

R7411 = 255 1% (114S0160)

=PPSPD_S0_MEM_B’

=PP5V_S0_HDD’

R7409 = 1.58k 1% (114S0236)

Added BOM table to insert the following APNs for IMVP6:1PHASE:

- UPDATED SCHEMATIC AND PCB PART NUMBER INFO

- ALL PAGES SYNC’ED FROM K84

2009-12-08: 1.3.0

INITIAL RELEASE 0.0.1-

2009-12-07: 1.2.0

2009-12-04: 1.1.0

=PP3V3_S0_PWRCTL’

=PP5V_S0_MCPREG’

csa 8: Deleted net properties for the following nets:2009-12-08: 1.4.0

10/1/2009:

2009-12-03: Proto 0 release 1.0.0

csa 74: Component value changes per Leo (Intersil):

C7434 from 0.12uF => 0.022uF, 10% (132S0102) Implemented different stuffing options for 1-phase vs 2-phase: Added IMVP6:2PHASE to the following components: R7417, C7428, R7409, R7411, C7406, R7414, C7414, C7413

C7428 = 0.22uF 10% (132S0102)

C7406 = 470pF 10% (132S4720) R7414 = 97.6k 1% (114S0410)

csa 74: Changed C7434 from NOSTUFF to IMVP6:2PHASE per Intersil

T27: Changed RC balance on BATT_ISENSE, same time constant (pg. 54).

Alternates table on csa 4 already has 152S0778 as alternate to 152S0693

STILL NEED TO UPDATE VALUE OF C7428!

C7414 = 1000pF 10% (132S0045)

Updated table to add new values for 1phase (PWM freq., Max current, Load line)

Added C4585, C4586 (10pF, 5%, 131S0029) and NOSTUFFed

csa 57: Began syncing from T27 per <radar:7304029 > T27 schematic bom option for R5714 & R5030 to keep K87 in sync

Added R5714 (114S0125) to table with BOMOPTION LED:K86_K87

2009-12-17: 1.9.0

csa 4: Added BOM table to substitute in parts that have BOMOPTION xxx:K6_K69 (to allow sync with T27)

R7417 = 7.68k 1% (114S0304)

R7417 from 5.36k => 6.34k, 1% (114S0296)

csa 34: Deleted net properties for =PP3V3_S3_WLAN

csa 4: Per <rdar://problem/7473229> K86: Move to MCP83

This is for K86 ONLY. Adding entry to minimize delta on csa 4 between K87 and K86

Per <rdar://problem/7495116> K87: remove ON Semi alternate for Q2300 (376S0624) Added LED:K86_K87 BOMOPTION to the K87_MISC BOM group

BOMOPTION is "MCP83M"

2009-12-22: 1.10.0

Updated DLY text note for U3440 to match T27 Changed R3454 to 100k, 1% (114S0411) to match T27 and K69

Added BOM table entry for MCP83M (337S3876)

- BOM: 639-0680

2010-01-07: 1.12.0

Changed BOMOPTION for R7872 from S0PGOOD_ISL to NOSTUFF

- Conn APN:518S0788"

csa 78: Per <rdar://problem/7495000> K87: Add NOSTUFF to R7872 to disconnect U7870 from ALL_SYS_PWRGD

- PCBF: 820-2801

"Assembly APN: 339S0114

Deleted OMIT BOMOPTION from J6955

LPCPLUS_GPIO

SMC_TMS

csa 23: *** BROKE SYNC WITH T27

csa 20; T27: Added CKPLUS_WAIVE properties to dismiss false errors (pg. 20). <radar:7368529> TASK: Waive false CheckPlus errors

2010-01-08: 2.0.0

Changed R4585, R4586 to 114S0065 (27.4 ohm, 1%)

csa 70: Per <rdar://problem/7519048> K86/K87: Change U7000 to 353S2929

Updated Q2355 and Q2356 with new schematic symbols

Changed K87_COMMON to call out K87_DEBUG_PVT instead of K87_DEBUG_ENG Diff from the two changes above:

Per <rdar://problem/7540522> K86/K87: Production Debug Components

csa 4: Per <rdar://problem/7540383> K86: Update CPU part number to 337S3792

R7417 changed to 7.87K (APN 114S0305)

R5714 has BOMOPTION LED:K6_K69, and we need to substitute a different part on csa 4

csa 74: Cosmetic change: moved R7413, C7406 BOMOPTION label so they don’t look like wire name

csa 7: Per <rdar://problem/7517432> K86/K87 functional net property needed on signals in schematics

Need to resync with T27 once the change has been made there

Changed U7000 from 353S2392 to 353S2929

Deleted BOM table that stuffsdel the bypass option

2010-01-13: 2.1.0

Changed U1000 CPU:1.2GHZ BOMOPTION from 337S3779 to 337S3792

Toggled:

BKLT:ENG ==> BKLT:PROD

Removed:

csa 74: Per <rdar://7525313 > K86 CPU loadline, OCP update

Added IMVP6:2PHASE BOM option to R7416 for K87’s 13.7K

Per <rdar://problem/7544629> K86/K87: Update MCP83 description on csa 4

Should switch syncing back to T27 once it is updated there

Changed BOM group structure to match that in the radar (see PDF attached to radar) Reverted back to ENG BOM, no longer PROD BOM (i.e. reverted much of 2.2.0 changes)

Per <rdar://problem/7495021> K86/K87: Replace "S" APNs with "T" APNs for programmed SMC and BR

csa 45: Per <rdar://problem/7524364> K86/K87: change SATA HDD D2R passive EQ values

BMON:ENG ==> BMON:PROD

SENS_R:ENG ==> SENS_R:PROD

DEBUG_ADC, S0PGOOD_ISL, EFI_DEBUG, MCPPLL_LDO, EXT1V05, MCP_T_DIODE_SENSOR, XDP_CON Unchanged: LPCPLUS, DEVEL_BOM, SMC_DEBUG:YES, XDP

Changed all instances of K87_DEVEL_xxxx to K87_DEVEL:xxxx

2010-01-18: 2.4.0

*** Resynced all synced pages and picked up the following (change notes from T27):

Revision History

=PP3V3_S0_CPUVTTISNS’

2010-01-28: 2.7.0

Changed BOMOPTIONs to be mutually exclusive (changed "_" to ":") Added row to EEE table for E3T

2010-01-19: 2.5.0

- REPLACED K84 MCP AND CPU PAGES WITH K6 PAGES

Changed R9726 from 22k to 10k (114S0315) and removed NOSTUFF

*** Resynced with T27 and K6 (no differences)

csa 4: Per <rdar://problem/7571786> K86/K87: Add E3T EEE code for K86 to schematic2010-01-22: 2.6.0

-pg. 66, added C6602

csa 45: Per <rdar://problem/7561001> K87:EMC: Radiated Emissions: Right Audio emissions fail

Added BOM table to stuff 0-ohms until we get go-ahead for filter

Added R4585, R4586 (51.1 ohm, 1%, 114S0093) and OMITted

csa 3: Updated text note to include "K86" in title

-pg. 67, added BOM options for U6700, R6712, and R6713 to support MAX14560 and MAX14504

Resync with T27 and K6. Clean up and rerelease schematic.

CSA 75: R7572 changed to 147K

Per <rdar://7644836> K87 power component update

CSA 69: J6955 BOMOPTION change to OMIT. Added BOM table with 607-6831 for J6955

2010-02-18: 2.17.0Per <rdar://7686179> K86/K87 schematic: Change audio jack part number for new connector cap

CSA 97: U9700 changed to APN 353S2965

CSA 12: For K86 only: C1272 = 330uF added.

2010-02-18: 2.16.0

Per <rdar://7634730> K86/K87: add an RC on the LVDS_IG_BKL_PWM

Per <rdar://7685202> K86/K87 schematic: change U9700 to 353S2965 for Freescale backlight issue

Per <rdar://7488543> K86/K86 Task: Measure each Power supply in MLB

Per <rdar://7676934> K86/K87: Hall eff documentation change. Substitute 607-6831 for doc purposes

CSA 97: R9725 changed to 200ohm, C9799 of 47pF added. R9726.1 connection moved to LVDS_IG_BKLPWM

CSA 70: R7015 changed to 56.2K, C7015 changed to 1000pF, C7042 changed to 0.068uF

CSA 12: Added pads for 0603 caps (APN 138S0635). Compoonents C1230, C1231, C1232, C1233, C1234, C1235, C1236, C1237.

Per <rdar://7685811> K86/K87 schematic: add additional 639 for differentiation between Foxconn and Molex DIMM connectors

Per <rdar://7683852> K87 Proto1: 5 of 6 systems failing graphics noise (Underwater) acoustic spec by up to 3.1dB

Changed R3790-R3795 to 116S0004 (0-ohm, 0402) from 22-ohm

csa 23: Per <rdar://problem/7544657> K86/K87: Fix schematic symbol for Q2355, Q2356

Net change was to move LPCPLUS to the 639 (from the 085)

csa 4: Per <rdar://problem/7549122> K86/K87: Switch to new BOM group structure

Cleaned up text notes for 1phase, 2phase, and edp #s per radar request.

CSA 4: Added Alternate part for U2592 LDO. 353S2987(TI), 353S2988(Micrel) to 353S2986(Intersil).

2010-03-22: A.5.0

Removed NOSTUFF from C4585, C4586

Per <rdar://problem/7519025> K86/K87: update all instances of 376S0786 schematic symbols

Removed Intersil LDO(353S2986).

csa 4: Added BOM table entry for MCP89-A02 per <radar:7416858 > Task: Get part numbers for A02 rev.

*** Made the following changes to follow T27 on the following unsynced pages:

T27: Added CKPLUS_WAIVE properties to dismiss false errors (pg. 54).

T27: Added BOMOPTIONs and APNs for Foxconn and Molex SO-DIMM connectors (pp. 29, 31).

2009-12-11: 1.7.0

csa 69: Added OMIT to J6955, BOM table to stuff K84 Hall effect connector

Revision HistorySYNC_DATE=MASTERSYNC_MASTER=MASTER

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Revision History

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Functional Test Points

FSB SIGNALS WITH NOTEST

(NEED TO ADD 1 GND TP)

(NEED 2 TP)

(NEED 4 TP)

(NEED 4 TP)


(NEED 2 TP)

DC POWER CONN FUNC_TEST




POWER NETS FUNC_TEST

(NEED 2 TP)

X16 WIRELESS CONN FUNC_TEST

(NEED 4 TP)

MIC FUNC_TEST

SPEAKER FUNC_TEST

J5100 LPC+SPI CONN FUNC_TEST





KEYBOARD CONN FUNC_TEST

(NEED 3 TP)

SATA ODD CONN FUNC_TEST

LVDS FUNC_TEST

IPD_FLEX_CONN FUNC_TEST


BATT POWER CONN FUNC_TEST

(NEED 2 TP)

FAN CONNECTORS FUNC_TEST


SATA HDD/SIL FUNC_TEST

HALL EFFECT CONNECTOR FUNC_TEST


TRUE SPI_MISO

PP3V3_S0_LCD_DDC_FTRUE

FSB_A_L<35..3>NO_TEST=TRUE

PM_SLP_S4_LTRUE

PP3V3_S3TRUE

PP1V5R1V35_S3TRUE

PP5V_SW_ODDTRUE

TRUE PP1V5_S0TRUE PP1V05_S0TRUE PPVCORE_S0_MCP

PP5V_S0TRUETRUE PP5V_S0TRUE PP1V8_S0

PPDDRVTT_S0TRUEPP0V9_S5TRUE

TRUE PP5V_S3_CAMERA_F

TRUE SMC_PM_G2_EN

PM_SLP_S3_LTRUE

PP4V5_AUDIO_ANALOGTRUE

PP3V3_S5_AVREF_SMCTRUE

TRUE PP3V3_SW_LCD_PANEL_FPPVOUT_S0_LCDBKLTTRUE

PP5V_S0_HDD_FLTTRUE

TRUE CONN_PCIE_MINI_D2R_N

TRUE PPVCORE_S0_CPU

FSB_HIT_LNO_TEST=TRUE

FSB_DINV_L<3..0>NO_TEST=TRUE

FSB_DSTB_L_N<3..0>NO_TEST=TRUE

FSB_LOCK_LNO_TEST=TRUE

FSB_HITM_LNO_TEST=TRUE

WS_CONTROL_KBDTRUETRUE WS_LEFT_OPTION_KBDTRUE WS_LEFT_SHIFT_KBD

WS_KBD15_CAPTRUE

TRUE CONN_PCIE_MINI_R2D_N

WS_KBD14TRUETRUE WS_KBD13

WS_KBD5TRUEFSB_D_L<63..0>NO_TEST=TRUE

FSB_ADS_LNO_TEST=TRUE

TRUE WS_KBD7

TRUE WS_KBD8

TRUE WS_KBD9

TRUE WS_KBD10

PP3V3_S3TRUE

USB_CAMERA_CONN_PTRUE

TRUE LVDS_IG_A_DATA_P<0>TRUE LVDS_IG_A_DATA_N<0>

TRUE LVDS_IG_A_DATA_N<1>

TRUE WS_KBD4

PSOC_SCLKTRUE

TRUE WS_KBD23

TRUE SATA_HDD_R2D_N

TRUE LVDS_IG_A_DATA_P<1>

TRUE SATA_HDD_D2R_C_P

TRUE PP3V42_G3H

TRUE SMC_LID_R

TRUE CONN_PCIE_MINI_R2D_P

TRUE Z2_HOST_INTN

TRUE PSOC_F_CS_L

TRUE PP3V3_S3_BT_F

WS_KBD_ONOFF_LTRUE

TRUE PP3V42_G3HWS_KBD1TRUE

TRUE ADAPTER_SENSETRUE PP18V5_DCIN_FUSE

PICKB_LTRUE

Z2_SCLKTRUE

TRUE PSOC_MOSIPSOC_MISOTRUE

TRUE SPKRAMP_L_N_OUT

TRUE Z2_MISO

TRUE Z2_CS_L

TRUE USB_CAMERA_CONN_N

NO_TEST=TRUE FSB_REQ_L<4..0>

FSB_DSTB_L_P<3..0>NO_TEST=TRUE

FSB_ADSTB_L<1..0>NO_TEST=TRUE

Z2_DEBUG3TRUE

Z2_CLKINTRUEZ2_KEY_ACT_LTRUE

TRUE Z2_BOOST_EN

WS_KBD22TRUE

TRUE LED_RETURN_5

TRUE PP5V_S0

TRUE CONN_PCIE_MINI_D2R_P

TRUE PCIE_CLK100M_MINI_CONN_P

PCIE_WAKE_LTRUE

BI_MIC_PTRUE

TRUE PP3V3_S0

TRUE PP3V3_S5

FAN_RT_TACHTRUE

PP3V42_G3HTRUETRUE SPI_CLK

TRUE PPVTT_S3_DDR_BUFTRUE PP1V05_S0_MCP_PLL_UF

TRUE SPKRAMP_R_P_OUT

BI_MIC_NTRUE

FAN_RT_PWMTRUE

TRUE PP3V42_G3H

TRUE PP3V3_G3_RTC

PP0V9_ENETTRUE

PPBUS_G3HTRUE

TRUE PP5V_S3

Z2_MOSITRUE

Z2_RESETTRUE

TRUE SMBUS_SMC_A_S3_SDA

WS_KBD2TRUETRUE WS_KBD3

TRUE WS_KBD11TRUE WS_KBD12

TRUE LED_RETURN_3TRUE LED_RETURN_2

TRUE LVDS_IG_A_CLK_F_PTRUE LVDS_IG_A_CLK_F_N

LED_RETURN_1TRUE

SMBUS_SMC_A_S3_SCLTRUE

TRUE PP3V3_SW_LCD_PANEL_F

TRUE LVDS_IG_DDC_CLK

TRUE LVDS_IG_DDC_DATA

TRUE PPVOUT_S0_LCDBKLT

TRUE SPKRAMP_SUB_P_OUT

TRUE CONN_USB2_BT_NAP_CLKREQ_Q_LTRUEAP_RESET_CONN_LTRUE

TRUE PP18V5_S3

TRUE PP3V3_WLAN

PP3V3_ENETTRUE

TRUE SPI_MOSI

PP18V5_S3TRUE

TRUE SPI_CS0_L

SPIROM_USE_MLBTRUETRUE LPCPLUS_GPIO

TRUE LPC_SERIRQTRUE SMC_TMS

WS_KBD21TRUETRUE WS_KBD20TRUE WS_KBD19TRUE WS_KBD18TRUE WS_KBD17

WS_KBD16_NUMTRUE

TRUE WS_KBD6

TRUE SMC_ODD_DETECT

TRUE SATA_HDD_D2R_C_NTRUE SYS_LED_ANODE_R

TRUE PPVBAT_G3H_CONN

TRUE PP5V_S0_HDD_FLT

CONN_USB2_BT_PTRUE

PP3V3_S3TRUE

TRUE BI_MIC_SHIELD

TRUE PCIE_CLK100M_MINI_CONN_NPP3V3_WLANTRUE

SPKRAMP_SUB_N_OUTTRUE

SPKRAMP_L_P_OUTTRUETRUE SPKRAMP_R_N_OUT

TRUE PP5V_SW_ODD

TRUE PP5V_S3_CAMERA_FTRUE LED_RETURN_6

TRUE LED_RETURN_4

TRUE LVDS_IG_A_DATA_P<2>LVDS_IG_A_DATA_N<2>TRUE

TRUE SMBUS_SMC_BSA_SDATRUE SYS_DETECT_L

TRUE SMBUS_SMC_BSA_SCL

TRUE SATA_HDD_R2D_P

TRUE SATA_ODD_D2R_C_PSATA_ODD_D2R_C_NTRUE

SATA_ODD_R2D_NTRUETRUE SATA_ODD_R2D_P

SYNC_DATE=MASTER

FUNC TESTSYNC_MASTER=MASTER

I449

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7 OF 109

C.0.0

051-8561

7 OF 76

72 37 19

64

69 14 10

62 36 35 19

8 7

75 8

46 33 7

75 62 8

62 8

39 8

62 8 7

62 8 7

8

8

8

64 7

62 35

66 62 35 19

48

36 35

64 7

67 64 46 7

33 7

75 30 9

39 8

69 14 10

69 14 10

69 14 10

69 14 10

69 14 10

43

43

43

43

75 30 9

43

43

43

69 14 10

69 14 10

43

43

43

43

8 7

75 64

71 64 9

71 64 9

71 64 9

43

44 43

43

71 33

71 64 9

71 33

8 7

54

75 30 9

44 43

44 43

30

43

8 7

43

54

54

44 43

44 43

44 43

44 43

52 51

44 43

44 43

75 64

69 14 10

69 14 10

69 14 10

44 43

44 43

44 43

44

43

67 64

62 8 7

75 30 9

75 30

30 16

75 53 52

75 62 8

75 62 8

42

8 7

72 37

8

8

52 51

75 53 52

42

8 7

23 20 19 8

8

39 8

8

44 43

44 43

74 38

43

43

43

43

67 64

67 64

75 64

75 64

67 64

74 38

64 7

64 9

64 9

67 64 46 7

52 51

75 30

30

30

44 7

30 7

8

72 37

44 7

72 37

47 37 19

37 19

37 35 19

37 36 35

43

43

43

43

43

43

43

35 33

71 33

33

55 54

33 7

75 30

8 7

53 52

75 30

30 7

52 51

52 51

52 51

46 33 7

64 7

67 64

67 64

71 64 9

71 64 9

74 38

54

74 38

71 33

71 33

71 33

71 33

71 33




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

0 MA

LVDDR VRef/VTT (0.75V/0.675V) Rails

4250 MA

DIGITAL GROUND

(CONNECTS TO THE DECAPS)

(SINCE PE0[3:0] IS NOT USED ON K6)

(CONNECTS TO MCP BALLS)

(CONNECTS TO MCP BALLS)

(CPU VCORE PWR)

"S3" RAILS "G3H" RAILS"S0,S0M" RAILS

UNUSED MCP PE0[3:0] AVDD/DVDD

(MCP VCORE AFTER SENSE RES)

(CONNECTS TO THE DECAPS)

FIX ME!! OUTPUT OF REGULATOR VALUES

105/241 MA

"S5" RAILS

"ENET" RAILS

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM

GND

VOLTAGE=0V

=PP3V3_S3_PDCISENS

=PP3V3_S3_MCP_GPIO

=PPBUS_G3H

=PP3V42_G3H_OPA330

=PP3V42_G3H_BMON_ISNS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPP3V42_G3H

VOLTAGE=3.42V

=PP3V42_G3H_HALL

=PPLVDDR_S3_MEM_A

MIN_NECK_WIDTH=0.17 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmPP1V5R1V35_S3

VOLTAGE=1.5V

=PP1V05_S0_MCP_PLL_IFP

=PP1V05_S0_MCP_DP0_VDD

=PP3V3_S0_FAN_RT=PPVCORE_S0_MCPGFXFET

=PP1V05_SW_MCP_FSB

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPPVCORE_S0_MCP

VOLTAGE=1.05VMAKE_BASE=TRUE

=PPVCORE_S0_MCP

PPVTT_S3_DDR_BUFMIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=0.75VMAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1.5 mm

VOLTAGE=1.5V

PP1V5_S0

MAKE_BASE=TRUE

=PPCPUVTT_S0_REG

MIN_NECK_WIDTH=0.20 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.30 MM

VOLTAGE=5V

PP5V_S0

=PP1V05_S0_CPU

=PP1V05_S0_MCP_FSB

=PPVIN_S3_DDRREG

=PPBUS_S5_CPUREGS_ISNS_R

PPBUS_G3H

MAKE_BASE=TRUE


VOLTAGE=12.6V

=PPVIN_S5_3V3S5

=PPBUS_S0_LCDBKLT

PPBUS_S5_IMVP_VTT_ISNSMIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6VMIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

=PP3V3_S3_BT

=PPDCIN_S5_CHGR

=PP3V42_G3H_ONEWIRE


PP3V3_S3


MIN_LINE_WIDTH=0.5 mm=PP5V_S0_LPCPLUS

=PP3V3_S5_REG

=PP3V3_S5_P3V3S3FET

=PP3V3_S5_MCPPWRGD

=PP3V3_S5_MCP

=PP3V3_S0_LCD_PANEL

=PP3V3_S0_FET

=PP3V3_S0_MCP_HVDD

=PP3V3_S0_P1V8S0

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_XDP

=PP3V3_S5_DP_PORT_PWR

=PP3V3_S5_P0V9S5

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P3V3S0FET

=PP3V3_S5_VMON

=PP3V3_S3_SMBUS_SMC_MGMT

=PPVCORE_S0_CPU

=PPVTT_S3_DDR_BUF

=PP5V_S0_CPU_IMVP

=PP5V_S0_FAN_RT

=PP5VR3V3_S0_DPCADET

=PP5V_S0_CPUVTTS0

=PP3V3_S3_VREFMRGN

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PP3V3_ENET_PHY_VDDREG

=PP3V3_ENET_PHY_VDDREG

=PP3V3_S3_SMBUS_SMC_A_S3

=PP5V_S3_P5VS0FET

=PP3V3_ENET_PHY

=PP1V5_S0_FET

=PP1V5R1V35_S0_MCPDDRFET

=PP1V5R1V35_S3_MCP_MEM

=PPDDR_S3_REG

=PPLVDDR_S3_MEM_B

=PPVIN_S0_DDRREG_LDO

=PP1V05_S0_REGPP1V05_S0_REG

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.4MMMAKE_BASE=TRUE

RTL8211_REGOUT

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.4MMMAKE_BASE=TRUE

=PP1V05_ENET_PHY

=PP0V9_ENET_FET

=PPDDRVTT_S0_MEM_B

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP3V3_ENET

=PP3V3_ENET_MCP_RMGT

=PP3V3_ENET_MCP_PLL_MAC

=PP3V3_ENET_FET

=PP0V9_ENET_P0V9ENETFET

=PP1V05_S0_MCP_PLL_UF_R

=PP1V05_S0_MCP_M2CLK_DLL

=PPVCORE_S0_CPU_REG

=PP3V42_G3H_REG

PPDDRVTT_S0


MAKE_BASE=TRUE


VOLTAGE=0.75V

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP5V_S3_REG

=PP3V3_S3_TPAD

MAKE_BASE=TRUEPP1V05_S0_MCP_PE_AVDD

=PP1V05_S0_MCP_PE_DVDD1 =PP1V05_S0_MCP_PE_DVDD

=PP1V05_S0_MCP_PE_AVDD0

=PP1V05_S0_MCP_PE_DVDD0

=PP3V3_S3_FET

=PPVIN_S5_SMCVREF

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S5_SMC

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_TPAD

=PP3V42_G3H_CHGR

=PP3V3_S5_LPCPLUS


=PPVIN_S0_CPUVTTS0

=PPVIN_S5_CPU_IMVP

=PP1V05_S0_MCP_PLL_UF

=PPBUS_S5_CPUREGS_ISNS

=PP5V_S3_MCPDDRFET

=PP18V5_DCIN_CONN

PP1V8_S0MIN_LINE_WIDTH=0.10MM


MIN_NECK_WIDTH=0.10MM

=PP3V3R1V5_S0_AUDIO

=PP1V8R1V5_S0_AUDIO

=PP1V5_S0_CPU

=PPDDRVTT_S0_MEM_A

=PPVTT_S0_DDR_LDO

=PP1V05_S0_MCP_PLL_OR PP1V05_S0_MCP_PLL_UF

MIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V


MAKE_BASE=TRUE

PP3V3_G3_RTC

=PP3V3_S3_SMS

=PP1V05_S0_MCP_SATA_DVDD

=PPMCPCORE_S0_REG

=RTL8211_REGOUT

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmPP0V9_ENET

VOLTAGE=0.9V


=PP1V5_S0_MCP_PLL_VLDO

=PP1V8_S0_REG

=PP3V3R1V5_S0_MCP_HDA

VOLTAGE=1.05V MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.4MMMAKE_BASE=TRUE

PP1V05_ENET


=PP5V_S3_AUDIO_AMP

=PP3V3_S3_WLAN

=PP5V_S0_MCPFSBFET

=PP5V_S0_FET

=PP3V3_S0_AUDIO

=PP3V3_S0_IMVP

=PP3V3_S0_LCD_DDC

MAKE_BASE=TRUEVOLTAGE=5VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP5V_S3

=PP5V_S3_EXTUSB

=PPVIN_S3_5VS3

VOLTAGE=18.5V

PP18V5_G3HMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

=PPVIN_S0_MCPCORE


=PPSPD_S0_MEM_A

=PP3V3_S0_MCP_GPIO


=PP5V_S3_ODD

=PP5V_S3_SYSLED

=PP5V_S3_DEBUG_ISNS

=PP5V_S3_AUDIO

=PP5V_S3_TPAD

=PP5V_S3_DEBUG_ADC_AVDD

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUEVOLTAGE=1.05V

PP0V9_S5

=PP0V9_S5_MCP_VDD_AUXC

=PP5V_S3_CAMERA

=PP5V_S3_DEBUG_ADC_DVDD

=PP5V_S3_DDRREG

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=0.20MM

PP3V3_S5MIN_LINE_WIDTH=0.30MM

=PP3V3_S5_MCP_GPIO

=PP3V3_S5_ROM

=PP0V9_S5_REG

=PP3V3_S0_ODD

=PP3V3_S0_MCP

=PP3V3_S0_SMC

=PP3V3_S0_MCPTHMSNS

=PP5V_S0_HDD

=PP5V_S0_MCPREG

=PP1V05_S0_MCP_AVDD_UF

=PPSPD_S0_MEM_B

=PP3V3_S0_PWRCTL

=PP3V3_S0_DPCONN

=PP3V3_S0_CPUVTTISNS

=PP1V05_S0_MCP_PE_DVDD

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.3 MMVOLTAGE=1.25V


MAKE_BASE=TRUE

=PP3V3_S0_CPUTHMSNS


=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_DEBUGROM


MAKE_BASE=TRUE

PP3V3_S0

VOLTAGE=3.3V

=PP3V3_S0_MCPCOREISNS

=PP3V3_S0_OPA330

MAKE_BASE=TRUEVOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

PP1V05_S0


Power Aliases

R0814

402MF-LF

ENET1V05:INT

5%

0

1/16W

R0813ENET1V05:EXT

1/16W

0

5%402 MF-LF

R0812402

0

MF-LF

ENET1V05:INT

1/16W5%

8 OF 109

C.0.0

051-8561

8 OF 76

1 2

1 2

1 2

19

55

40

7

54

26

75 7

24 17

24 17

42 22

23 20

39 7

23 20

7

75 62 7

60

62 7

13 12 11 10

23 20 14

57

40

39 7

56

68

30

55

54

7 37

56

63

25

23 20

64

63

23 20

61

38

38

38

13

66

61

63

63

62

38

12 11

57 29

58

42

66

60

29

31

38

63

31 9

63

21

15

63 57

27

57

61 31

63

27

7

23 20 18 9

23

63 62 61 9

63

61

23 15

58

54

7

24 17

56

44 43

23

20 23 8

20

20

63

36

62

38

36 35

34

43

62 55

37

20

60

58

23

40

21

54

7

48

48

12 11

26

57

61 7

23 20 19 7

45

23 20

59

31

7

23 20

61

61

23 19

63

51

30

22

63

53 52 48

58

64

7

34

56

59

38

26

19 18 17

23

33

36

46

52 50 48

44

46

7

23 20

64

46

57

75 62 7

19 18

47

61

33

23 20

36

41

33

59

23

27

62

66

40

23 8

39 7

41

61

40

37

75 62 7

40

23

62 7

OUTIN

IN

IN

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

BI

OUT

OUT

OUT

IN

IN

BI

BI

BI

BI

OUT

IN

IN

OUT

OUT

BI

BI

IN

BI

BI

BI

BI

OUT IN

OUT

OUT

OUT

OUT

IN

IN

IN OUT

IN

OUT

OUTIN

IN

OUT

IN

OUTIN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

USB ALIASESUNUSED USB PORTS

SMC ALIASES

LVDS ALIASES

ETHERNET ALIASES

1 1 1

BSEL<2..0>

0 0 10 1 00 1 11 0 01 0 11 1 0

0 0 0133200

333100

(RSVD)

(166)

(400)

266

FSB MHZ

MCP89 MISC ALIASES

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

MLB MOUNTING (TO TOPCASE) SCREW HOLES

LVDS CONNECTOR HOLE

EMI THINBC POGO PINS

EMI TALL POGO PINS (870-1698 )

LEFT OF CPU

EMI IO MEDIUM POGO PINS

PCI-E ALIASES

ABOVE CPU

BELOW CPU

(870-1794 )

HEATSINK STANDOFFS

FAN STANDOFF

UNUSED GPU LANES

CPU FSB FREQUENCY STRAPS

CHARGER SIGNAL

MCP89 ETHERNET VREF

UNUSED ETHERNET LANE

UNUSED FIREWIRE LANE

DISPLAY PORT ALIASES

BELOW MCP

(870-1820 )

CPU VCORE ALIASES

=PEG_D2R_P<15:0>

MAKE_BASE=TRUE

PCIE_AP_D2R_N

MAKE_BASE=TRUE

PCIE_AP_D2R_P

MAKE_BASE=TRUE

PCIE_AP_R2D_C_NPCIE_MINI_R2D_C_N

CONN_PCIE_MINI_D2R_P

CONN_PCIE_MINI_D2R_N

DP_IG_AUX_CH1_N

DP_IG_ML1_P<0..3>

DP_IG_ML0_N<0..3>

=MCP_IFPA_TXC_P

LCD_IG_PWR_EN

LCD_IG_BKLT_EN

=PP3V3_ENET_PHY

MAKE_BASE=TRUE

TP_USB_EXTD_N

TP_USB_EXTC_NMAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_P<0..3>NO_TEST=TRUE MAKE_BASE=TRUE

LVDS_IG_BKL_ON

NC_LVDS_IG_B_CLK_NNO_TEST=TRUE MAKE_BASE=TRUE

LVDS_IG_BKL_PWM

LVDS_IG_A_CLK_PMAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_P3NO_TEST=TRUE MAKE_BASE=TRUE

TP_ENET_CLK125M_TXCLK

TP_ENET_TXD<0..3>

ENET_CLK125M_TXCLKMAKE_BASE=TRUE

ENET_TX_CTRLMAKE_BASE=TRUE

TP_SMC_SYS_KBDLEDMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

=MCP_BSEL<0:2>

CPU_PECI_MCP

MAKE_BASE=TRUECPU_BSEL<0:2>

PCIE_ENET_R2D_C_N

PCIE_CLK100M_ENET_N

TP_PCIE_CLK100M_ENET_PMAKE_BASE=TRUE

MAKE_BASE=TRUE

LVDS_IG_A_DATA_P<0..2>

LVDS_IG_A_DATA_N<0..2>MAKE_BASE=TRUE

=MCP_IFPA_TXD_N<0..2>

=MCP_IFPA_TXD_P<0..2>

PCIE_AP_R2D_PMAKE_BASE=TRUE

MAKE_BASE=TRUE

LVDS_IG_DDC_CLK

MAKE_BASE=TRUE

TP_FW_CLKREQ_L

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

ENET_ENERGY_DET

PCIE_CLK100M_FW_P

=PP3V3_ENET_FET

PCIE_ENET_R2D_C_P

TP_MCP_MEM_VDD_SEL_1V5MAKE_BASE=TRUE

MCP_MEM_VDD_SEL_1V5

TP_ENET_CLKREQ_LMAKE_BASE=TRUE

LVDS_IG_A_CLK_NMAKE_BASE=TRUE

TP_ENET_MDC

TP_MCP_CLK25M_BUF0_R

TP_ENET_TX_CTRL

TP_ENET_RESET_L ENET_RESET_LMAKE_BASE=TRUEMCP_CLK25M_BUF0_RMAKE_BASE=TRUE

MAKE_BASE=TRUEENET_TXD<0..3>

TP_USB_MINI_PMAKE_BASE=TRUE

TP_USB_T57_NMAKE_BASE=TRUE

TP_USB_T57_PMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_USB_WM_N

TP_USB_WM_PMAKE_BASE=TRUE

USB_WM_N

USB_IR_N TP_USB_IR_NMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_DP_IG_ML1N<0..3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLK_PNO_TEST=TRUE

NC_LVDS_IG_B_DATA_N<0..3>NO_TEST=TRUE MAKE_BASE=TRUE

=MCP_IFPA_TXC_N

=MCP_IFPAB_DDC_DATA

USB_MINI_PPCIE_CLK100M_AP_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PCIE_CLK100M_AP_N

CONN_PCIE_MINI_R2D_P

CONN_PCIE_MINI_R2D_N

=PEG_D2R_N<15:0>

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_N

TP_PCIE_CLK100M_FW_NMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_PMAKE_BASE=TRUE

TP_FW_PME_L

FW_PWR_EN

PCIE_FW_D2R_N

LCD_IG_BKLT_PWM

MAKE_BASE=TRUENO_TEST=TRUE

NC_PEG_R2D_C_P<15:0>


NC_PEG_D2R_P<15:0>


NC_PEG_D2R_N<15:0>

MAKE_BASE=TRUE

PCIE_AP_R2D_N

DP_IG_ML_N<0..3>

DP_IG_HPD1

=MCP_IFPA_TXD_P<3>

NC_LVDS_IG_A_DATA_N3NO_TEST=TRUE MAKE_BASE=TRUE

USB_EXTC_N

TP_PCIE_CLKREQ_LMAKE_BASE=TRUE

=PEG_R2D_C_P<15:0>

=PEG_R2D_C_N<15:0>

USB_EXTD_NMAKE_BASE=TRUE

TP_USB_EXTD_PUSB_EXTD_P

USB_EXTC_P

TP_USB_SDCARD_PMAKE_BASE=TRUE

USB_MINI_N

USB_T57_N

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

USB_T57_P

USB_SDCARD_NMAKE_BASE=TRUE

TP_USB_SDCARD_N

USB_WM_P

USB_SDCARD_P

PEG_CLK100M_P

PEG_CLKREQ_L

PCIE_AP_R2D_C_PMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_USB_IR_PUSB_IR_P

=MCP_IFPAB_DDC_CLK

MAKE_BASE=TRUE

TP_USB_EXTC_P

TP_USB_MINI_NMAKE_BASE=TRUE

PCIE_MINI_R2D_C_P


NC_PEG_R2D_C_N<15:0>

PEG_CLK100M_NMAKE_BASE=TRUE

TP_PEG_CLK100M_N

MAKE_BASE=TRUE

TP_PEG_CLK100M_P

MAKE_BASE=TRUEENET_MDC

MAKE_BASE=TRUE

LVDS_IG_DDC_DATA

DP_EXT_HPDMAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_EXT_CA_DET

DP_EXT_AUX_CH_C_NMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_DP_IG_AUX_CH1N

DP_EXT_ML_P<0..3>MAKE_BASE=TRUE

DP_IG_ML_P<0..3>

DP_EXT_AUX_CH_C_PMAKE_BASE=TRUE

SMC_SYS_KBDLED

SMC_BC_ACOKMAKE_BASE=TRUE


MCP_RGMII_VREF

=RTL8211_ENSWREG

=MCP_IFPB_TXD_N<0..3>

=MCP_IFPB_TXD_P<0..3>

=MCP_IFPB_TXC_P

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

TP_PCIE_FW_R2D_C_N

TP_PCIE_FW_R2D_C_PMAKE_BASE=TRUE

PCIE_FW_D2R_P

PCIE_FW_R2D_C_N

=MCP_IFPB_TXC_N

=MCP_IFPA_TXD_N<3>

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_P

PCIE_FW_R2D_C_P

FW_PME_L

ENET_CLKREQ_L

TP_PCIE_ENET_D2R_PMAKE_BASE=TRUE

PCIE_CLK100M_ENET_P

PCIE_CLK100M_FW_N

RTL8211_ENSWREGMAKE_BASE=TRUEMIN_LINE_WIDTH=0.4MM

MIN_NECK_WIDTH=0.2mm

DP_EXT_ML_N<0..3>MAKE_BASE=TRUE

TP_PCIE_CLK100M_ENET_NMAKE_BASE=TRUE

DP_IG_AUX_CH1_P

DP_IG_HPD0

DP_IG_ML1_N<0..3>

DP_AUX_CH_C_N

DP_AUX_CH_C_P

DP_CA_DET

TP_PCIE_ENET_R2D_C_NMAKE_BASE=TRUE

TP_PCIE_ENET_R2D_C_PMAKE_BASE=TRUE

TP_PCIE_ENET_D2R_NMAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_IG_AUX_CH_N

MAKE_BASE=TRUE

TP_DP_IG_ML1P<0..3>

TP_DP_IG_AUX_CH1PMAKE_BASE=TRUE

DP_IG_ML0_P<0..3>

DP_IG_AUX_CH0_NMAKE_BASE=TRUE

DP_IG_AUX_CH_PDP_IG_AUX_CH0_P

TP_FW_PWR_ENMAKE_BASE=TRUE

IMVP6_NTCMAKE_BASE=TRUE

TP_IMVP6_NTC

TP_IMVP6_VR_TTMAKE_BASE=TRUE

=CHGR_ACOK

IMVP6_VR_TT

FW_CLKREQ_L

SYNC_DATE=(02/04/2009)

SIGNAL ALIASSYNC_MASTER=(K84_MLB)

2.0DIA-MLB-THIN-BC-K84ZS0920

SM

NOSTUFF

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98ZS0919

SM

ZS0918

SM

OMIT

2.0DIA-MLB-THIN-BC-K84

ZS0917

OMIT

SM

2.0DIA-MLB-THIN-BC-K84

ZS09122.0DIA-TALL-EMI-MLB-M97-M98

SM

OMIT ZS09132.0DIA-TALL-EMI-MLB-M97-M98

SM

OMIT OMITZS0914

2.0DIA-TALL-EMI-MLB-M97-M98SM

ZS0915

SM

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

ZS09162.0DIA-MLB-THIN-BC-K84

SM

OMIT

Z0905OMIT

3P2R2P7

Z0913OMIT

3P2R2P7

ZS09112.0DIA-MED-EMI-MLB-K84

OMIT

SM

ZS0909

SM2.0DIA-MED-EMI-MLB-K84

OMITZS0908

2.0DIA-MED-EMI-MLB-K84

OMIT

SM


OMIT

SM

ZS0902

SM

OMIT

2.0DIA-MED-EMI-MLB-K84

OMITZS0901

SM2.0DIA-MED-EMI-MLB-K84


OMIT

SM

ZS0910OMIT

SM


Z0906OMIT

3P2R2P7

Z09073P2R2P7

OMIT

ZS0907

SM


OMIT

ZS0904OMIT


OMITZS0906

SM

2.0DIA-TALL-EMI-MLB-M97-M98ZS0905


OMIT

Z09103P2R2P7

OMIT

R0940

5%1/16W

402

100K

MF-LF

69 10 14

Z0903STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902STDOFF-4.5OD.98H-1.1-3.48-TH

Z0904STDOFF-4.5OD.98H-1.1-3.48-TH

Z0901STDOFF-4.5OD.98H-1.1-3.48-TH

Z0911OMIT

3P2R2P7

58

31

58

R0916ENET1V05:EXT

402MF-LF1/16W5%0

R091505%1/16WMF-LF

ENET1V05:INT

402

18 63 62 61 8

R0970

MF-LF1/16W5%

100K

402

R09581.47K

1/16W1%

MF-LF402

C09580.1UF

CERM

20%

402

10V

R0957

1%

402

1/16W

1.47K

MF-LF

18

19

64 7 17

17

17

71 64 7

71 64 7

71

71

66 65

65

65

75 66

75 66

66

71 65

71 65

75 66

75 66

17

17

17

17

17

17

17

17

17

64

68

68 67

64 7

71 64

71 64

17

17

17

17

17

17

17

17

17

17

17

17

55 54 36 35

9 OF 109

C.0.0

051-8561

9 OF 76

1

2

2

11

2

1 2

1

2

1

2

1

1

1

1

1

1 2

1

1 11

1

11

1

1 1 1

11 1 1

1

1

1

111

1

11

1

1

16

71 16

71 16

71 16 30

75 30 7

75 30 7

31 8

18

18

73 31

73 31

14

71 16

71 16

71

71 16

71 16

71 16

71 16

18

18

18

18 73 31

73 31

73 31

72 18

72 18

72 18 71 16

71 16

75 30 7

75 30 7

16

16

71 16

71

17

72 18

16

16

72 18

72 18

72 18

72 18

72 18

30

30

72 18

72 18

72 18

72 18

71 16

16

71 16

72 18

30

71 16

73 31

35

23 20 18 8 71 16

71 16

71 16

16

16

71 16

71 16

16

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

OUT

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

BI

BI

BI

BI

TEST7

TEST6

DSTBP1*

DINV1*

D31*

D30*

D25*

D11*

D12*

D13*

D14*

DSTBP0*

DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0* D32*

D1*

D2*

D5*

D16*

D20*

D21*

D22*

D23*

D24*

D26*

D27*

D28*

D29*

DSTBN1*

GTLREF

TEST3

TEST4

TEST5

BSEL0

BSEL1

BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2*

DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3*

DSTBP3*

DINV3*

COMP0

COMP1

COMP2

COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3

DATA GRP 2

MISC

DATA GRP 0

DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3*

A4*

A14*

A16*

REQ0*

REQ1*

REQ2*

REQ3*

REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20*

A21*

A22*

A23*

A24*

A26*

A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5

RSVD6

RSVD7

RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

R1005.2:

C1014.1:R1006.1:

PLACE_NEARs:

PLACE_NEARs:

R1022.1:R1021.1:R1020.1:

R1023.1:

CPU JTAG Support

54.91%

1/16WMF-LF

402

R1000

685%

1/16WMF-LF

402

R1002

1K1%1/16WMF-LF402 U1000.AD26:12.7 mm

R1005

2.0K1%1/16WMF-LF402

U1000.AD26:12.7 mm

R1006

1%

MF-LF402

1/16W

54.9

U1000.Y1:12.7 mm

R1023

27.41%1/16WMF-LF402

U1000.AA1:12.7 mm

R1022

54.91%

1/16WMF-LF

402

U1000.U26:12.7 mm

R1021

1%

MF-LF402

1/16W

27.4

U1000.R26:12.7 mm

R1020

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

14 58 69

14 69

14 69

14 69

58

13 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

9 69

9 69

9 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

7 14 69

14 69

14 69

14 69

14 69

14 69

14 69

7 14 69

7 14 69

7 14 69

13 69

13 69

13 69

13 69

13 69

13 69

10 13 69

13 25

14 36 69

41 75

14 36 69

14 69

13 14 69

14 69

14 69

14 69

14 69

10 13 69

10 13 69

10 13 69

10 13 69

41 75

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

402

5%

MF-LF

0

NO STUFF

1/16W

R1010

1K5%

1/16WMF-LF

402

NO STUFFR1011

54.91%

1/16WMF-LF

402

R1001

402

1%

MF-LF1/16W

54.9R1090

402

1%

MF-LF1/16W

54.9R1091

402

1%

MF-LF1/16W

54.9R1093

7 14 69

7 14 69

7 14 69

7 14 69

402

1%

MF-LF1/16W

649R1094

1K5%1/16WMF-LF402

NO STUFFR1012

0.1uF

402

10%

NO STUFF

U1000.AF26:12.7 mm

X5R16V

C1014

PENRYN

OMIT

FCBGA

U1000

402

1%

54.9

MF-LF1/16W

PLACE_NEAR=J1300.51:12.7 mm

R1092

FCBGAPENRYN

OMIT

U1000

SYNC_DATE=02/16/2010SYNC_MASTER=T27_MLB

CPU FSB

FSB_D_L<16>

CPU_COMP<3>CPU_COMP<2>CPU_COMP<1>

FSB_D_L<63>

CPU_COMP<0>

TP_CPU_RSVD_D3TP_CPU_RSVD_D22TP_CPU_RSVD_D2TP_CPU_RSVD_F6

FSB_A_L<5>

FSB_A_L<15>

FSB_A_L<10>

FSB_ADS_L

CPU_IGNNE_L

CPU_THERMD_N

FSB_A_L<25>

FSB_A_L<11>

FSB_A_L<7>FSB_A_L<8>FSB_A_L<9>

FSB_A_L<27>FSB_A_L<26>

FSB_A_L<24>FSB_A_L<23>FSB_A_L<22>FSB_A_L<21>FSB_A_L<20>

FSB_BPRI_L


FSB_ADSTB_L<0>


FSB_A_L<28>FSB_A_L<29>FSB_A_L<30>FSB_A_L<31>FSB_A_L<32>FSB_A_L<33>FSB_A_L<34>FSB_A_L<35>FSB_ADSTB_L<1>

CPU_FERR_L

CPU_STPCLK_LCPU_INTRCPU_NMICPU_SMI_L

TP_CPU_RSVD_M4TP_CPU_RSVD_N5TP_CPU_RSVD_T2TP_CPU_RSVD_V3TP_CPU_RSVD_B2

FSB_BNR_L

FSB_DEFER_LFSB_DRDY_LFSB_DBSY_L

FSB_BREQ0_L

FSB_CPURST_LFSB_RS_L<0>FSB_RS_L<1>FSB_RS_L<2>FSB_TRDY_L

FSB_HIT_LFSB_HITM_L

XDP_BPM_L<1>XDP_BPM_L<2>XDP_BPM_L<3>XDP_BPM_L<4>

XDP_TCKXDP_TDIXDP_TDOXDP_TMSXDP_TRST_LXDP_DBRESET_L

CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P

FSB_REQ_L<4>FSB_REQ_L<3>FSB_REQ_L<2>FSB_REQ_L<1>FSB_REQ_L<0>

FSB_A_L<16>

FSB_A_L<14>


FSB_A_L<6>

CPU_A20M_L

CPU_INIT_L

FSB_LOCK_L

FSB_D_L<10>

FSB_D_L<15>FSB_DSTB_L_N<0>

FSB_D_L<3>FSB_D_L<4>

FSB_D_L<17>

CPU_PSI_LFSB_CPUSLP_LCPU_PWRGDFSB_DPWR_LCPU_DPSLP_LCPU_DPRSTP_L

FSB_DINV_L<3>FSB_DSTB_L_P<3>FSB_DSTB_L_N<3>

FSB_D_L<62>FSB_D_L<61>FSB_D_L<60>FSB_D_L<59>FSB_D_L<58>FSB_D_L<57>FSB_D_L<56>FSB_D_L<55>FSB_D_L<54>FSB_D_L<53>FSB_D_L<52>FSB_D_L<51>FSB_D_L<50>FSB_D_L<49>FSB_D_L<48>

FSB_DINV_L<2>FSB_DSTB_L_P<2>FSB_DSTB_L_N<2>FSB_D_L<47>FSB_D_L<46>FSB_D_L<45>FSB_D_L<44>FSB_D_L<43>FSB_D_L<42>FSB_D_L<41>FSB_D_L<40>FSB_D_L<39>FSB_D_L<38>FSB_D_L<37>FSB_D_L<36>FSB_D_L<35>FSB_D_L<34>FSB_D_L<33>

CPU_BSEL<2>CPU_BSEL<1>CPU_BSEL<0>

TP_CPU_TEST5

TP_CPU_TEST3

FSB_DSTB_L_N<1>

FSB_D_L<29>FSB_D_L<28>FSB_D_L<27>FSB_D_L<26>

FSB_D_L<24>FSB_D_L<23>FSB_D_L<22>FSB_D_L<21>FSB_D_L<20>

FSB_D_L<5>





FSB_DINV_L<0>FSB_DSTB_L_P<0>


FSB_D_L<25>


FSB_DINV_L<1>FSB_DSTB_L_P<1>

TP_CPU_TEST6TP_CPU_TEST7

CPU_IERR_L

XDP_BPM_L<5>

CPU_PROCHOT_L

XDP_TMS

XDP_TDI

CPU_GTLREF

XDP_TCK

XDP_TRST_L

CPU_TEST4

=PP1V05_S0_CPU

XDP_BPM_L<0>

FSB_CLK_CPU_N

XDP_TDO

CPU_TEST2CPU_TEST1

10 OF 109

C.0.0

051-8561

10 OF 76

1

2

1

2

1

2

1

21

2

1

2

1

2

1

2

1 2

1

2

1

2

1 2

1 2

1 2

1 2

1

2

2

1

C3

A26

M26

N24

N25

T25

P23

J23

H22

F26

K22

H26

H25

G24

K24

E23

E25

R23

P26

E22 Y22

F24

E26

G25

N22

L23

M24

L22

M23

P25

P22

T24

R24

L25

L26

AD26

C24

AF26

AF1

B22

B23

C21

AB24

V24

V26

V23

T22

U25

U23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

Y26

AA26

U22

AE24

AD24

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

AC22

AD23

AF22

AC23

AE25

AF24

AC20

R26

U26

AA1

Y1

E5

B5

D24

D6

D7

AE6

K25

F23

G22

J26

H23

J24

D25

C23

1 2

H4

B3

A6

K5

J4

L5

P4

R1

K3

H2

K2

J3

L1

A21

A22

C7

A24

D21

C20

AB6

AB5

AB3

AA6

AC5

AC1

AC2

AC4

AD1

AD3

AD4

E4

G6

G2

G3

F4

F3

C1

D20

F1

E1

F21

H5

E2

B2

V3

T2

N5

M4

A3

B4

C6

D5

A5

V1

AA3

AB2

AA4

W3

V4

U2

Y4

W5

R3

U5

Y2

M1

L2

P2

G5

W6

U4

Y5

U1

R4

T3

W2

J1

N2

M3

P5

T5

B25

C4

H1

N3

P1

L4

F6

D2

D22

D3

69

69

69

69

69

10 13 69

10 13 69

29 69

10 13 69

10 13 69

8 11 12 13

10 13 69

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

VCC

VCCP

VCCA

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4




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8 7 5 4 2 1

(BR1#)

130 mA

(CPU INTERNAL PLL POWER 1.5V)

2500 mA (after VCC stable) 4500 mA (before VCC stable)

(CPU IO POWER 1.05V)

23 A (LV Design Target)30.4 A (SV LFM)

41 A (SV HFM) 44 A (SV Design Target)

(CPU CORE POWER)

(Socket-P KEY)

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

58 69

58 69

58 69

58 69

58 69

58 69

MF-LF402

1001%1/16W

PLACE_NEAR=U1000.AE7:25.4 mm

R1101

58 69

58 69

58 69

OMIT

PENRYNFCBGA

U1000

OMIT

PENRYNFCBGA

U1000

1001%1/16WMF-LF402

PLACE_NEAR=U1000.AF7:25.4 mm

R1100


CPU Power & Ground

CPU_VID<6>CPU_VID<5>CPU_VID<4>CPU_VID<3>CPU_VID<2>CPU_VID<1>CPU_VID<0>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

=PPVCORE_S0_CPU

11 OF 109

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1

2

AD15

AD17

AD18

C15

A7

A10

A13

A17

B15

B17

B20

C17

C18

D9

D12

D14

D18

E7

E9

E10

E12

E13

E15

E17

E18

E20

F7

F9

F10

F12

F14

F15

F18

F20

AA7

AA9

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AB9

AC10

AB10

AB12

AB14

AB15

AB17

AB18

AB20

AB7

AC7

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

AD14

AE9

AE10

AE12

AE13

AE15

AE17

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

G21

V6

J6

K6

M6

J21

K21

M21

N21

N6

R21

R6

T21

T6

V21

W21

B26

C26

AD6

AF5

AE5

AF4

AE3

AF3

AE2

AF7

AE7

A9

A12

A15

B14

B18

C9

C10

C12

C13

D10

D15

D17

B12

B10

B7

A18

F17

B9

A20

N23

N26

B1

P3

E19

B19

A23

D16

D11

D4

D1

C25

C22

C2

T4

B8

A4

A8

A11

A14

A16

A19

AF2

B11

B13

B16

B21

B24

C5

C8

C11

C14

C16

C19

D8

D13

D26

E3

E6

E11

E14

E16

E24

F5

F8

F11

F13

F16

F19

F2

F22

F25

G4

G1

G23

G26

H3

H6

H21

H24

J2

J5

J22

J25

K1

K4

K23

K26

L3

L21

L24

M2

M5

M22

M25

N1

N4

P6

P21

P24

R2

R5

R22

R25

T1

T23

T26

U3

U6

U21

U24

V2

V5

V22

V25

W1

W4

W23

W26

Y3

Y6

Y21

Y24

AA2

AA5

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

AE19

AE23

AE26

A2

AF6

AF8

AF11

AF13

AF16

AF19

AF21

A25

AF25

E8

E21

L6

D23

D19

B6

1

2

8 12

8 10 12 13

8 11 12

8 11 12




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8 7 5 4 2 1

PLACEMENT_NOTE (C1200-C1219):

4X 330UF. 20X 22UF 0805

1x 10uF, 1x 0.01uF

1x 330uF, 6x 0.1uF 0402

VCCA (CPU AVdd) DECOUPLING

VCCP (CPU I/O) DECOUPLING

CPU VCore HF and Bulk Decoupling

PLACEMENT_NOTE (C1240-C1243):

20%

CRITICAL

22UF

CERM-X5R6.3V

805

Place inside socket cavity on secondary side.

C1206

C126020%

2.0VPOLY-TANTD2T-SM2

330UF

PLACEMENT_NOTE=Place C1260 between CPU & NB.

CRITICAL

NO STUFFCRITICAL

6.3VX5R-CERM

20%

603

22UFC1236

CRITICALC123522UF

X5R-CERM

NO STUFF

603

6.3V20%

6.3V20%

X5R-CERM

CRITICALC1234

603

22UF6.3V

603X5R-CERM

CRITICAL

20%22UFC1233

CRITICALNO STUFF

C1231

603X5R-CERM6.3V20%22UF

CRITICALC123222UF20%

NO STUFF

X5R-CERM603

6.3V

CRITICAL

22UF20%

X5R-CERM

C1230

603

6.3V

NO STUFF

805

CRITICAL

CERM-X5R6.3V20%


22UFC1204

C123720%6.3VX5R-CERM603

22UF

CRITICAL

22UF

805CERM-X5R6.3V20%


C1216CRITICALNO STUFF

CRITICALC121422UF

805CERM-X5R6.3V20%


C1208CRITICAL

22UF

805CERM-X5R6.3V20%


22UF20%6.3V

805

C1203


CERM-X5R

CRITICAL

NO STUFF

20%22UF

805CERM-X5R6.3V


C1207CRITICAL

NO STUFF

6.3V

22UFC1202

805

20%


CERM-X5R

CRITICALCRITICAL

22UF20%

C1201


6.3VCERM-X5R805

C1213CRITICAL

22UF

805CERM-X5R

20%


6.3V

C121222UF

CERM-X5R

20%

805

6.3V


CRITICALC1211CRITICAL

22UF

805CERM-X5R6.3V20%


NO STUFF NO STUFFCRITICAL

22UF

805CERM-X5R6.3V20%

C1219

Place inside socket cavity on secondary side.Place inside socket cavity on secondary side.

22UF6.3V

805

20%

CERM-X5R

C1200CRITICAL

NO STUFF

20%

CERM-X5R

C121022UF

CRITICAL

805

6.3V


C126120%10VCERM402

0.1UF

CRITICAL

805CERM-X5R6.3V20%22UF


C1205

NO STUFF

805CERM-X5R

CRITICALC120920%6.3V

22UF


C1215

805

22UF6.3V20%

CERM-X5R


CRITICAL

20%22UF

805CERM-X5R6.3V

C1217CRITICAL


C126220%10VCERM402

0.1UFC126320%10VCERM402

0.1UFC126420%10VCERM402

0.1UFC126520%10VCERM402

0.1UFC126620%10VCERM402

0.1UF

CRITICAL

22UF

805

6.3V20%

C1218

CERM-X5R


C1251BYPASS=U1000.B26::4 mm

10%16VCERM402

0.01UFC1250

20%6.3VX5R603

10uF

Place on secondary side.

D2T-SM

2.0V20%470UF-4MOHM

POLY-TANT

NO STUFFCRITICAL

C124020%


2.0VPOLY-TANTD2T-SM

470UF-4MOHM

CRITICALC1241

CRITICALC1242470UF-4MOHM


20%2.0VPOLY-TANTD2T-SM

2.0V20%

CRITICAL

470UF-4MOHM

POLY-TANT


C1243

D2T-SM

CPU DecouplingSYNC_DATE=02/16/2010SYNC_MASTER=T27_MLB

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

12 OF 109

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2

1

32

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

3 2

1

3 2

1

3 2

1

3 2

1

8 10 11 13

8 11

8 11

IN

BI

BI

BI

BI

OUT

IN

BI

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

NC

IN

IN

IN




36

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Apple Inc.

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8 7 5 4 2 1

Direction of XDP modulePlease avoid any obstructionsON ODD-NUMBERED SIDE OF J1300

OBSFN_C0

OBSFN_C1

OBSDATA_C0

OBSDATA_C1

OBSDATA_C2

OBSDATA_C3

OBSFN_D0

OBSFN_D1

OBSDATA_D0

OBSDATA_D1

OBSDATA_D2

OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

TDO

TRSTn

TDI

TMS

XDP_PRESENT#

TCK0

TCK1

SCL

SDA

HOOK2

HOOK3

VCC_OBS_AB

HOOK1

PWRGD/HOOK0

OBSDATA_B3

OBSDATA_B2

OBSDATA_B1

OBSDATA_B0

OBSFN_B1

OBSFN_B0

OBSDATA_A3

OBSDATA_A2

OBSDATA_A1

OBSDATA_A0

OBSFN_A1

OBSFN_A0

MCP89-SPECIFIC PINOUT

Mini-XDP Connector

USE WITH 920-0782 ADAPTER FLEX TO SUPPORT CPU, MCP DEBUGGING.

NOTE: This is not the standard XDP pinout.

518S0774

10 14 69

1/16W5%

402MF-LF

1K

XDP

R1399

19 38 72

19 38 72

1/16W1%

402MF-LF

54.9

XDP

R1315

16V10%

402X5R

0.1uF

XDPC1300

16V10%

402X5R

0.1uF

XDPC1301

10 69

10 69

10 69

10 14 69

PLACE_NEAR=U1000.C1:5 MM1/16W5%

402MF-LF

1K

XDP

R1303

10 69

10 69

10 69

10 69

19

19

19

19

14 69

14 69

10 69

10 69

10 69

10 25

19

10 69

19

XDP_CONCRITICAL

F-ST-SM-HFDF40C-60DS-0.4V

J1300


eXtended Debug Port(MiniXDP)SYNC_DATE=(02/25/2009)

TP_XDP_OBSDATA_C2TP_XDP_OBSDATA_C3

PM_LATRIGGER_LJTAG_MCP_TCK

=PP1V05_S0_CPU

XDP_OBS20

XDP_BPM_L<1>

XDP_CPURST_L

XDP_TDO

XDP_TDIXDP_TMS

XDP_BPM_L<5>

TP_XDP_OBSDATA_B0

TP_XDP_OBSDATA_B2

XDP_TCK

SMBUS_MCP_0_CLK

XDP_BPM_L<4>

XDP_BPM_L<2>XDP_BPM_L<3>

XDP_BPM_L<0>

TP_XDP_OBSFN_B1TP_XDP_OBSFN_B0

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B3

XDP_PWRGD

SMBUS_MCP_0_DATA

TP_XDP_OBSDATA_D3

TP_XDP_OBSDATA_D0

JTAG_MCP_TMSJTAG_MCP_TDI

TP_XDP_OBSDATA_C0TP_XDP_OBSDATA_C1

JTAG_MCP_TRST_LJTAG_MCP_TDO

XDP_TRST_L

XDP_DBRESET_L

CPU_PWRGD

FSB_CPURST_L

FSB_CLK_ITP_P

TP_XDP_OBSDATA_D1

TP_XDP_OBSDATA_D2

FSB_CLK_ITP_N

=PP3V3_S0_XDP

13 OF 109

C.0.0

051-8561

13 OF 76

1 2

1

2

2

1

2

1

1 2

3

1

7

5

11

9

13

17

15

23

19

21

25

27

29

33

31

35

39

37

41

43

45

47

49

51

53

59

57

55

38

40

36

32

34

30

28

26

24

22

16

18

20

10

14

12

6

8

2

4

56

58

60

54

52

50

48

46

44

42

8 10 11 12

69

8

IN

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

CPU_A18*

CPU_D35*

CPU_D37*

CPU_A10*

CPU_A9*

CPU_D48*

CPU_A16*

CPU_D33*

CPU_RS2*

CPU_RS1*

CPU_RS0*

CPU_BSEL2

CPU_BSEL1

CPU_THERMTRIP*

CPU_PECI

CPU_PROCHOT*

CPU_DBSY*

CPU_ADSTB1*

CPU_REQ1*

CPU_REQ4*

CPU_BR0*

CPU_BNR*

CPU_ADS*

CPU_REQ2*

CPU_REQ3*

CPU_REQ0*

CPU_ADSTB0*

CPU_A31*

CPU_A32*

CPU_A30*

CPU_A28*

CPU_A26*

CPU_A27*

CPU_A23*

CPU_A24*

CPU_A25*

CPU_A21*

CPU_A22*

CPU_A19*

CPU_A20*

CPU_A13*

CPU_A14*

CPU_A12*

CPU_A11*

CPU_A8*

CPU_A5*

CPU_A6*

CPU_A7*

CPU_A3*

CPU_A4*

CPU_DSTBN0*

CPU_DBI0*

CPU_DSTBP1*

CPU_DSTBN1*

CPU_DBI1*

CPU_DSTBP2*

CPU_DSTBN2*

CPU_DBI2*

CPU_DSTBP3*

CPU_DSTBN3*

CPU_DBI3*

CPU_BSEL0

CPU_COMP_GND

BCLK_VML_COMP_VDD

CPU_COMP_VCC

BCLK_VML_COMP_GND

CPU_D1*

CPU_D2*

CPU_D3*

CPU_D4*

CPU_D5*

CPU_D6*

CPU_D9*

CPU_D11*

CPU_D12*

CPU_D13*

CPU_D14*

CPU_D15*

CPU_D16*

CPU_D17*

CPU_D18*

CPU_D19*

CPU_D20*

CPU_D21*

CPU_D22*

CPU_D23*

CPU_D24*

CPU_D25*

CPU_D26*

CPU_D27*

CPU_D28*

CPU_D29*

CPU_D30*

CPU_D31*

CPU_D32*

CPU_D34*

CPU_D36*

CPU_D38*

CPU_D39*

CPU_D40*

CPU_D41*

CPU_D42*

CPU_D45*

CPU_D46*

CPU_D47*

CPU_D49*

CPU_D50*

CPU_D51*

CPU_D52*

CPU_D53*

CPU_D54*

CPU_D55*

CPU_D56*

CPU_D57*

CPU_D58*

CPU_D59*

CPU_D60*

CPU_D61*

CPU_D62*

CPU_D63*

CPU_A20M*

CPU_IGNNE*

CPU_INIT*

CPU_INTR

CPU_NMI

CPU_SMI*

CPU_PWRGD

CPU_RESET*

CPU_DPRSLPVR

CPU_SLP*

CPU_D10*

CPU_D8*

CPU_D7*

CPU_A33*

CPU_A34*

CPU_A35*

CPU_D44*

CPU_D43*

CPU_DSTBP0*

CPU_TRDY*

CPU_LOCK*

CPU_HIT*

CPU_DRDY*

CPU_HITM*

CPU_DPRSTP*

CPU_D0*

CPU_DPSLP*

CPU_DPWR*

CPU_STPCLK*

CPU_A15*

CPU_A17*

CPU_A29*

CPU_BPRI*

CPU_DEFER*

CPU_FERR*BCLK_OUT_CPU_P

BCLK_OUT_CPU_N

BCLK_OUT_ITP_P

BCLK_OUT_ITP_N

BCLK_OUT_NB_N

BCLK_IN_N

BCLK_IN_P

BCLK_OUT_NB_P

(1 OF 11)

FSB

OUT

IN

IN

IN

IN

IN

IN

IN




36

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Loop-back clock for delay matching.

9

9

9

10 69

10 13 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

7 10 69

10 69

10 69

10 69

10 69

10 69

10 69

13 69

13 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 13 69

10 69

10 69

10 69

10 69

10 58 69

9

10 36 69

10 36 69

7 10 69

7 10 69

49.9

402MF-LF1/16W1%

R1436

1/16W1%

402MF-LF

49.9R1431

49.9

MF-LF402

1%1/16W

R143049.91/16W1%

MF-LF402

R1435

1/16W

402MF-LF

625%

R1415

1/16W

402MF-LF

54.91%

R1410

5%

MF-LF402

NO STUFF

1/16W

150R1440

OMIT

MCP89M-A01FBGA

U1400

58 69

7 10 69

7 10 69

10 69

10 69

10 69

10 69

7 10 69


MCP CPU Interface

=PP1V05_S0_MCP_FSB

=PP1V05_S0_MCP_FSB

FSB_CLK_MCP_PFSB_CLK_MCP_N

FSB_CLK_ITP_NFSB_CLK_ITP_P

FSB_CLK_CPU_NFSB_CLK_CPU_P

CPU_FERR_L

FSB_DEFER_LFSB_BPRI_L

FSB_A_L<29>

FSB_A_L<17>

FSB_A_L<15>

CPU_STPCLK_LFSB_DPWR_LCPU_DPSLP_L

FSB_D_L<0>

CPU_DPRSTP_L

FSB_HITM_L

FSB_DRDY_LFSB_HIT_L

FSB_LOCK_LFSB_TRDY_L

FSB_DSTB_L_P<0>




FSB_D_L<10>

FSB_CPUSLP_LPM_DPRSLPVRFSB_CPURST_LCPU_PWRGDCPU_SMI_LCPU_NMICPU_INTRCPU_INIT_LCPU_IGNNE_LCPU_A20M_L

FSB_D_L<63>FSB_D_L<62>FSB_D_L<61>FSB_D_L<60>FSB_D_L<59>FSB_D_L<58>FSB_D_L<57>FSB_D_L<56>FSB_D_L<55>FSB_D_L<54>FSB_D_L<53>FSB_D_L<52>FSB_D_L<51>FSB_D_L<50>FSB_D_L<49>

FSB_D_L<47>FSB_D_L<46>FSB_D_L<45>

FSB_D_L<42>FSB_D_L<41>FSB_D_L<40>FSB_D_L<39>FSB_D_L<38>

FSB_D_L<36>

FSB_D_L<34>

FSB_D_L<32>FSB_D_L<31>FSB_D_L<30>FSB_D_L<29>FSB_D_L<28>FSB_D_L<27>FSB_D_L<26>FSB_D_L<25>FSB_D_L<24>FSB_D_L<23>FSB_D_L<22>FSB_D_L<21>FSB_D_L<20>FSB_D_L<19>FSB_D_L<18>FSB_D_L<17>FSB_D_L<16>FSB_D_L<15>FSB_D_L<14>FSB_D_L<13>FSB_D_L<12>FSB_D_L<11>

FSB_D_L<9>

FSB_D_L<6>FSB_D_L<5>FSB_D_L<4>FSB_D_L<3>FSB_D_L<2>FSB_D_L<1>

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC

MCP_BCLK_VML_COMP_VDD

MCP_CPU_COMP_GND

=MCP_BSEL<0>

FSB_DINV_L<3>FSB_DSTB_L_N<3>FSB_DSTB_L_P<3>



FSB_DINV_L<0>FSB_DSTB_L_N<0>



FSB_A_L<8>







FSB_A_L<28>

FSB_A_L<30>


FSB_ADSTB_L<0>

FSB_REQ_L<0>

FSB_REQ_L<3>FSB_REQ_L<2>

FSB_ADS_LFSB_BNR_LFSB_BREQ0_L

FSB_REQ_L<4>

FSB_REQ_L<1>

FSB_ADSTB_L<1>

FSB_DBSY_L

CPU_PROCHOT_LCPU_PECI_MCP

PM_THRMTRIP_L

=MCP_BSEL<1>=MCP_BSEL<2>

FSB_RS_L<0>FSB_RS_L<1>FSB_RS_L<2>

FSB_D_L<33>

FSB_A_L<16>

FSB_D_L<48>


FSB_D_L<37>

FSB_D_L<35>

FSB_A_L<18>

14 OF 109

C.0.0

051-8561

14 OF 76

1

2

1

2

1

2

1

2

1

2

1

2

1

2

AB35

L31

P32

Y38

T37

C37

Y35

G34

AC31

AC33

AB29

B34

C34

W33

AH34

U28

AE29

AB34

T36

T35

AE30

AE32

AE31

U37

T38

U36

W36

AC35

AE37

AC37

AE36

AB37

AC34

AC38

AB36

AB38

AC36

AF36

Y34

AE38

U33

W34

Y36

W35

W38

U35

T34

W37

U38

U34

K35

L37

T31

T30

P28

K33

K32

N35

C36

D36

A35

A34

AH35

AH37

AH36

AH38

N36

P36

L36

N34

L35

P37

L34

K36

K38

N37

H37

L38

N28

U30

N29

P34

T29

T32

U32

T33

P31

P30

N30

P33

N31

T28

P35

P29

H33

L30

L33

N32

N33

H35

K31

H34

G33

H32

G35

D37

H38

G38

G37

G36

B35

E35

B36

E36

C35

D34

E38

D38

E34

E37

W30

AB30

AB28

W31

AC30

AC28

Y32

AE28

G1

Y33

K37

H36

P38

AE35

AE33

AE34

L32

K30

K34

AC29

AC32

W32

U29

AB31

W29

N38

AB33

U31

Y29

Y37

AF38

AF37

Y31

Y30

AB32AF33

AF32

AF34

AF35

AF28

AF31

AF30

AF29

8 14 20 23

8 14 20 23

69

69

69

69

69

69

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT OUT

OUT

OUT

MDQS0_7_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_5_N

MDQS0_5_P

MDQS0_4_P

MDQS0_4_N

MDQS0_3_P

MDQS0_2_P

MDQS0_2_N

MDQS0_1_P

MDQS0_1_N

MDQS0_0_P

MDQS0_0_N

MRAS0*

MCAS0*

MWE0*

MBA0_2

MBA0_1

MBA0_0

MA0_14

MA0_15

MA0_13

MA0_12

MA0_11

MA0_9

MA0_10

MA0_8

MA0_7

MA0_6

MA0_3

MA0_4

MA0_1

MA0_2

MA0_0

+VIO_M2CLK_DLL_1

+VIO_M2CLK_DLL_2

+VIO_PLL_MEM_2

+VIO_PLL_MEM_1

+VIO_PLL_FSB_1

+VIO_PLL_FSB_2

MCLK0A_1_P

MCLK0A_1_N

MCLK0A_0_P

MCLK0A_0_N

MCS0A_1*

MCS0A_0*

MODT0A_0

MODT0A_1

MCKE0A_1

MCKE0A_0

MDQ0_63

MDQ0_62

MDQ0_61

MDQ0_58

MDQ0_59

MDQ0_55

MDQ0_57

MDQ0_56

MDQ0_53

MDQ0_54

MDQ0_50

MDQ0_52

MDQ0_51

MDQ0_48

MDQ0_49

MDQ0_45

MDQ0_46

MDQ0_47

MDQ0_43

MDQ0_44

MDQ0_41

MDQ0_40

MDQ0_39

MDQ0_37

MDQ0_38

MDQ0_36

MDQ0_35

MDQ0_34

MDQ0_33

MDQ0_32

MDQ0_31

MDQ0_30

MDQ0_29

MDQ0_27

MDQ0_28

MDQ0_26

MDQ0_25

MDQ0_24

MDQ0_22

MDQ0_23

MDQ0_19

MDQ0_21

MDQ0_20

MDQ0_17

MDQ0_18

MDQ0_16

MDQ0_14

MDQ0_15

MDQ0_12

MDQ0_13

MDQ0_11

MDQ0_10

MDQ0_9

MDQ0_8

MDQ0_7

MDQ0_5

MDQ0_6

MDQ0_4

MDQ0_2

MDQ0_3

MDQ0_1

MDQ0_0

MDQM0_7

MDQM0_6

MDQM0_5

MDQM0_4

MDQM0_2

MDQM0_3

MDQM0_0

MDQM0_1

MDQ0_42

MA0_5

+VIO_PLL_CPU_4

+VIO_PLL_CPU_3

+VIO_PLL_CPU_2

+VIO_PLL_CPU_1

MDQS0_3_N

MDQ0_60

MEMORY PARTITION 0

(2 OF 11)

MDQ1_51

MDQ1_13

MDQ1_25

MDQ1_39

MEM_COMP_VDD

MEM_COMP_GND

MDQM1_1

MDQ1_44

MDQ1_43

MDQ1_42

MDQ1_41

MDQ1_40

MDQ1_38

MDQ1_10

MDQ1_16

MDQ1_14

MDQ1_3

MDQ1_2

MDQ1_1

MDQM1_2

MDQM1_3

MDQM1_4

MDQM1_5

MDQM1_6

MDQM1_7

MDQS1_6_N

MDQS1_7_N

MDQS1_7_P

MDQ1_0

MDQ1_4

MDQ1_5

MDQ1_6

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_11

MDQ1_12

MDQ1_15

MDQ1_17

MDQ1_18

MDQ1_21

MDQ1_22

MDQ1_23

MDQ1_24

MDQ1_26

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_30

MDQ1_31

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_35

MDQ1_36

MDQ1_37

MDQ1_46

MDQ1_47

MDQ1_48

MDQ1_52

MDQ1_53

MDQ1_54

MDQ1_56

MDQ1_57

MDQ1_58

MDQ1_59

MDQ1_60

MDQ1_61

MDQ1_62

MDQ1_49

MDQS1_6_P

MDQ1_63

MDQ1_50

MDQM1_0

MDQ1_45

MDQ1_55

MDQS1_5_P

MDQS1_5_N

MDQS1_4_P

MDQS1_4_N

MDQS1_3_P

MDQS1_3_N

MDQS1_2_P

MDQS1_2_N

MDQS1_1_P

MDQS1_1_N

MDQS1_0_N

MDQS1_0_P

MRAS1*

MCAS1*

MWE1*

MBA1_2

MBA1_1

MBA1_0

MA1_15

MA1_14

MA1_13

MA1_12

MA1_11

MA1_10

MA1_9

MA1_8

MA1_7

MA1_6

MA1_4

MA1_5

MA1_3

MRESET0*

MCLK1A_1_P

MCLK1A_1_N

MCLK1A_0_P

MCLK1A_0_N

MCS1A_1*

MCS1A_0*

MODT1A_1

MODT1A_0

MCKE1A_1

MCKE1A_0

MA1_1

MA1_0

MA1_2

MDQ1_19

MDQ1_20

MEMORY PARTITION 1

(3 OF 11)

OUT

OUT

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

20 mA

25 mA

25 mA

70 mA

550 mA

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

26 70

21 26 70

21 26 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

26 70 27 70

21 27 70

21 27 70

OMIT

FBGAMCP89M-A01U1400

OMIT

MCP89M-A01FBGA

U1400

27 70

27 70

27 70

27 70

26 27

5%

402

1/16WMF-LF

1KR1520

402

1%1/16W

40.2

MF-LF

R1511

MF-LF402

1/16W

40.21%

R1510


MCP Memory Interface

MEM_A_A<8>

=PP1V5R1V35_SW_MCP_MEM

MEM_A_A<3>

MEM_B_DQ<15>

MEM_A_A<9>

MEM_A_A<11>

MEM_A_A<0>

=PP1V5R1V35_S3_MCP_MEM

MEM_A_DQS_N<5>MEM_A_DQS_P<4>

MEM_A_DQS_P<2>MEM_A_DQS_N<2>

MEM_A_DQ<62>

MEM_A_DQ<59>MEM_A_DQ<60>MEM_A_DQ<61>

MEM_A_DQ<58>MEM_A_DQ<57>




MEM_A_DQ<48>MEM_A_DQ<47>MEM_A_DQ<46>MEM_A_DQ<45>MEM_A_DQ<44>




MEM_A_DQ<35>MEM_A_DQ<34>MEM_A_DQ<33>MEM_A_DQ<32>



MEM_A_DQ<28>


MEM_A_DQ<23>





MEM_A_DQ<15>


MEM_A_DQ<8>




MEM_A_DQ<0>

MEM_A_DM<7>MEM_A_DM<6>

MEM_A_DM<4>MEM_A_DM<5>

MEM_A_DM<1>MEM_A_DM<2>MEM_A_DM<3>

MEM_A_DM<0>

MEM_A_DQ<63>


MEM_A_DQ<31>

MEM_A_CKE<1>MEM_A_CKE<0>

MEM_A_ODT<1>MEM_A_ODT<0>

MEM_A_CS_L<0>MEM_A_CS_L<1>

MEM_A_CLK_N<0>MEM_A_CLK_P<0>

MEM_A_CLK_N<1>MEM_A_CLK_P<1>

MEM_A_A<1>MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<12>


MEM_A_A<13>

MEM_A_BA<0>

MEM_A_BA<2>MEM_A_BA<1>

MEM_A_CAS_LMEM_A_RAS_L



MEM_A_DQS_N<3>

MEM_A_DQS_N<4>MEM_A_DQS_P<3>

MEM_A_DQS_P<5>

MEM_A_DQS_P<6>MEM_A_DQS_N<7>MEM_A_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQ<49>

MEM_B_DQ<63>MEM_B_DQ<62>MEM_B_DQ<61>MEM_B_DQ<60>MEM_B_DQ<59>MEM_B_DQ<58>MEM_B_DQ<57>MEM_B_DQ<56>MEM_B_DQ<55>MEM_B_DQ<54>MEM_B_DQ<53>MEM_B_DQ<52>

MEM_B_DQ<50>

MEM_B_DQ<48>MEM_B_DQ<47>MEM_B_DQ<46>

MEM_B_DQ<37>MEM_B_DQ<36>MEM_B_DQ<35>MEM_B_DQ<34>MEM_B_DQ<33>MEM_B_DQ<32>MEM_B_DQ<31>MEM_B_DQ<30>

MEM_B_DQ<28>

MEM_B_DQ<26>

MEM_B_DQ<24>MEM_B_DQ<23>MEM_B_DQ<22>MEM_B_DQ<21>

MEM_B_DQ<18>MEM_B_DQ<17>


MEM_B_DQ<8>MEM_B_DQ<7>MEM_B_DQ<6>MEM_B_DQ<5>MEM_B_DQ<4>

MEM_B_DQ<0>

MEM_B_DQS_P<7>MEM_B_DQS_N<7>

MEM_B_DQS_N<6>MEM_B_DQS_P<5>MEM_B_DQS_N<5>MEM_B_DQS_P<4>MEM_B_DQS_N<4>MEM_B_DQS_P<3>MEM_B_DQS_N<3>MEM_B_DQS_P<2>MEM_B_DQS_N<2>MEM_B_DQS_P<1>MEM_B_DQS_N<1>MEM_B_DQS_P<0>MEM_B_DQS_N<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_ODT<1>MEM_B_ODT<0>

MEM_B_CKE<1>MEM_B_CKE<0>

MEM_B_DM<7>MEM_B_DM<6>MEM_B_DM<5>MEM_B_DM<4>MEM_B_DM<3>MEM_B_DM<2>

MEM_B_DQ<1>MEM_B_DQ<2>MEM_B_DQ<3>

MEM_B_DQ<14>

MEM_B_DQ<16>


MEM_B_DQ<10>

MEM_B_A<15>MEM_B_A<14>MEM_B_A<13>MEM_B_A<12>MEM_B_A<11>MEM_B_A<10>MEM_B_A<9>MEM_B_A<8>MEM_B_A<7>MEM_B_A<6>MEM_B_A<5>MEM_B_A<4>MEM_B_A<3>MEM_B_A<2>MEM_B_A<1>MEM_B_A<0>

MEM_B_RAS_LMEM_B_CAS_LMEM_B_WE_L

MEM_B_BA<2>MEM_B_BA<1>MEM_B_BA<0>

MEM_B_DQ<38>

MEM_B_DQ<40>MEM_B_DQ<41>MEM_B_DQ<42>MEM_B_DQ<43>MEM_B_DQ<44>MEM_B_DQ<45>

MEM_B_DM<0>MEM_B_DM<1>

MCP_MEM_COMP_GNDMCP_MEM_COMP_VDD

MEM_B_DQ<39>

MEM_B_DQ<25>

MEM_B_CS_L<1>

MEM_B_DQ<13>

MEM_B_DQ<51>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>MEM_B_CLK_P<1>

MEM_RESET_L

MEM_A_WE_L

MEM_A_DQ<39>

MEM_B_DQ<27>MEM_A_A<6>MEM_A_A<5>

MEM_B_DQ<29>

MEM_B_DQ<9>


PP1V05_S0_MCP_PLL_FSBMEM

MEM_A_A<7>

MEM_A_DQS_N<6>

15 OF 109

C.0.0

051-8561

15 OF 76

AN7

AM10

AN10

AM7

AM13

AN13

AL16

AK16

AH28

AM29

AN29

AP34

AP35

AH31

AG31

AN19

AL19

AL20

AL25

AN20

AM19

AK25

AK26

AJ20

AJ26

AH25

AH26

AM20

AN23

AJ25

AM22

AL23

AN22

AK23

AK22

AL22

AF24

AG25

AG26

AF25

AF26

AG28

AH23

AJ23

AJ22

AH22

AH19

AK20

AK19

AH20

AL26

AN25

AP5

AP7

AR8

AR5

AR4

AK11

AM8

AN8

AH13

AL11

AK10

AH14

AL10

AJ13

AN11

AJ16

AK14

AK13

AJ14

AH16

AM14

AN14

AK17

AN17

AL17

AJ19

AH17

AJ17

AM16

AM17

AN26

AH29

AK29

AM25

AL29

AM26

AL28

AK28

AP29

AM28

AP28

AL31

AN32

AN31

AN28

AM31

AM32

AR34

AL35

AL33

AP32

AP33

AM35

AL32

AJ35

AH32

AJ31

AH33

AL34

AJ34

AJ33

AJ32

AR7

AM11

AL14

AN16

AP31

AJ29

AJ30

AM34

AL13

AM23

AF27

AE26

AD26

AC26

AJ28

AP8

AV5

AR37

AV28

AV14

AG22

AG23

AT37

AR14

AR11

AP11

AT11

AP13

AU14

AU35

AT32

AT35

AP37

AP36

AJ38

AV32

AR28

AT14

AV10

AU7

AT2

AV8

AR1

AR2

AJ37

AL36

AJ36

AM37

AM36

AR38

AR36

AV34

AP38

AV35

AU32

AR31

AT34

AR32

AT31

AV29

AV26

AV25

AT29

AU29

AT26

AU26

AR16

AP16

AT13

AP14

AP17

AR17

AU10

AT10

AT8

AR10

AU8

AT7

AT4

AU3

AP2

AP3

AU4

AV4

AR3

AP10

AV7

AP1

AU5

AM38

AR13

AT5

AU11

AV11

AU13

AV13

AT28

AU28

AU31

AV31

AU36

AT36

AL37

AL38

AR19

AU17

AT17

AR25

AT19

AR20

AP26

AR26

AV16

AP25

AT23

AP20

AU23

AV22

AV23

AT22

AP23

AU22

AR23

AP4

AU20

AV20

AU19

AV19

AU16

AP19

AT16

AV17

AU25

AT25

AR22

AT20

AP22

AR29

AU34

1

2

1

2

1

2

20 21 23

8

70

70

8 23

23

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

PE0_REFCLK_P

PE0_REFCLK_N

PE1_REFCLK_P

PE2_REFCLK_P

PE1_REFCLK_N

PE3_REFCLK_P

PE2_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE5_REFCLK_P

PE4_REFCLK_N

PE5_REFCLK_N

PE0_TX0_P

PE0_TX0_N

PE0_TX1_P

PE0_TX1_N

PE0_TX2_P

PE0_TX3_P

PE0_TX2_N

PE0_TX4_P

PE0_TX3_N

PE0_TX5_P

PE0_TX4_N

PE0_TX5_N

PE1_TX0_N

PE1_TX0_P

PE1_TX1_P

PE1_TX1_N

PEX_RST*

PEX0_TERM_P

PEA_CLKREQ*/GPIO_49

PEB_CLKREQ*/GPIO_50

PEC_CLKREQ*/GPIO_51

PEE_CLKREQ*/GPIO_53

PED_CLKREQ*/GPIO_52

PEF_CLKREQ*/GPIO_54

PE_WAKE*

PE0_RX0_P

PE0_RX0_N

PE0_RX1_P

PE0_RX1_N

PE0_RX3_P

PE0_RX4_P

PE0_RX3_N

PE0_RX4_N

PE0_RX5_P

PE0_RX5_N

PE1_RX0_P

PE1_RX0_N

PE1_RX1_N

PE1_RX1_P

+3.3V_PLL_HVDD_1

+3.3V_PLL_HVDD_2

+VIO_PLL_PE

+VIO_PLL_XREF_XS_1

+VIO_PLL_XREF_XS_2

+VIO_PLL_SATA_1

+VIO_PLL_XREF_XS_3

+VIO_PLL_SATA_2

+VIO_PLL_H

PE0_RX2_N

PE0_RX2_P

PCI EXPRESS

(4 OF 11)

OUT

IN

OUT

OUT

IN

IN

IN

OUT

OUT

IN

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

PE1 ports are Gen1-only. 2 RCs: x1, x1PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1

+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND

If PE0[3:0] are not used,+VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND

If PE0[4:5] and PE1[0:1] are not used,

(IPU-S5)

50 mA

100 mA

120 mA

25 mA

80 mA

325 mA

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

(IPU)

(IPD)

PLACE_NEAR=U1400.U2:12.7 mm

402MF-LF1/16W

1%2.49K

R1610

9 71

9 71

9 71

9 71

7 30

9

30

9

9

9

9

9

9

9

9

9 71

9 71

25

9 71

9 71

9 71

9 71

9 71

9 71

9

9

9

9

9

9

9

9

FBGAMCP89M-A01

OMIT

U1400

9

9

9 71

9 71

9

9 71

9 71

9 71

9 71

9

9 71

9 71

1/16WMF-LF402

5%10K

NO STUFFR1600

MCP PCIe InterfacesSYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010

PCIE_ENET_R2D_C_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_AP_P

FW_PWR_ENPCIE_CLK100M_FW_N

=PEG_R2D_C_P<3>

=PEG_R2D_C_N<0>

ENET_CLKREQ_L

=PEG_R2D_C_N<1>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<2>

PP1V05_S0_MCP_PLL_PEXSATA

PCIE_AP_D2R_N

TP_PCIE_CLK100M_PE4P

PCIE_AP_D2R_P

FW_PME_L

PCIE_FW_R2D_C_PPCIE_FW_D2R_N

AP_CLKREQ_LPEG_CLK100M_NPEG_CLK100M_P

TP_PCIE_PE4_R2D_CN

PCIE_ENET_R2D_C_P

TP_PCIE_PE4_R2D_CP

PCIE_AP_R2D_C_N

PEG_CLKREQ_L

=PEG_D2R_P<0>=PEG_D2R_N<0>

=PEG_D2R_P<1>=PEG_D2R_N<1>

=PEG_D2R_P<2>

TP_PCIE_PE4_D2RN

PCIE_ENET_D2R_P

PCIE_CLK100M_FW_P

TP_PCIE_CLK100M_PE5P

=PEG_R2D_C_P<2>

PCIE_AP_R2D_C_P

MCP_PEX0_TERMP

FW_CLKREQ_L

TP_PCIE_CLK100M_PE4N

=PEG_R2D_C_P<0>

PCIE_WAKE_L

PCIE_FW_D2R_P

PCIE_ENET_D2R_N

PP3V3_S0_MCP_PLL_HVDD

=PEG_R2D_C_P<1>

TP_PCIE_CLK100M_PE5N

PCIE_CLK100M_AP_N

PCIE_RESET_L

PCIE_CLK100M_ENET_N

PCIE_FW_R2D_C_N

TP_PCIE_PE4_D2RP

=PEG_D2R_N<3>=PEG_D2R_P<3>

=PEG_D2R_N<2>

16 OF 109

C.0.0

051-8561

16 OF 76

1

2

Y1

W1

W3

U4

W2

U7

U5

U9

U6

W10

U8

W11

AC3

AC2

AB2

AB3

AC6

AC8

AC7

AB4

AC9

Y5

AB5

Y4

Y6

Y7

Y9

Y8

U1

U2

W4

W5

W7

W6

W8

W9

U3

AC1

AB1

AC5

AC4

AB7

AB9

AB6

AB8

Y2

Y3

AB11

AB10

Y11

Y10

V11

V13

AH10

AG11

AF12

AH8

AF13

AH9

AH11

AC11

AC10

1

2

23

71

23

OUT

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

FLAT PANEL

RGB

(5 OF 11)

+3.3V_RGBDAC

DDC_DATA0/GPIO_39

DDC_CLK0/GPIO_38

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_HSYNC

RGB_DAC_BLUE

RGB_DAC_VSYNC

RGB_DAC_RSET

RGB_DAC_VREF

IFPA_TXC_P

IFPA_TXD0_P

IFPA_TXC_N

IFPA_TXD0_N

DP0_3_P/TMDS0_TXC_P

DP0_3_N/TMDS0_TXC_N

DP0_2_N/TMDS0_TX0_N

DDC_CLK3/DP_AUX_CH1_P

DDC_DATA3/DP_AUX_CH1_N

DP0_1_P/TMDS0_TX1_P

DP0_1_N/TMDS0_TX1_N

DP0_0_P/TMDS0_TX2_P

DP0_0_N/TMDS0_TX2_N

DP1_3_P/TMDS0B_TXC_P

DP1_3_N/TMDS0B_TXC_N

DP1_2_P/TMDS0_TX3_P

DP1_2_N/TMDS0_TX3_N

DP1_1_P/TMDS0_TX4_P

DP1_1_N/TMDS0_TX4_N

DP1_0_P/TMDS0_TX5_P

DP1_0_N/TMDS0_TX5_N

HPLUG_DET0/GPIO_20

HPLUG_DET1/GPIO_21

HPLUG_DET2/GPIO_22

DDC_CLK2/DP_AUX_CH0_P

DDC_DATA2/DP_AUX_CH0_N

+3.3V_PLL_DP0_1

+VIO_PLL_IFPAB_1

+3.3V_PLL_USB_2

+VIO_PLL_IFPAB_2

+VIO_PLL_SPPLL0_1

+VIO_PLL_CORE_LEG

+VIO_PLL_SPPLL0_2

+VIO_PLL_NV_1

+VIO_PLL_V

+VDD_IFPA

+VIO_PLL_NV_2

+VDD_IFPB

+VIO_DP0_1

+VIO_DP0_2

+VIO_DP0_3

IFPA_TXD1_P

IFPA_TXD1_N

IFPA_TXD2_P

IFPA_TXD2_N

IFPA_TXD3_P

IFPA_TXD3_N

IFPB_TXC_P

IFPB_TXC_N

IFPB_TXD4_P

IFPB_TXD4_N

IFPB_TXD5_P

IFPB_TXD5_N

IFPB_TXD6_P

IFPB_TXD6_N

IFPB_TXD7_P

IFPB_TXD7_N

DDC_CLK1/GPIO_40

DDC_DATA1/GPIO_41

TMDS0_RSET

TMDS0_VPROBE

IFPAB_RSET

IFPAB_VPROBE

+3.3V_PLL_USB_1

+3.3V_PLL_DP0_2

DP0_2_P/TMDS0_TX0_P

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57 OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: TMDS/HDMI not supported on IFPA/B for MCP89 A01.

140 mA

LVDS: Power +VDD_IFPx at 1.8V

=MCP_IFPAB_DDC_DATA

=MCP_IFPA_TXC_P/N

=MCP_IFPAB_DDC_CLK=MCP_IFPB_TXD_P/N<3>=MCP_IFPB_TXD_P/N<2>=MCP_IFPB_TXD_P/N<1>=MCP_IFPB_TXD_P/N<0>=MCP_IFPB_TXC_P/N=MCP_IFPA_TXD_P/N<3>=MCP_IFPA_TXD_P/N<2>=MCP_IFPA_TXD_P/N<1>=MCP_IFPA_TXD_P/N<0>

(UNUSED)

(UNUSED)(UNUSED)

MCP Signal TMDS/HDMI

TMDS_IG_DDC_CLKTMDS_IG_DDC_DATA

TMDS_IG_TXD_P/N<5>TMDS_IG_TXD_P/N<4>TMDS_IG_TXD_P/N<3>

TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<2>TMDS_IG_TXD_P/N<1>TMDS_IG_TXD_P/N<0>

Interface Mode

LVDS_IG_A_CLK_P/NLVDS_IG_A_DATA_P/N<0>LVDS_IG_A_DATA_P/N<1>LVDS_IG_A_DATA_P/N<2>LVDS_IG_A_DATA_P/N<3>LVDS_IG_B_CLK_P/NLVDS_IG_B_DATA_P/N<0>LVDS_IG_B_DATA_P/N<1>LVDS_IG_B_DATA_P/N<2>LVDS_IG_B_DATA_P/N<3>

LVDS_IG_DDC_DATALVDS_IG_DDC_CLK

LVDS

NOTE: No Composite/S-Video/Component Video support on MCP89

Okay to float all RGB_DAC signals.DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).

(GMUX_INT)

160 mA

Connect +3.3V_RGBDAC pin to GND.

RGB DAC Disable:

TMDS: Power +VDD_IFPx at 3.3V

180 mA

30 mA

210 mA

60 mA

40 mA60 mA

40 mA20 mA

180 mA

NOTE: 100K pull-downs required if HPLUG_DET0/HPLUG_DET1 are not used.


GPIO Pull-Ups

DDC Mode Pull-downsNOTE: DP_AUX_CH1 also requires pull-downs if used for dual-mode DisplayPort (DP++). If unused no pulls are necessary, if used for TMDS/HDMI only then only pull-ups are necessary.

160 mA

17

9

9

9 17

9

9

9

9

9

9

9

9

24 71

24 71

9

9

9

9

9

9

9

9

9

9

9

9

FBGAMCP89M-A01

OMIT

U1400

9

9

9

24 71

24 71

9

9

9

9

9

9

9

9

9 17

9

9

9

9

9

9

9

9

9

9

9

9

17 53

17

5% 1/16W 402MF-LF10KR178210K

MF-LF 4021/16W5%R1781

10KMF-LF 4021/16W5%

R1780

MF-LF 4021/16W5%100KR1711 MF-LF 4021/16W5%100KR1710

MCP GraphicsSYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010

=MCP_IFPA_TXC_N

TP_MCP_RGB_DAC_RSET

PP3V3_S0_MCP_PLL_DP_USB

DP_IG_AUX_CH1_N

DP_IG_ML1_N<0>

=MCP_IFPA_TXD_P<1>

TP_MCP_RGB_BLUE

=MCP_IFPA_TXD_N<1>

=MCP_IFPA_TXD_N<0>

=MCP_IFPB_TXD_N<2>=MCP_IFPB_TXD_P<2>=MCP_IFPB_TXD_N<1>

=MCP_IFPB_TXC_N

LCD_IG_PWR_EN

LCD_IG_BKLT_PWM


DP_IG_ML0_P<0>

DP_IG_ML0_P<1>

DP_IG_ML1_N<3>

=MCP_IFPAB_DDC_CLK

=MCP_IFPB_TXD_P<3>

MCP_TMDS0_VPROBE

DP_IG_ML1_N<1>

MCP_TMDS0_RSET

MCP_IFPAB_RSET

AUD_IP_PERIPHERAL_DETMIKEY_MIC_LOAD_DET

=MCP_IFPA_TXC_P

=MCP_IFPA_TXD_P<2>=MCP_IFPA_TXD_N<2>=MCP_IFPA_TXD_P<3>=MCP_IFPA_TXD_N<3>

=MCP_IFPB_TXC_P

=MCP_IFPB_TXD_P<1>=MCP_IFPB_TXD_N<0>

=MCP_IFPB_TXD_N<3>

LCD_IG_BKLT_EN

TP_MCP_RGB_GREEN

TP_MCP_RGB_HSYNC

TP_MCP_RGB_RED

DP_IG_ML1_P<3>

DP_IG_ML1_N<2>DP_IG_ML1_P<1>

DP_IG_ML1_P<2>

DP_IG_ML0_P<2>

DP_IG_ML0_N<1>

DP_IG_ML0_N<2>

DP_IG_ML0_N<3>

TP_MCP_RGB_DAC_VREF

=MCP_IFPB_TXD_P<0>

MCP_IFPAB_VPROBE

=MCP_IFPAB_DDC_DATA

DP_IG_HPD0


PP1V05_S0_MCP_PLL_CORE


PP3V3_S0_MCP_DAC

DP_IG_ML0_N<0>

DP_IG_ML1_P<0>

=MCP_IFPA_TXD_P<0>

TP_MCP_RGB_VSYNC

DP_IG_HPD1SATARDRVR_A_EN

DP_IG_AUX_CH1_P

DP_IG_AUX_CH0_PDP_IG_AUX_CH0_N

MIKEY_MIC_LOAD_DET

=PP3V3_S0_MCP_GPIO

AUD_IP_PERIPHERAL_DETSATARDRVR_A_EN

DP_IG_AUX_CH0_NDP_IG_AUX_CH0_P

DP_IG_ML0_P<3>

17 OF 109

C.0.0

051-8561

17 OF 76

B29

H25

F29

C31

B31

D31

A31

E31

C29

D29

K22

C22

L22

B22

D26

E26

F26

K25

K26

F25

G25

E25

D25

F28

G28

E28

D28

A28

A29

C28

B28

H26

J26

J25

L28

K28

M23

N23

M22

L24

N25

M25

L26

N24

M26

A22

L25

A23

A26

B26

C26

E22

D22

F22

G22

H22

J22

B23

C23

L23

K23

J23

H23

G23

F23

D23

E23

J28

G29

F31

H28

K20

L20

N21

N22

G26

C25

B25

A25

1 2

1 2

1 2

1 2

1 2

23

8 24

8 24

23

8 24

24

17

8 18 19

17 53

17

9 17

9 17

IN

BI

IN

IN

IN

IN

IN

IN

USB0_N

USB0_P

SATA_A0_RX_N

SATA_A1_TX_P

SATA_A1_TX_N

USB4_N

SATA_A0_RX_P

USB1_P

USB1_N

USB2_P

USB2_N

USB3_N

USB3_P

USB4_P

USB5_P

USB5_N

USB6_P

USB6_N

USB7_P

USB7_N

USB8_N

USB9_N

USB9_P

USB10_N

USB10_P

USB_OC3*/GPIO_28_MGPIO_1

USB_RBIAS_GND

RGMII_VREF

RGMII_TXD1

RGMII_TXD0

RGMII_TXD3

RGMII_TXD2

RGMII_TXCLK

RGMII_TXCTL

RGMII_MDC

RGMII_MDIO

BUF_25MHZ

RGMII_RESET*

SATA_A0_TX_P

SATA_A0_TX_N

SATA_A1_RX_P

SATA_A1_RX_N

SATA_B0_TX_P

SATA_B0_TX_N

SATA_B0_RX_N

SATA_B0_RX_P

SATA_B1_TX_P

SATA_B1_TX_N

SATA_B1_RX_N

SATA_B1_RX_P

SATA_LED*/GPIO_30

SATA_TERMP

NC_1

NC_2

NC_4

NC_3

RGMII_RXD1

RGMII_RXD0

RGMII_RXD2

RGMII_RXD3

RGMII_RXCLK

RGMII_RXCTL

RGMII_INTR/GPIO_35

+3.3V_PLL_MAC_DUAL

RGMII_COMP_VDD

RGMII_COMP_GND

USB8_P

USB_OC2*/GPIO_27_MGPIO_0

USB_OC1*/GPIO_26

USB_OC0*/GPIO_25

USB11_P

USB11_N

LAN

SATA

USB

(6 OF 11)

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

NCNCNCNC

IN

BI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Geyser Trackpad/Keyboard

External C

Watermelon

Connect RGMII_INTR to 10K pull-down (if not used as GPIO).

Internal MAC Disable:

+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail.RGMII_COMP_VDD/_GND must remain connected as shown.

Connect RGMII_MDIO to 10K pull-down.

Connect RGMII_RXCTL to 10K pull-down.

20 mA

External A

Bluetooth

SD Card/ExpressCard

IR

All other pins can be left TP or NC.

Connect RGMII_VREF to 10K pull-down.

Connect RGMII_RXCLK to 10K pull-down.

T57


Connect RGMII_RXD<0:3> together to 10K pull-down.

Camera/External E

External B

External D

OHCI0/EHCI0

OHCI1/EHCI1

Internal 19.5K Pull-Downs on all USB pairs

USB JTAG in S3/S4/S5.

Only USB8-11 support nV

AirPort (PCIe Mini-Card)

OC3# Also for EXCARDOC2# Also for EXTE

9

31 73

31 73

31 73

31 73

31 73

31 73

31 73

49.9

402MF-LF1/16W

1%

R1810

1/16WMF-LF

49.9

402

1%

R1811

MCP89M-A01FBGA

OMIT

U1400

30 72

30 72

34 72

34 72

43 72

43 72

9 72

9 72

9 72

9 72

5%1/16WMF-LF

8.2K

402

R1850

MF-LF402

8.2K5%1/16W

R1851

8.2K5%

402

1/16WMF-LF

R1852

8.2K

402

1/16WMF-LF

5%

R1853

64 72

64 72

9 72

9 72

9 72

9 72

9 72

9 72

9 72

9 72

34 72

34 72

1%

MF-LF402

1/16W

887R1860

33 71

33 71

33 71

33 71

33 71

33 71

33 71

33 71

2.49K1/16W

402

1%

MF-LF

R1805

9

9 72

9 72 1/16WMF-LF

402

100K5%

R1800

MCP SATA, USB & EthernetSYNC_DATE=02/16/2010SYNC_MASTER=T27_MLB


=PP3V3_S0_MCP_GPIO

=PP3V3_S5_MCP_GPIO

USB_BT_NUSB_BT_P

USB_TPAD_P

MCP_MII_COMP_GNDMCP_MII_COMP_VDD

PP3V3_ENET_MCP_PLL_MAC

ENET_ENERGY_DET

ENET_RX_CTRLENET_CLK125M_RXCLK

ENET_RXD<3>ENET_RXD<2>

ENET_RXD<0>ENET_RXD<1>

MCP_SATA_TERMP

MXM_GOOD_L

TP_SATA_D_D2RPTP_SATA_D_D2RN

TP_SATA_D_R2D_CNTP_SATA_D_R2D_CP

TP_SATA_C_D2RN

SATA_ODD_D2R_NSATA_ODD_D2R_P

SATA_HDD_R2D_C_NSATA_HDD_R2D_C_P

TP_ENET_RESET_L

TP_MCP_CLK25M_BUF0_R

ENET_MDIOTP_ENET_MDC

TP_ENET_TX_CTRLTP_ENET_CLK125M_TXCLK

TP_ENET_TXD<2>TP_ENET_TXD<3>

TP_ENET_TXD<0>TP_ENET_TXD<1>

MCP_RGMII_VREF

USB_IR_PUSB_IR_N

USB_EXTB_PUSB_EXTB_N

USB_TPAD_N

USB_EXTD_NUSB_EXTD_P

USB_SDCARD_NUSB_SDCARD_P

USB_CAMERA_NUSB_CAMERA_P

USB_WM_P

USB_EXTC_PUSB_EXTC_N

USB_T57_NUSB_T57_P

USB_MINI_PSATA_HDD_D2R_P

USB_WM_N

SATA_ODD_R2D_C_NSATA_ODD_R2D_C_P

SATA_HDD_D2R_N

USB_EXTA_N

TP_SATA_C_R2D_CPTP_SATA_C_R2D_CN

TP_SATA_C_D2RP

USB_EXTA_P

USB_MINI_N

USB_EXTB_OC_L

USB_EXTD_OC_L

MCP_USB_RBIAS_GND

USB_EXTC_OC_L

USB_EXTA_OC_L

18 OF 109

C.0.0

051-8561

18 OF 76

1

2

1

2

C20

B20

AJ4

AJ3

AJ2

D20

AJ5

J20

H20

C19

B19

F20

G20

E20

E19

D19

G19

F19

J17

H17

H19

B17

C17

D17

E17

K19

L19

C13

H13

G13

D14

F14

G14

E14

F13

K13

J13

J14

AH4

AH5

AH3

AH2

AJ6

AJ7

AH7

AH6

AL4

AL3

AL1

AL2

AH1

AJ1

G4

E7

F4

F7

C14

B14

D16

F16

E16

A14

H14

M16

D13

E13

J19

K17

L17

A17

F17

G17

1

2

1

2

1

2

1

2

1

2

1

2

1

2

8 9 20 23

8 17 19

8 19

73

73

23

71

9

9

9

9

9

9

9

9

9

34

72

34

OUT

OUT

IN OUT

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET*

HDA_SYNC

LPC_SERIRQ

LPC_FRAME*

LPC_RESET*

LPC_CLK0

MISC_VDDEN0/GPIO_47

MISC_VDDEN1/GPIO_48

MISC_VDDEN4/GPIO_19

MISC_VDDEN3/GPIO_18

MISC_VDDEN2/GPIO_17

MEM_VDD_SEL/GPIO_46

FANCTL0/GPIO_61

FANRPM0/GPIO_60/MGPIO_2

FANCTL1/GPIO_62

SLP_S3*

FANRPM1/GPIO_63/MGPIO_3

SLP_S5*

SLP_RMGT*

MCP_VID0/GPIO_13

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

SPI_CS0*/GPIO_10

SPI_DI/GPIO_08

SPI_DO/GPIO_09

SPI_CLK/GPIO_11

SPKR/GPIO_1

THERM_DIODE_N

THERM_DIODE_P

SMB_DATA0

SMB_CLK1/MSMB_CLK

SMB_CLK0

SMB_ALERT*/GPIO_64

SMB_DATA1/MSMB_DATA

SUS_CLK/GPIO_34

BUF_SIO_CLK/GPIO_33

PKG_TEST

TEST_MODE_EN

PKG_TEST2

+VDD_HDA

HDA_SDATA_IN0

HDA_PULLDN_COMP

HDA_SDATA_IN1/GPIO_2

LPC_AD1

LPC_AD0

LPC_DRQ0*/GPIO_43

LPC_AD3

LPC_AD2

LPC_CLKRUN*/GPIO_42

EXT_SMI*/GPIO_32

SIO_PME*/GPIO_31

A20GATE/GPIO_55

KBRDRSTIN*/GPIO_56

RSTBTN*

PWRBTN*

RTC_RST*

PWRGD_SB

PWRGD

MCP_WAKE_REQ*

MCP_MEMVDD_EN/GPIO_44

MEMVTT_EN/GPIO_45

INTRUDER*

MGPU_PIO1/GPIO_7

MGPU_PIO0/GPIO_6

MGPU_PIO3/GPIO_24

MGPU_PIO2/GPIO_23

JTAG_TDO

JTAG_TDI

JTAG_TRST*

JTAG_TCK

JTAG_TMS

XTALIN

XTALIN_RTC

XTALOUT

XTALOUT_RTC

MCP_VID3/GPIO_16

MCP_WAKE_DIS*

MISC

LPC

(7 OF 11)

HDA

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

BI

OUT

OUT

BI

BI

BI

BI

OUT

IN

IN

BI

OUT

OUT

IN

IN

OUT

OUT

IN

BI

OUT

OUT

BI

IN OUT

OUTIN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

GPIO Pull-Ups/Downs

Output limited to +VDD_HDA.

(IPD)

Straps not provided on this page.NOTE: 42 & 62 MHz use FAST_READ command.

62.5 MHz

42.7 MHz

31.2 MHz

25.0 MHz

Connects to SMC for automatic recovery.

NOTE: MCP89 A01 has

(IPU)

strong (~10K) pull-downs on these pins.

(IPU-S5)

(IPU)

(IPD)

70 mA

(IPD)

(IPU)

(IPU)

(IPU)

1

0

Frequency

24 MHz

14.31818 MHz

0

0

1

1

SPI Frequency Select

1

SPI_DO

0

Frequency

BIOS Boot Select

0

LPC_FRAME#

LPC

(IPU-S5)

(IPU)

(IPD)

(IPU)

(IPU)

0

1

NOTE: MCP89 does not support FWH, only LPC ROMs. So Apple designs will

HDA_SYNC

I/F

SPI_CLK

BUF_SIO_CLK Frequency

(IPU-S5)

1

SPI

(IPU)

NOTE: MCP SLP_S5# signal has thebehavior of Intel’s SLP_S4# signal.

70 mA

not use LPC for BootROM override.

1 = SAFE mode (For ROMSIP recovery)0 = USER mode (Normal boot mode)

MCP_SPKR:

(IPD)

(IPD)NOTE: MCP89 A01 has strong (~10K)

Platform-Specific Connections

(IPU)

(IPU-S5)

(IPD)

Confirmed OK for this signal.

pull-downs on these pins.

HDA Output CapsFor EMI Reduction on HDA interface


35 37 72

19 25 72

35 37 25 72

402

10K5%1/16WMF-LF

R19612

1

MCP89M-A01FBGA

OMIT

U1400

MF-LF1/16W

402

5%

22R1953

48 72

MF-LF402

5%1/16W

22R1952402

MF-LF1/16W

22

5%

R1951 MF-LF

5%

402

22

1/16W

R1950

48 72

48 72

48 72

402

1%1/16WMF-LF

49.9R1900

48 72

25

25

25

25

35

35

13

25

19 59

19 59

19 59

19 59

41 75

41 75

7 19 35 36 62

62

7 35 62 66

37 72

7 19 37 72

37 72

37 72

1/16WMF-LF

10K5%

402

R1970

36

1/16WMF-LF

5%

402

10KR1959

1K

MF-LF

1%1/16W

402

R1975

25 72

19 30 62

38 72

38 72

13 38 72

13 38 72

10K5%

MF-LF1/16W

402

R1930100K

MF-LF1/16W5%

402

R1931

13

13

13

13

13

25

35

35

36

1%49.9K

MF-LF402

1/16W

R1920

MF-LF1/16W1%

402

49.9KR1921

50V5%

402CERM

10PFC1951

CERM50V

10PF5%

402

C1950

50V

10PF5%

402CERM

C1953

10PF5%

402CERM50V

C1952

7 35 37

21

21 62

MF-LF

5%

402

22

1/16W

R1960MF-LF1/16W5%

22402

R1910

402MF-LF1/16W22

5%R1912 5%

221/16W MF-LF 402

R1911

402MF-LF1/16W22

5%R1913

35 37 72

35 37 72

35 37 72

35 37 72

53

35

53

7 19 37 47

19 22

19

19 26 27 35

19

19 33

19

35 36 62

19

9

19 36

5% MF-LF1/16W100K

402R1985

10KMF-LF 4021/16W5%

R1996

4025% 1/16W MF-LF10KR1988

4021/16W5% MF-LF10KR1980

100KMF-LF 4021/16W5%

R1987

10KMF-LF1/16W5% 402

R1990

5% 1/16W 402MF-LF10KR1991

10KMF-LF 4021/16W5%

R1989

MF-LF 4021/16W5%100KR1997

5% 1/16W 402MF-LF10KR1981

MF-LF1/16W5% 402100KR1992100K

MF-LF1/16W5% 402R1993

100KMF-LF1/16W5% 402

R1994

4025% 1/16W MF-LF100KR1995

40210K

MF-LF1/16W5%R1984

5% 1/16W100K

MF-LF 402R1986

7 19 37

7 19 35 36 62 35

35 37 19 25 72

33

1/16WMF-LF

5%

402

R1965

MF-LF402

1/16W5%10K

NO STUFFR1966

40210K

MF-LF1/16W5%R1983

4025% 1/16W MF-LF20KR1998

402MF-LF100K

1/16W5%R1999

SYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010

MCP HDA, LPC & MISC

HDA_BIT_CLK_R

MEM_EVENT_L

SMBUS_MCP_1_DATA

HDA_SDIN0

AUD_IPHS_SWITCH_EN

PM_BATLOW_L

MCP_PS_PWRGD

MCP_MEM_VDD_EN

LPC_AD<3>

LPC_AD<1>LPC_AD<0>

GFXVCORE_PWR_ENT57_RESET

JTAG_MCP_TMS

MCP_CLK25M_XTALOUT

LPC_AD<2>

MCP_MEM_VTT_EN

SMC_IG_THROTTLE_L

JTAG_MCP_TDI

LPC_PWRDWN_L

PM_SLP_S5_L

LPC_RESET_L

PM_SLP_S4_LMAKE_BASE=TRUE

MCP_WAKE_REQ_L

MCP_CLK25M_XTALIN

JTAG_MCP_TDO

MCP_SPKR

HDA_SDOUT

HDA_RST_R_L HDA_RST_L

HDA_BIT_CLK_R HDA_BIT_CLK

=PP3V3_S0_MCP_GPIO

LPC_FRAME_L

HDA_SDOUT_R

ARB_DETECT_L

ENET_LOW_PWRSDCARD_RESET

PM_SLP_S4_L

SPI_CLK_RSPI_MISOSPI_MOSI_R

MCP_THMDIODE_N

SMBUS_MCP_0_CLKSMBUS_MCP_0_DATASMBUS_MCP_1_CLK

AP_PWR_EN

PM_CLK32K_SUSCLK_R

SPIROM_USE_MLB

HDA_SYNC

LPC_FRAME_R_L

LPC_CLK33M_SMC_R

MCP_CPU_VTT_EN_LMLB_RAM_VENDORT57_PWR_ENSMC_ADAPTER_EN

ODD_PWR_EN_L

SMC_RUNTIME_SCI_L

LPC_SERIRQ

LPCPLUS_GPIO

AUD_I2C_INT_L

MCP_HDA_PULLDN_COMP


LPC_AD_R<1>LPC_AD_R<0>

PM_CLKRUN_L

LPC_AD_R<3>LPC_AD_R<2>

TP_MLB_RAM_SIZE

PM_LATRIGGER_L

PM_PWRBTN_L

RTC_RST_L

PM_SYSRST_DEBOUNCE_L

PM_SLP_S3_LPM_SLP_RMGT_L

MCP_VID<0>MCP_VID<1>MCP_VID<2>MCP_VID<3>

MCP_THMDIODE_P

SPI_CS0_R_L

HDA_SYNC_R

MCP_TEST_MODE_EN

LPC_RESET_L

RTC_CLK32K_XTALOUT

PM_RSMRST_L

JTAG_MCP_TCKJTAG_MCP_TRST_L

RTC_CLK32K_XTALIN

SPIROM_USE_MLB

MCP_CPU_VTT_EN_LMLB_RAM_VENDORT57_PWR_ENLPCPLUS_GPIO

ODD_PWR_EN_LMEM_EVENT_LENET_LOW_PWRSMC_IG_THROTTLE_L

MCP_VID<0>MCP_VID<1>MCP_VID<2>

AP_PWR_EN

ARB_DETECT_L

HDA_RST_R_LHDA_SYNC_R

MCP_VID<3>

SPI_MISO

HDA_SDOUT_R SM_INTRUDER_L

MCP_MEM_VDD_SEL_1V5

SMC_WAKE_SCI_LPP3V3_G3_RTC

=PP3V3_S0_MCP_GPIO

=PP3V3_S5_MCP_GPIO=PP3V3_S3_MCP_GPIO

SDCARD_RESETT57_RESETGFXVCORE_PWR_EN

19 OF 109

C.0.0

051-8561

19 OF 76

E1

E4

D1

D2

L8

L7

K7

L5

K10

C8

G8

D8

A8

C7

H7

H6

G6

C4

H4

D5

K9

K3

K5

K4

E11

F11

B8

D7

H3

G2

G3

B4

A5

A4

C5

B5

H11

H1

L16

D4

K16

D6

E2

D3

E3

L1

K1

K2

L3

L2

L6

G11

D11

B3

H2

F10

J10

G16

C11

C2

H16

B7

G10

J16

H5

G5

J11

H10

D10

C10

E10

A10

B10

A11

B16

B11

C16

K6

A7

1 2

1 2

1 2

1 2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

2

1

2

1

2

1

2

1

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1 2

1 2

1 2

19 72

19 72

19 72

8 17 18 19

19 72

19

19

19

72

8 23

19 72

7 19 37 47

19

19

19

7 19 37

19 33

19 26 27 35

19

19 36

19 59

19 59

19 59

19 30 62

19

19 72

19 72

19 59

7 19 37 72

19 72

7 8 20 23

8 17 18 19

8 18

8

19

19

19 22

+VDD_MEM_30

+VDD_MEM_31

+VDD_MEM_28

+VDD_MEM_29

+VDD_MEM_25

+VDD_MEM_26

+VDD_MEM_27

+VDD_MEM_23

+VDD_MEM_24

+VDD_MEM_22

+VDD_MEM_20

+VDD_MEM_21

+VDD_MEM_17

+VDD_MEM_18

+VDD_MEM_19

+VDD_MEM_15

+VDD_MEM_16

+VDD_MEM_12

+VDD_MEM_13

+VDD_MEM_14

+VDD_MEM_10

+VDD_MEM_11

+VDD_MEM_8

+VDD_MEM_9

+VDD_MEM_7

+VDD_MEM_5

+VDD_MEM_6

+VDD_MEM_4

+VDD_MEM_3

+VDD_MEM_2

+VDD_MEM_1

+VTT_CPU2_1

+VTT_CPU2_2

+VTT_CPU2_3

+VTT_CPU2_4

+VTT_CPU_27

+VTT_CPU_24

+VTT_CPU_25

+VTT_CPU_26

+VTT_CPU_23

+VTT_CPU_22

+VTT_CPU_21

+VTT_CPU_20

+VTT_CPU_19

+VTT_CPU_18

+VTT_CPU_16

+VTT_CPU_17

+VTT_CPU_14

+VTT_CPU_15

+VTT_CPU_11

+VTT_CPU_12

+VTT_CPU_13

+VTT_CPU_9

+VTT_CPU_10

+VTT_CPU_8

+VTT_CPU_1

+VTT_CPU_7

+VTT_CPU_6

+VTT_CPU_5

+VTT_CPU_4

+VTT_CPU_3

+VTT_CPU_2

(8 OF 11)

POWER I

POWER II

(9 OF 11)

+VDD_COREB_1

+VDD_COREB_3

+VDD_COREB_2

+VDD_COREB_4

+VDD_COREB_5

+VDD_COREB_6

+VDD_COREB_8

+VDD_COREB_7

+VDD_COREB_9

+VDD_COREB_10

+VDD_COREB_11

+VDD_COREB_13

+VDD_COREB_12

+VDD_COREB_14

+VDD_COREB_15

+VDD_COREB_16

+VDD_COREB_18

+VDD_COREB_17

+VDD_COREB_19

+VDD_COREB_20

+VDD_COREB_21

+VDD_COREB_22

+VDD_COREB_23

+VDD_COREB_24

+VDD_COREB_26

+VDD_COREB_25

+VDD_COREB_27

+VDD_COREB_28

+VDD_COREB_29

+VDD_COREB_31

+VDD_COREB_30

+VDD_COREB_32

+VDD_COREB_33

+VDD_COREB_34

+VDD_COREB_36

+VDD_COREB_35

+VDD_COREB_37

+VDD_COREB_38

+VDD_COREB_39

+VDD_COREB_40

+VDD_COREB_41

+VDD_COREB_42

+VDD_COREB_SENSE

GND_COREB_SENSE

+VIO_SATA_AVDD_1

+VIO_SATA_AVDD_3

+VIO_SATA_AVDD_2

+VIO_SATA_AVDD_4

+VIO_SATA_AVDD_5

+VIO_SATA_DVDD_1

+VIO_SATA_DVDD_2

+VIO_SATA_DVDD_3

+VIO_SATA_DVDD_4

+VIO_SATA_DVDD_5

+VIO_SATA_DVDD_6

+VIO_SATA_DVDD_7

+VIO_SATA_DVDD_8

+VIO_SATA_DVDD_9

+VIO_SATA_DVDD_10

+VIO_SATA_DVDD_11

+VIO_SATA_DVDD_12

+VDD_DUAL_RMGT_1

+VDD_DUAL_RMGT_2

+3.3V_DUAL_RMGT_1

+3.3V_DUAL_USB_1

+3.3V_DUAL_RMGT_2

+3.3V_DUAL_USB_2

+3.3V_DUAL_1

+3.3V_DUAL_2

+3.3V_HVDD_3

+3.3V_HVDD_1

+3.3V_HVDD_2

+3.3V_5

+3.3V_3

+3.3V_4

+3.3V_2

+3.3V_1

+VDD_DUAL_AUXC_2

+VDD_DUAL_AUXC_1

+VDD_DUAL_AUXC_3

+3.3V_VBAT

+VIO_PE_AVDD1_4

+VIO_PE_AVDD1_5

+VIO_PE_AVDD1_1

+VIO_PE_AVDD1_3

+VIO_PE_AVDD1_2

+VIO_PE_AVDD0_5

+VIO_PE_AVDD0_6

+VIO_PE_AVDD0_3

+VIO_PE_AVDD0_4

+VIO_PE_AVDD0_2

+VIO_PE_AVDD0_1

+VIO_PE_DVDD1_2

+VIO_PE_DVDD1_3

+VIO_PE_DVDD1_1

+VIO_PE_DVDD0_3

+VIO_PE_DVDD0_4

+VIO_PE_DVDD0_2

+VIO_PE_DVDD0_1

+VDD_COREA_32

+VDD_COREA_33

+VDD_COREA_30

+VDD_COREA_31

+VDD_COREA_29

+VDD_COREA_28

+VDD_COREA_27

+VDD_COREA_25

+VDD_COREA_24

+VDD_COREA_26

+VDD_COREA_22

+VDD_COREA_23

+VDD_COREA_21

+VDD_COREA_19

+VDD_COREA_20

+VDD_COREA_18

+VDD_COREA_16

+VDD_COREA_17

+VDD_COREA_15

+VDD_COREA_14

+VDD_COREA_11

+VDD_COREA_12

+VDD_COREA_13

+VDD_COREA_9

+VDD_COREA_10

+VDD_COREA_6

+VDD_COREA_7

+VDD_COREA_8

+VDD_COREA_4

+VDD_COREA_5

+VDD_COREA_1

+VDD_COREA_3

+VDD_COREA_2

GND_COREA_SENSE

+VDD_COREA_SENSE

(10 OF 11)

GND

GND_28

GND_29

GND_27

GND_97

GND_98

GND_69

GND_68

GND_71

GND_70

GND_72

GND_74

GND_73

GND_75

GND_76

GND_77

GND_78

GND_79

GND_80

GND_81

GND_82

GND_84

GND_83

GND_85

GND_86

GND_87

GND_89

GND_88

GND_90

GND_92

GND_91

GND_94

GND_93

GND_95

GND_96

GND_99

GND_102

GND_100

GND_101

GND_103

GND_104

GND_105

GND_107

GND_106

GND_109

GND_108

GND_110

GND_112

GND_111

GND_113

GND_114

GND_115

GND_117

GND_116

GND_118

GND_119

GND_120

GND_122

GND_121

GND_123

GND_124

GND_125

GND_126

GND_127

GND_128

GND_130

GND_129

GND_131

GND_133

GND_132

GND_134

GND_2

GND_1

GND_4

GND_3

GND_6

GND_7

GND_5

GND_8

GND_9

GND_12

GND_11

GND_10

GND_14

GND_13

GND_15

GND_16

GND_17

GND_19

GND_18

GND_20

GND_21

GND_22

GND_23

GND_24

GND_25

GND_26

GND_30

GND_31

GND_32

GND_35

GND_34

GND_33

GND_37

GND_36

GND_38

GND_40

GND_39

GND_43

GND_41

GND_42

GND_45

GND_44

GND_47

GND_48

GND_46

GND_50

GND_49

GND_53

GND_52

GND_51

GND_55

GND_54

GND_56

GND_57

GND_58

GND_60

GND_59

GND_61

GND_62

GND_63

GND_64

GND_65

GND_66

GND_67

(11 OF 11)

GND

GND_157

GND_158

GND_199

GND_198

GND_197

GND_196

GND_195

GND_194

GND_193

GND_192

GND_191

GND_188

GND_190

GND_189

GND_187

GND_186

GND_183

GND_184

GND_185

GND_182

GND_181

GND_179

GND_180

GND_178

GND_177

GND_176

GND_175

GND_173

GND_174

GND_170

GND_172

GND_171

GND_169

GND_168

GND_166

GND_165

GND_167

GND_164

GND_163

GND_161

GND_160

GND_162

GND_159

GND_156

GND_155

GND_154

GND_153

GND_152

GND_150

GND_151

GND_147

GND_149

GND_148

GND_146

GND_145

GND_142

GND_143

GND_144

GND_140

GND_141

GND_138

GND_139

GND_137

GND_136

GND_135

GND_264

GND_263

GND_262

GND_261

GND_259

GND_258

GND_260

GND_256

GND_257

GND_254

GND_253

GND_255

GND_252

GND_251

GND_250

GND_249

GND_248

GND_246

GND_247

GND_245

GND_244

GND_243

GND_241

GND_242

GND_240

GND_239

GND_238

GND_236

GND_235

GND_237

GND_233

GND_234

GND_232

GND_230

GND_231

GND_228

GND_229

GND_227

GND_225

GND_226

GND_223

GND_224

GND_220

GND_222

GND_221

GND_219

GND_218

GND_217

GND_215

GND_216

GND_213

GND_212

GND_214

GND_211

GND_210

GND_209

GND_208

GND_207

GND_205

GND_206

GND_203

GND_204

GND_202

GND_200

GND_201




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B


NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.

?? uA (G3)

250 mA

be used for remote sensing unlessNOTE: VDD_COREx_SENSE signals should NOT

(PE0[5:4], PE1[1:0])

(PE0[3:0])

as close to COREB FET as possible.

regulators. COREA/COREB are powered by separate

4300 mA2000 mA

200 mA

8450 mA (0.85V) 15350 mA (0.85V)

300 mA

100 mA

300 mA

200 mA

40 mA

240 mA

140 mA

5 mA (S0)

150 mA

200 mA (DVDD0 & DVDD1)

30 mA

(PE0[3:0])500 mA (AVDD0 & AVDD1)

Okay to GND if not using PE0[3:0]

500 mA (AVDD0 & AVDD1)(PE0[5:4], PE1[1:0])

Okay to GND if not using PE0[3:0]

200 mA (DVDD0 & DVDD1)

Instead connect regulator sense point

FBGA

OMIT

MCP89M-A01U1400

CKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2Gnd

CKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2Gnd

OMIT

MCP89M-A01FBGA

U1400

FBGA

OMIT

MCP89M-A01U1400

MCP89M-A01

OMIT

FBGA

U1400

MCP Power & GroundSYNC_DATE=02/16/2010SYNC_MASTER=T27_MLB


=PP1V05_S0_MCP_FSB



PP3V3_G3_RTC

TP_MCP_VDDCOREA_SENSEP

=PP1V05_SW_MCP_FSB

TP_MCP_VDDCOREB_SENSEN

=PPVCORE_SW_MCP_GFX

PP1V05_S0_MCP_SATA_AVDD

=PPVCORE_S0_MCP

TP_MCP_VDDCOREA_SENSEN



=PP3V3_S0_MCP_HVDD

TP_MCP_VDDCOREB_SENSEP

=PP3V3_S5_MCP


=PP3V3_S0_MCP




20 OF 109

C.0.0

051-8561

20 OF 76

AJ10

AF20

AJ8

AF14

AL8

AF17

AJ11

AM3

AL5

AF15

AH12

AM2

AG17

AL6

AG16

AJ9

AF19

AM5

AG19

AF23

AF22

AG20

AG13

AF16

AK8

AM1

AM4

AF21

AF18

AL7

AG14

W27

W28

Y27

Y28

N26

H31

B32

R26

T26

U26

H30

M28

E32

C32

U27

G31

H29

W26

P26

F32

A32

J29

N27

T27

G32

P27

V26

Y26

L29

D32

K29

M4

P4

M2

N12

N4

N14

N10

V20

P3

P1

N11

P6

N6

N2

N9

N8

N3

M10

N1

M5

M7

P2

M8

M11

N7

V19

N16

P5

N5

N15

N13

P9

V17

V18

M13

M14

Y19

Y20

Y17

Y18

P7

P8

U10

T10

AE1

AE3

AE2

AE4

AE5

AF1

AF2

AF3

AF4

AF5

AF6

AF9

AF10

AF11

AE11

AE12

AE13

L12

L13

A13

A20

B13

A19

F8

E8

U13

T11

T12

E5

F5

E29

U12

U11

M17

L11

M20

A16

W12

W13

Y12

AA13

Y13

AD13

AB13

AC12

AD11

AB12

AC13

AE7

AE8

AE6

AE9

AE10

AF8

AF7

P10

P11

AA22

P12

Y22

W22

V22

T9

T5

U22

R5

T7

T4

T8

R8

R2

AB19

P13

R4

AB21

AB18

T1

T2

AB17

R10

T6

T13

R11

R13

R7

T3

AB20

AB22

L9

L10

M32

B2

B18

AM27

AP27

B12

AD7

E12

D12

G12

AL12

A2

AM6

AD37

AG32

H12

AR35

H9

G24

V10

AL30

V5

G7

V29

AP15

AJ12

AN2

AR15

D21

N20

G21

E21

H21

AR27

AM15

AH24

AA31

AM9

K12

J31

E30

V7

AK7

AU12

M31

AP6

A36

B37

F35

L27

D35

AP30

AL24

AH15

B21

AV3

B38

AT38

AA21

AD4

A37

AP18

AN4

B24

V4

D30

AA7

AK4

AD34

R37

M37

AP21

AU37

AM21

D18

B1

AC27

AD5

J2

C1

AM30

AT1

AP24

AT3

AM33

AE27

AJ24

AA8

AH18

AM18

B6

J32

AJ21

AK35

H15

D33

E6

J5

K18

F34

AD10

AN34

R35

V8

AR9

AA10

AA2

H8

R32

AG29

AM12

AP12

V32

AR33

AH21

AA32

J7

K24

AK37

AG34

J8

K21

AG8

AN5

V2

AD2

AD32

D15

AG2

L15

AK32

AR12

AN35

AN37

AH27

E18

H27

N19

L4

D9

AV37

AL27

G15

A3

L18

B15

AJ15

AA4

H18

AU38

E9

E27

L21

AG10

AU1

J4

AU27

AH30

J34

AU33

AR30

AK34

E15

D27

J35

R34

C38

V28

M34

AA11

B27

AL21

V34

K11

AK31

AU21

AA34

M19

K15

E24

N18

AK5

D24

AU30

H24

AR21

B30

AM24

AU9

AA5

G18

B9

AL18

AR24

AD35

AJ18

AG5

AU15

AU24

U21

AA20

AA19

AA18

AB27

AA26

AA17

W19

W20

AD29

AD28

AG4

N17

AA29

AA28

V21

W17

W18

U20

U19

W21

U18

Y21

V31

K8

U17

R31

R28

G30

R29

AB26

M29

AL9

F2

K27

L14

K14

AR18

AG37

AL15

V37

AA37

AU2

AD31

AP9

AD8

AG7

AG35

AJ27

G9

AV36

AR6

B33

AU18

AA35

G27

V35

J37

F37

C3

AK2

AU6

AV2

E33

M35

8 9 18 23

8 14 23

15 21 23

8 23

7 8 19 23

8 23

22 24

23

8 23

8

8

8 23

8 23

8

8 23

8

8 23

8 23

NC

NC

OUT

OUTIN

BI

BI

BI

BI

D

G S

IN

VCC

D

DONE

G

GNDTHRM

S

EN

CNFG

PAD

NC

K1

G

S

SENSE

D

KELVIN

D

G

G

D

S

S

D

G

G

D

S

S




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

droop during Q2300 turn-on.C2300 helps reduce input rail

STMFS4854N

10 mOhm @3.2V

4.3 A (EDP)

N-Channel

Part

Type

Rds(on)

Loading

Q2300

(OR 1.35V)

4250 mA

- FET Ron <= 3.8 mOhms- Max Ramp-Up Time: 65 uS (ENABLE to 90%)- Min Ramp-Up Time: 20 uS (10% to 90%)

NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.

Gated Rail Savings: 120mW

(G driven to VCC)

Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)

<R1>

DIMM CKE Clamps

NO STUBS on CKE signals!

Clamps enable before MCP89 MEMVDD rail switched off.Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.

CKE must be held low to keep memory in self-refresh.

Q2355/Q2356 chosen for low output capacitance.

NV Requirements:

40

40

1%1/16W

402

560K

MF

R2305

19 62

20%10VCERM402

0.1UFC2305

100UF20%

6.3VCERM-X5R

1206-1

PLACE_NEAR=Q2300.9:2 mm

CRITICALC2300

15 27 70

15 27 70

15 26 70

15 26 70 SOD-VESM-HFSSM3K15FVQ2350

19

MF-LF402

10K1/16W

5%

R2350

SLG5AP031TDFN

CRITICAL

U2305

STMFS485NST1G

DFN

CRITICAL

Q2300

Q2355SOT-963

NTUD3170NZXXG

CRITICAL

SOT-963

Q2356NTUD3170NZXXG

CRITICAL

SYNC_MASTER=K6_MLB SYNC_DATE=02/16/2010

MCP89 Memory Rail Gating

MCPDDRFET_KELVIN

MCPDDRFET_SENSEMCP_MEM_VDD_EN

MCPMEM_CNFG

TP_MCPMEM_DONE

=PP1V5R1V35_S0_MCPDDRFET


MAKE_BASE=TRUEVOLTAGE=1.5VMIN_NECK_WIDTH=0.2 mm

PP1V5R1V35_SW_MCP

=PP5V_S3_MCPDDRFET

MCPMEM_GATE

=PP5V_S3_MCPDDRFET


MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_B_CKE<1>

MEMVTT_EN_L

MEM_B_CKE<0>

MCP_MEM_VTT_EN

23 OF 109

C.0.0

051-8561

21 OF 76

1

2

2

1

2

1

12

3

1

2

1

5

8

7

4 9

6

2

3

8

321 5

4

6

7

9

3

1

2

4

5

6

3

1

2

4

5

6

8

8 21

8 21

15 20 23

OUT

OUT

S

D

G

IN

CNFG

EN

S

THRMGND

G

DONE

D

VCC

PAD




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

<C1>

Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)

(G driven to VCC)

- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)

Q2400

15.35 A (EDP)

NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.

droop during Q2400 turn-on.C2400 helps reduce input rail

N-Channel

Si4838BDY

3.2 mOhm @2.5V

- Min Ramp-Up Time: 100 uS (10% to 90%)

- FET Ron <= 2.5 mOhms

Gated Rail Savings: 860mW

NV Requirements:

Type

Part

Loading

Rds(on)

XW2401

PLACE_NEAR=C2400.2:1 mm

SM

XW2400SM


59 75

59 75

Q2400CRITICAL

SI4838BDYSO-8

19

C240520%10VCERM402

0.1UF

C2400100UF


CRITICAL

1206-1CERM-X5R6.3V20%

C240610%

CERM

820PF

402

50V

U2405SLG5AP033

TDFN

CRITICAL


MCP89 GFX Core Rail Gating

=PP5V_S0_MCPFSBFET

TP_MCPGFX_DONEVOLTAGE=0.9V


MAKE_BASE=TRUE

PPVCORE_SW_MCP_GFX

GFXVCORE_PWR_EN

MCPGFX_CNFG

=PPVCORE_S0_MCPGFXFET

MCPGFX_GATE

MCPCORES0_VSEN_P

MCPCORES0_VSEN_N

=PPVCORE_SW_MCP_GFX

24 OF 109

C.0.0

051-8561

22 OF 76

1 2

1 2

4

31 2

5 6 7 8

2

1

2

1

2

1

3

2

6

94

7

8

5

1

8

8

20 24

OUT

D

S

G+IN

-IN

V+

V-

+IN

-IN

V+

V-

DS

G

IN

NC

VOUT

EN

VIN

GND





36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DO NOT SYNC FROM T27. DECOUPLING CAP VALUES CHANGED.

MCP 1.05V PCIE Digital Power

MCP 2.0V-3.3V RTC Power

210 mA

140 mA

MCP 0.9V AUX Core Power

PLACEMENT_NOTEs:

(For R and C)

MCP 3.3V PLL Power

MCP S0 FSB (VTT) PowerMCP CPU FSB (VTT) Power

4300 mA (1.5V)

250 mA

MCP Memory Power

MCP Non-GFX Core Power

8450 mA (0.85V)

2000 mA

150 mA

200 mA

300 mA

240 mA

MCP 1.05V Memory DLL Power

200 mA

? uA (G3)5 mA (S0)

30 mA

500 mA

325 mA

160 mA

MCP 1.05V PCIe Analog Power

MCP 1.05V PCIe/SATA PLL Power

MCP 1.05V CPU/FSB/MEM PLL Power

70 mA

300 mA

MCP 1.05V SATA Analog Power

800 mA

555 mA

MCP 1.05V Core/Misc PLL Power

MCP 3.3V I/O Power

70 mA

MCP 3.3V/1.5V HDA Power

20 mA

MCP 3.3V MAC PLL Power

550 mA

MCP 3.3V AUX/USB Power

50 mA

100 mA

MCP 0.9V MAC/SMU Power

MCP 3.3V MAC/SMU Power

Current #s from MCP89 A01 Bring-Up Support doc (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009)

260 mA

MCP 1.05V SATA Digital Power

20 mA

MCP 3.3V PCIe/SATA I/O PLL Power

MCP 3.3V DP & USB PLL Power

C25030.22UF

402X5R

20%6.3V

1UFC250210%

402-1X5R10V 10V

402CERM

20%

C25070.1UF0.1UF

402CERM10V20%

C2506C2505

10V

0.1UF

402CERM

20%0.1UF10V20%

CERM402

C25040.1UF

402

10V20%

C2508

CERM

X5R10V10%1UF

402-1

C25314.7UF

402X5R

20%4V

C2536

402

0.1UF10VCERM

20%

C251920%10VCERM402

0.1UFC2518

10VCERM402

20%

C25170.1UF

10VCERM402

20%0.1UFC2516

0.1UF10VCERM402

20%

C2515C251420%10V

402CERM

0.1UFC251320%10VCERM402

0.1UF0.1UF20%10VCERM402

C251220%10VCERM402

C25110.1UF

402

20%

X5R

4.7UF4V

C2510

L256030-OHM-5A

0603

L256730-OHM-5A

0603

10UF

603-1X5R

20%6.3V

C2500 C2501

X5R4V

402

4.7UF20%

C252720%10VCERM402

0.1uF10V20%

CERM402

0.1uFC2526

C25370.1uF

402

20%10VCERM

0.1uF10VCERM402

20%

C2534

CERM

20%10V

402

C25560.1UF

20%

CERM10V

402

C25290.1uF

4V

402X5R

20%4.7uF

C2528

20%10VCERM402

0.1uFC2549

20%

CERM

4.7UF6.3V

603

C2548

0.1uF20%10VCERM402

C2535

402

0.1uF

CERM10V20%

C25544.7uF

C2553

CERM

20%6.3V

603

0.1uF20%10VCERM402

C255120%

CERM

4.7uF6.3V

603

C2550

C254320%

CERM

4.7uF6.3V

603 402

20%10VCERM

0.1uFC2544

402

20%10VCERM

0.1uFC2545

0.1uF20%10VCERM402

C2546

CERM

0.1uF

402

10V20%

C2547

C252010UF

603-1X5R

20%6.3V

20%

X5R402

4.7UF4V

C25211UF

402-1X5R10V10%

C2522

X5R

1UF

402-1

10V10%

C2523 C25251UF

X5R10V10%

402-1

4.7UF

402X5R

20%4V

C2524

4.7UF

CERM

20%6.3V

603

C2555

C2560

6.3V

10UF

603-1X5R

20%4.7UFC2561

4V

402X5R

20%

402-1

C25621UF

X5R10V10% 10%

C2563

402-1

1UF

X5R10V

20%0.1UF

402CERM10V

C2564

C2567

6.3V

10UF

603-1X5R

20%

C25684.7UF

X5R4V

402

20%

C256920%10VCERM402

0.1UF

C25650.1UF

402CERM10V20%

402CERM10V20%

C25660.1UF

20%

X5R402

4.7UF4V

C2540

20%

402CERM10V

C25420.1uF

C2541

603

6.3V

4.7UF

CERM

20%

C257220%10VCERM402

0.1uFC2571

402CERM10V20%0.1UF

PLACE_NEAR=R2570.1:50 mil

20%4.7UF

C2570

4VX5R402

0402

R25700.33

5%

MF1/16W

C25730.1UF

402CERM10V20%

C25780.1UF

402CERM10V20%

C25770.1uF

402CERM10V20%

C25760.1UF20%10V

402CERM

402

4VX5R

20%

C25754.7UF

0.1UF20%10VCERM

C2583

402402CERM10V20%

C25820.1uF

C2581

CERM

0.1UF20%

402

10VX5R402

4V20%

4.7UFC2580

C257920%10VCERM402

0.1UF

CERM402

20%10V

0.1UFC2584

4.7UFC2552

603

6.3V20%

CERM

0603

L2570220-OHM-2.2A

CRITICAL

CRITICALL2580

220-OHM-2.2A

0603

CRITICAL

0603

220-OHM-2.2AL2575

CRITICAL

0402

FERR-240-OHM-200MAL2555

C25302.2UF

6.3V20%

402-LFCERM

402-LF

C2533

6.3VCERM

2.2UF20%

C2532

CERM6.3V20%

402-LF

2.2UF

35

X5R402

Place close to SMC

6.3V20%0.22UFC2598HTOL_SENSE:YES

R2598HTOL_SENSE:YES

402

1%1/16WMF-LF

4.53K

Place close to SMC

0.1UF20%10VCERM402

C2591

Q2592CRITICAL

HTOL_SENSE:YESSOT-563-HFNTZD3152P

OPA330SC70-5

HTOL_SENSE:YES

U2593CRITICAL

402

HTOL_SENSE:YESR2597

1%

MF-LF1/16W

1K

OPA330U2594SC70-5

CRITICALHTOL_SENSE:YES

20%

CERM603

6.3V

4.7UFC2590

1/16W

R2590

1%MF-LF402

HTOL_SENSE:YES

845K

L2590

0402

FERR-240-OHM-200MA

CRITICAL

0.1uFC259720%10V

402CERM

402

20%

C2594

10VCERM

0.1UF

HTOL_SENSE:YES

HTOL_SENSE:YESR2599

402MF-LF1/16W

5%100K

R2596

402MF-LF

1%1/16W

HTOL_SENSE:YES

1K

CRITICAL

SOT-563-HFNTZD3152PQ2592

HTOL_SENSE:YES

10%10V

402X5R

1UFC2592MCPHVDD:P2V5

35

C25960.1UF

402

20%

CERM10V

4.7UF

CERM

20%6.3V

603

C2595

PLACE_NEAR=R2595.1:50 mil

0402

1/16W

0.33

5%

MF

R2595

20%

402CERM

0.1UF

HTOL_SENSE:YES

C2599

10V

402

1/16W5%

MF-LF

10K

LDO:ADJR2594

MF-LF

5%

LDO:ADJ

10K

402

R2591

1/16W

MCPHVDD:P3V3

MF-LF402

5%

R25930

1/16W

OMIT_TABLE

SC70

U2592

CRITICAL

MIC5365-2.5V

0603

L2595220-OHM-2.2A

CRITICAL

MCPHVDD:P2V5

X5R402

C25931UF10%10V

MCPHVDD:P2V5

402

R2592

MF-LF1/16W

5%10K

1/16WMF-LF

0

402

5%

R2550

353S2979 IC,LDO,TPS717,ADJ,150MA,3%,SC70,HFLF CRITICAL LDO:ADJU25921

353S2987 IC,TPS71725,LDO REG,2.5V,150MA,SC70 LDO:FIXED1 U2592 CRITICAL

RES,0402,0,5%,1/16W116S0004 R25961 HTOL_SENSE:NOCRITICAL

SYNC_MASTER=(T27_MLB)

MCP Standard DecouplingSYNC_DATE=(11/16/2009)


=PP1V05_S0_MCP_PE_DVDD


SMC_N_MIRROR

SMC_NB_MISC_ISENSE


VOLTAGE=3.3V

PP3V3_S0_MCP_PLL_HVDD

=PP1V05_SW_MCP_FSB


=PP3V3_S5_MCP

=PP1V05_S0_MCP_FSB


PP3V3_G3_RTC

=PP3V3_S0_MCP_HVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MMPP1V05_S0_MCP_PE_AVDDMIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V05_S0_MCP_SATA_AVDD

VOLTAGE=1.05V

=PP1V05_S0_MCP_AVDD_UF

PP1V05_S0_MCP_PLL_FSBMEM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_PEXSATAMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM

=PP3V3_S0_MCP


=PP3V3_ENET_MCP_PLL_MACMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM

VOLTAGE=3.3V

PP3V3_ENET_MCP_PLL_MAC

SMC_N_FOLLOW GND_SMC_AVSS


MIN_LINE_WIDTH=0.25 MMGND_MCP_PLL_FSBMIN_NECK_WIDTH=0.25 MMVOLTAGE=0V

SMC_P_FOLLOW

OPA_MIRROR_OUT



PP1V05_S0_MCP_PLL_COREMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

=PP3V3_S0_OPA330

SMC_P24VOLTAGE=3.3V


PP3V3_S0_MCP_HVDD

GND_MCP_PLL_DP_USBMIN_LINE_WIDTH=0.25 MM

VOLTAGE=0VMIN_NECK_WIDTH=0.25 MM

MCP_PLL_LD0_EN


LDO_ADJ

=PP3V3_S0_OPA330

PP3V3_S0_LDO_R


VOLTAGE=3.3V

PP3V3_S0_LDO_R_BRDGMIN_LINE_WIDTH=0.4 MM

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MM

=PPVCORE_S0_MCP

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP3V3_S0_MCP_PLL_DP_USB

25 OF 109

C.0.0

051-8561

23 OF 76

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

21

21

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1 2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

21

21

21

21

2

1

2

1

2

1

2

1

1 2

2

1

4

3

5

2

5

41

3

2

5

4

1

3

2

1

1 2

21

2

1

2

1

1 2

1 6

2

2

1

2

1

2

1

1 2

2

1

1

2

1

2

1 2

2

4

5

3

1

21

2

11

2

8

8

8 9 18 20

16

8 20

8 15

8 20

8 14 20

15 20 21

7 8 19 20

8 20

8

20

8

15

16

8 20

8 19

8 18

35 36 39 40

8 20 8 20

8

17

8 23

8 20

8 23

8 20




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B


MCP 3.3V/1.8V IFP Interface Power MCP 1.05V IFP PLL Power

MCP 1.05V DisplayPort Power

160 mA

MCP GFX Core Power

MCP 3.3V RGBDAC Power

If RGBDAC is not used, tie to GND.

plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap.If RGBDAC is used, requires ferrite (155S0382)

15350 mA (0.85V)

60 mA180 mA (1.8V LVDS)

140 mA

NO STUFF

0.1UF20%10V

CERM402

C2650

NO STUFF

1K

MF-LF402

1%1/16W

R2655

10V20%

402CERM

0.1UF

NO STUFFC2655

4.7UF20%

402X5R4V

C2640

1/16W5%

402MF-LF

0R2670

603CERM6.3V

4.7uF20%

C2620

CERM

20%0.1uF

402

10V

C2621

10V

402

0.1uF20%

CERM

C2631

402X5R4V

4.7uF20%

C2630

6.3VX5R

20%10UF

603-1

C26004.7UF

402X5R4V20%

C26011UF

402-1X5R10V10%

C26021UF

402-1X5R10V10%

C2603

402X5R6.3V20%0.22UFC2604

0.22UF

402X5R6.3V20%

C26050.1UF10V20%

CERM402

C26060.1UF

402CERM10V20%

C26070.1UF

402CERM10V20%

C26080.1UF

402CERM10V20%

C26090.1UF

402CERM10V20%

C26100.1UF

402CERM10V20%

C26110.1UF

402CERM10V20%

C2612

CERM

20%0.1uF

402

10V

C2641

1%1/16WMF-LF402

1KR2650

SYNC_DATE=02/16/2010

MCP Graphics SupportSYNC_MASTER=T27_MLB



MCP_IFPAB_RSETMCP_TMDS0_VPROBEMCP_TMDS0_RSET


MCP_IFPAB_VPROBE

PP3V3_S0_MCP_DAC

MAKE_BASE=TRUE

GND_MCP_DAC_P3V3

VOLTAGE=0VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM

=PPVCORE_SW_MCP_GFX

26 OF 109

C.0.0

051-8561

24 OF 76

2

1

1

22

1

2

1

1

2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1

2

8 17

8 17

17 71

17 71

17 71

8 17

17 71

17

20 22

IN OUT

IN OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUTIN

NCNC

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

B

Y

A




36

BRANCH

REVISION

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DR


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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MCP 25MHz Crystal

LPC Reset (Unbuffered)

Platform Reset Connections

DO NOT SYNC WTIH T27. REMOVED PCIE RESET SIGNALS +CAESAR XTAL

MCP S0 PWRGD & CPU_VLD

10K pull-up to 3.3V S0 inside MCP

RTC Crystal

System Reset Circuit

PCIE Reset (Unbuffered)

10 13 19

50V

402CERM

5%

12pFC2810

12pF

402CERM50V5%

C2811

402

1/16W

0

5%

MF-LF

R2810

10M

402

5%

MF-LF1/16W

NO STUFFR2811 19 72

1/16W

402

0

5%

MF-LF

XDP

R2896

402

1/16W5%

MF-LF

33

PLACE_NEAR=U1400.K7:5 MM

R2883

33

1/16W5%

MF-LF402

PLACE_NEAR=U1400.K7:5 MMR2881

5%

SILK_PART=SYS RSTPLACEMENT_NOTE=Place R2897 on BOTTOM

01/16WMF-LF

402

OMITR2897

37

35

19

19

16

402

1/16WMF-LF

5%

33

PLACE_NEAR=U1400.L5:5 MM

R28265%

33

MF-LF1/16W

402

PLACE_NEAR=U1400.L5:5 MMR2825

19 72

12pF

402CERM

5%50V

C2815

50V5%

CERM402

12pFC2816

CRITICAL

25.0000MSM-3.2X2.5MM

Y2815

0

MF-LF

5%

402

1/16W

R2815

1M5%

402MF-LF

NO STUFF

1/16W

R2816

19

19

35 72

22

1/16W5%

MF-LF402

PLACE_NEAR=U1400.H11:5 MM

R282919 72

33

5%

MF-LF402

1/16W

R2899

10%1UF

X5R10V

402

NO STUFFC2899

35

37 72

35 72

CRITICAL

7X1.5X1.4-SM32.768KY2810

0

5%

MF-LF1/16W

402

R289129

0

5%1/16WMF-LF402

R289368

30

402

0

5%

MF-LF1/16W

R2894

35 62

58

402CERM10V20%

0.1UFC2850

19

SOT35374LVC1G08GWU2850 SB Misc

SYNC_MASTER=(T27_MLB) SYNC_DATE=(10/07/2009)

MCP_CLK25M_XTALIN

SMC_LRESET_L

LPC_RESET_L

LPC_CLK33M_SMC_R

PCIE_RESET_LMAKE_BASE=TRUE

PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

AP_RESET_L

BKLT_PLT_RST_L

PCA9557D_RESET_L

ALL_SYS_PWRGD

VR_PWRGOOD_DELAY

MCP_CLK25M_XTALOUT MCP_CLK25M_XTALOUT_R

RTC_CLK32K_XTALOUT RTC_CLK32K_XTALOUT_R

PM_SYSRST_L

PM_SYSRST_DEBOUNCE_L

LPCPLUS_RESET_L

XDP_DBRESET_L

RTC_CLK32K_XTALIN

MCP_PS_PWRGD

=PP3V3_S5_MCPPWRGD

28 OF 109

C.0.0

051-8561

25 OF 76

1 2

1 2

1 2

1

2

1 2

1 2

1 2

1

2

1 2

1 2

1 2

1 2

31

24

1 2

1

2

1 2

1 2

2

1

41

1 2

1 2

1 2

2

1

4

3

1

2

5

8

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4*

DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS

DQ58

DQ59

DM7

VSS

DQ57

DQ56

DQ50

DQ51

VSS

DQS6*

DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS

DQ42

SDA

SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60

DQ61

VSS

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS

DQ40

DQ34

VSS

DQ32

TEST

VDD

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD

CK0

A1

A3

VDD

VDD

A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS

DQ44

DQ45

DQ39

DQ38

VSS

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD

ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

VDD

A0

CK1

A2

VDD

A4

VDD

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI

BIBI

BI

IN

BI

BI

BI

BI

BI

BI

IN

BI

IN

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

DQ16

DM3

DQ26

DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24

DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8

DQ9

DM0

DQ0

DQ1

VREFDQ

DQ3

DQ2

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSKEY

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

(SYMBOL 1 OF 2)

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

IN

BI

BI

IN

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

NC

NC

NC




36

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REVISION

DRAWING NUMBER SIZE

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PAGE TITLE

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A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

SPD Addr: 0xA0(Wr)/0xA1(Rd)

- =PPLVDDR_S3_MEM_A

NOTE: J3100 is OMITted on this page. Proper APN(s) required elsewhere.

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

Molex: 516-0213Foxconn: 516-0201

- =PPSPD_S0_MEM_A (2.5 - 3.3V)- =PPDDRVTT_S0_MEM_A

- =I2C_SODIMMA_SCL

Molex: 516-0213Foxconn: 516-0201

- =I2C_SODIMMA_SDA

(NONE)

"Factory" (top) slot

DDR3 Plane Stitching Caps (Space evenly across plane split)

OMITCRITICAL

F-RT-THB

DDR3-SODIMM-DUAL-M97-3

J290028

28

10V20%

402CERM

0.1UFC2931

2.2UF

CERM402-LF

20%6.3V

C2930 28

28

15 21 70

28

28

28

28

28

28

28

28

15 27

28

28

28

28

28

28

28

28

28

28

28

28

CRITICALOMIT

DDR3-SODIMM-DUAL-M97-3

F-RT-THBJ290028

28

28

28

28

28

28

28

28

28

28

28

28

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

28

28

28

28

28

28

28

15 70

28

28

28

28

28

28

28

28

28

28

10V20%

402CERM

0.1UFC2936

6.3V20%

402-LFCERM

2.2UFC2935

28

28

28

28

28

28

28

28

28

28

28

28

19 27 35

38

38

15 21 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

10K1/16W5%

402MF-LF

R294110K

MF-LF402

5%1/16W

R29402.2UF

CERM402-LF

20%6.3V

C2940

6.3V20%

603X5R

10UFC2900

10UF20%

6.3VX5R603

C2901

402

10V20%

CERM

0.1UFC29102

1

0.1UF

CERM

20%10V

402

C29112

1402

0.1UF

CERM

20%10V

C29122

1402

0.1UF

CERM

20%10V

C29132

1402CERM

20%10V

0.1UFC29142

1 10V20%

CERM

0.1UF

402

C29152

1 10V20%

CERM

0.1UF

402

C29162

1 10V20%

CERM

0.1UF

402

C29172

1402

0.1UF

CERM

20%10V

C29182

1 10V20%

CERM

0.1UF

402

C29192

1 10V20%

CERM

0.1UF

402

C29202

1 10V20%

CERM

0.1UF

402

C29212

1 10V20%

CERM

0.1UF

402

C29222

1 10V20%

CERM

0.1UF

402

C29232

1


DDR3 SO-DIMM Connector A

=MEM_A_DQS_N<2>

=MEM_A_DQ<19>

=MEM_A_DQ<5>

=MEM_A_DQS_N<0>=MEM_A_DQS_P<0>

=MEM_A_DQ<6>=MEM_A_DQ<7>




=MEM_A_DM<1>MEM_RESET_L

=MEM_A_DM<2>




=MEM_A_DQ<30>=MEM_A_DQ<31>=MEM_A_DQ<27>

=MEM_A_DQ<26>

=MEM_A_DM<3>


=MEM_A_DQ<18>

=MEM_A_DQS_P<2>






=MEM_A_DM<0>


MEM_A_CKE<1>





MEM_A_CLK_P<1>MEM_A_CLK_N<1>

MEM_A_BA<1>MEM_A_RAS_L

MEM_A_CS_L<0>MEM_A_ODT<0>

MEM_A_ODT<1>







=MEM_A_DM<6>





MEM_A_CKE<0>

MEM_A_BA<2>


MEM_A_A<5>

MEM_A_A<1>

MEM_A_CLK_P<0>MEM_A_CLK_N<0>

MEM_A_A<10>MEM_A_BA<0>

MEM_A_CAS_LMEM_A_WE_L

MEM_A_A<3>

MEM_A_A<13>MEM_A_CS_L<1>





=MEM_A_DM<5>



=MEM_A_DQ<57>

=MEM_A_DM<7>


PPVREF_S3_MEM_VREFCA_A

PPVREF_S3_MEM_VREFDQ_A

MEM_EVENT_L=I2C_SODIMMA_SDA=I2C_SODIMMA_SCLMEM_A_SA<1>

MEM_A_SA<0>=PPSPD_S0_MEM_A

=PPDDRVTT_S0_MEM_A

MEM_A_A<8>

=MEM_A_DQ<56>


=MEM_A_DQS_P<6>=MEM_A_DQS_N<6>

=MEM_A_DM<4>

=PPLVDDR_S3_MEM_A

=MEM_A_DQ<4>

29 OF 109

C.0.0

051-8561

26 OF 76

90

86

84

91

131

105

107

124

195

201

203

127

135

137

139

143

151

103

197

189

191

193

187

179

183

181

175

177

173

169

171

167

165

163

159

161

153

155

157

200

202

204

196

198

192

190

194

186

188

180

182

184

178

176

174

170

172

166

168

164

160

162

154

156

158

149

145

147

141

133

129

125

123

117

121

119

115

113

109

111

99

101

97

95

93

87

89

85

83

81

79

77

75

73

150

152

144

146

148

142

140

138

134

136

128

132

130

126

118

120

122

114

116

108

110

112

104

106

100

98

102

96

94

92

88

82

80

78

74

76

185

199

2

1

2

1

37

39

61

63

65

67

69

71

4

72

70

68

66

64

62

60

58

56

52

54

50

48

46

42

44

40

38

36

32

34

30

28

26

24

22

20

18

16

14

12

10

8

6

2

57

59

55

53

51

47

49

45

41

43

35

31

33

29

27

25

21

23

19

13

11

9

5

7

1

3

17

15

2

1

2

1

1

2

1

22

1

2

1

2

1

29

29

8

8

8

BI

BIBI

BI

IN

BI

BI

BI

BI

BI

BI

IN

BI

IN

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

IN

BI

BI

IN

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

DQ2

DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1*

DQS1

DQ10

DQ11

DQ17

DQS2*

DQS2

DQ18

DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6

DQ7

DQ12

DQ13

DM1

RESET*

DQ14

DQ15

DQ20

DQ21

DM2

DQ22

DQ23

DQ28

DQ29

DQS3*

DQS3

DQ30

DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

KEY

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42

DQ43

DQ48

DQ49

VSS

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15

A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36

DQ37

VSS

DM4

VSS

VSS

DQ38

DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD

NC

BA2

CK0

VDD

BA0

WE*

A13

S1*

VDD

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54

DQ55

VSS

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS

DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PINMTG PIN

MTG PIN MTG PIN

MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PINMTG PINS

KEY

(2 OF 2)

NC

NC

NC




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Proper APN(s) required elsewhere.

Page Notes

NOTE: J3100 is OMITted on this page.




- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =PPLVDDR_S3_MEM_B

- =I2C_SODIMMB_SDA

Molex: 516s0790Foxconn: 516s0706

Molex: 516s0790Foxconn: 516s0706

- =PPDDRVTT_S0_MEM_B

SPD Addr: 0xA2(Wr)/0xA3(Rd)

DDR3 Plane Stitching Caps (Space evenly across plane split)

"Expansion" (bottom) slot

- =I2C_SODIMMB_SCL

(NONE)

28

28

0.1UF

CERM402

20%10V

C3131

6.3V20%

402-LFCERM

2.2UFC3130 28

28

15 21 70

28

28

28

28

28

28

28

28

15 26

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

28

28

28

28

28

28

28

15 70

28

28

28

28

28

28

28

28

28

28

CERM402

20%10V

0.1UFC3136

2.2UF

CERM402-LF

20%6.3V

C3135

28

28

28

28

28

28

28

28

28

28

28

28

19 26 35

38

38

15 21 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

10K

MF-LF402

5%1/16W

R3141

10K

MF-LF

5%1/16W

402

R31402

1

6.3V20%

402-LFCERM

2.2UFC3140

6.3V20%

X5R

10UF

603

C310010UF

X5R603

20%6.3V

C3101

10V20%

CERM

0.1UF

402

C31102

1402

0.1UF

CERM

20%10V

C31112

1402

0.1UF

CERM

20%10V

C31122

1402

0.1UF

CERM

20%10V

C31132

1402

0.1UF

CERM

20%10V

C31142

1 10V20%

CERM

0.1UF

402

C31152

1 10V20%

CERM

0.1UF

402

C31162

1 10V20%

CERM

0.1UF

402

C31172

1402

0.1UF

CERM

20%10V

C31182

1 10V20%

CERM

0.1UF

402

C31192

1 10V20%

CERM

0.1UF

402

C31202

1 10V20%

CERM

0.1UF

402

C31212

1 10V20%

CERM

0.1UF

402

C31222

1 10V20%

CERM

0.1UF

402

C31232

1

CRITICALOMIT

DDR3-SODIMM

F-RT-BGA3J3100

OMITCRITICAL

F-RT-BGA3

DDR3-SODIMM

J3100

DDR3 SO-DIMM Connector BSYNC_DATE=02/16/2010SYNC_MASTER=T27_MLB

MEM_B_CKE<0>

=PPLVDDR_S3_MEM_B

=PPDDRVTT_S0_MEM_B

MEM_B_BA<1>

MEM_B_CS_L<0>

=PPSPD_S0_MEM_B

MEM_B_A<12>

MEM_B_CKE<1>

MEM_B_A<15>MEM_B_A<14>




MEM_B_CLK_N<1>MEM_B_CLK_P<1>

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_ODT<1>

=I2C_SODIMMB_SDAMEM_EVENT_L

=I2C_SODIMMB_SCL

MEM_B_BA<2>

MEM_B_A<9>



MEM_B_CLK_P<0>MEM_B_CLK_N<0>

MEM_B_A<10>MEM_B_BA<0>

MEM_B_WE_LMEM_B_CAS_L

MEM_B_CS_L<1>MEM_B_A<13>

MEM_B_SA<0>

MEM_B_SA<1>

=MEM_B_DQ<59>=MEM_B_DQ<58>


=MEM_B_DM<7>


=MEM_B_DQS_N<6>=MEM_B_DQS_P<6>


=MEM_B_DQ<43>

=MEM_B_DM<5>

=MEM_B_DQS_P<4>

=MEM_B_DQ<35>

=MEM_B_DQ<40>

=MEM_B_DQ<34>


=MEM_B_DQS_N<4>

=MEM_B_DQ<41>

=MEM_B_DQ<42>

=MEM_B_DQ<39>


=MEM_B_DM<4>

=MEM_B_DQ<38>





=MEM_B_DM<6>

=MEM_B_DQ<54>


=MEM_B_DQS_P<7>=MEM_B_DQS_N<7>


=MEM_B_DQ<55>

PPVREF_S3_MEM_VREFDQ_B


=MEM_B_DM<3>






=MEM_B_DQS_P<1>



=MEM_B_DM<0>


PPVREF_S3_MEM_VREFCA_B

=MEM_B_DQS_N<1>





=MEM_B_DM<2>

MEM_RESET_L=MEM_B_DM<1>







31 OF 109

C.0.0

051-8561

27 OF 76

2

1

2

1

2

1

2

1

1

22

1

2

1

2

1

15

17

3

1

7

5

9

11

13

19

23

21

25

27

29

33

31

35

43

41

45

49

47

51

53

55

59

57

2

6

8

10

12

14

16

18

20

22

24

26

28

30

34

32

36

38

40

44

42

46

48

50

54

52

56

58

60

62

64

66

68

70

72

4

71

69

67

65

63

61

39

37

99

97

95

93

91

89

87

85

81

83

161

157

159

163

165

167

151

149

135

153

76

74

78

80

82

84

86

90

88

92

96

102

98

100

106

104

112

110

108

116

114

122

120

118

126

124

130

132

128

136

134

138

140

142

148

146

144

152

150

73

75

77

79

101

111

109

113

119

121

117

123

125

131

129

133

141

147

145

158

156

154

162

160

164

168

166

172

170

174

176

178

184

182

180

188

186

194

190

192

198

196

204

202

200

155

171

169

173

177

175

107

105

103

143

139

137

127

115

94

187

185

181

208207

209 210

211 212

206

179

183

203

201

197

191

189

193

195

199

205

8

8

8

29

29

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

HOST PARTITION A 2 -> SO-DIMM A 3


Host Partition A 4 -> SO-DIMM A 4


Host Partition A 6 -> SO-DIMM A 6 Host Partition B 6 -> SO-DIMM B 6

Host Partition B 1 -> SO-DIMM B 2




Host Partition B 7 -> SO-DIMM B 7Host Partition A 7 -> SO-DIMM A 7





15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

26

26

26

26

26

26

26

26

26

26

26

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

26

26

26

26

26

26

15 70

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

15 70

15 70

15 70

15 70

15 70

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

15 70

27

27

27

27

27

27

15 70

15 70

15 70

15 70

15 70

15 70

27

27

27

27

15 70

15 70

15 70

15 70

27

27

27

27

27

27

15 70

15 70

15 70

15 70

15 70

15 70

15 70

27

27

27

27

27

15 70

15 70

15 70

15 70

15 70

27

27

27

15 70

27

27

27

15 70

15 70

15 70

15 70

15 70

27

27

15 70

27

27

27

27

15 70

15 70

15 70

15 70

15 70

15 70

15 70

27

27

27

27

27

15 70

15 70

15 70

15 70

15 70

15 70

15 70

27

27

27

27

27

27

15 70

15 70

15 70

15 70

15 70

15 70

15 70

27

27

27

27

27

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

SO-DIMM PinswapsSYNC_MASTER=MASTER SYNC_DATE=MASTER

MAKE_BASE=TRUEMEM_A_DQ<23> MAKE_BASE=TRUEMEM_A_DQ<22>

MAKE_BASE=TRUEMEM_A_DQ<20>

=MEM_A_DQ<31>

MAKE_BASE=TRUEMEM_A_DQ<19> MAKE_BASE=TRUEMEM_A_DQ<18>

MEM_A_DM<2>MAKE_BASE=TRUE


=MEM_A_DQ<21>

=MEM_A_DQ<23>MEM_A_DQ<26>MAKE_BASE=TRUE



MAKE_BASE=TRUEMEM_A_DM<3> MAKE_BASE=TRUEMEM_A_DQS_N<3>

MEM_A_DQ<17>MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQS_P<2>


MEM_A_DQS_N<2>MAKE_BASE=TRUE

=MEM_A_DQ<9>


MAKE_BASE=TRUEMEM_A_DQS_P<3> =MEM_A_DQS_P<2>

=MEM_A_DQ<25>MAKE_BASE=TRUEMEM_A_DQ<21>


=MEM_A_DQ<28>

=MEM_A_DQ<30>

=MEM_A_DQ<29>

=MEM_A_DQ<26>

=MEM_A_DQ<14>



=MEM_A_DQ<17>

=MEM_A_DQ<35>

=MEM_A_DQ<33>

=MEM_A_DQ<19>



=MEM_A_DM<1>


=MEM_A_DQ<7>

=MEM_A_DQ<55>

=MEM_B_DQS_P<0>

=MEM_B_DM<0>=MEM_B_DQS_N<0>



=MEM_B_DQ<4>


=MEM_B_DQ<7>

=MEM_B_DM<2>=MEM_B_DQS_N<2>=MEM_B_DQS_P<2>



=MEM_B_DQ<21>


MAKE_BASE=TRUEMEM_B_DQS_P<0>

MAKE_BASE=TRUEMEM_B_DQS_N<0>MEM_B_DM<0>

MAKE_BASE=TRUE

MEM_B_DQ<2>MAKE_BASE=TRUEMEM_B_DQ<3>MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQ<1>MEM_B_DQ<0>

MAKE_BASE=TRUE

MEM_B_DQ<4>MAKE_BASE=TRUEMEM_B_DQ<5>MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQ<6>MEM_B_DQ<7>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQ<8>



MAKE_BASE=TRUEMEM_B_DQS_N<1>

MAKE_BASE=TRUEMEM_B_DM<1>





=MEM_B_DQ<18>


=MEM_B_DM<3>



=MEM_B_DQ<27>=MEM_B_DQ<24>=MEM_B_DQ<28>

=MEM_B_DQ<31>


=MEM_B_DM<1>




=MEM_B_DQ<10>

=MEM_B_DQS_N<4>=MEM_B_DM<4>

=MEM_B_DQ<32>




MAKE_BASE=TRUEMEM_B_DQS_N<2> MAKE_BASE=TRUEMEM_B_DQS_P<2>







MAKE_BASE=TRUEMEM_B_DQ<21> MAKE_BASE=TRUEMEM_B_DQ<20>


MEM_B_DQ<24>MAKE_BASE=TRUE




MEM_B_DQ<26>MAKE_BASE=TRUE














=MEM_B_DQ<41>

=MEM_B_DM<5>


=MEM_B_DQ<42>




=MEM_B_DQ<52>

=MEM_B_DM<6>


=MEM_B_DQ<51>



=MEM_B_DQS_P<7>=MEM_B_DQS_N<7>=MEM_B_DM<7>

=MEM_B_DQ<56>



















MAKE_BASE=TRUEMEM_B_DQ<55> MAKE_BASE=TRUEMEM_B_DQ<54> MAKE_BASE=TRUEMEM_B_DQ<53> MAKE_BASE=TRUEMEM_B_DQ<52> MAKE_BASE=TRUEMEM_B_DQ<51>


MAKE_BASE=TRUEMEM_B_DQS_N<7> MAKE_BASE=TRUEMEM_B_DQS_P<7>







MAKE_BASE=TRUEMEM_B_DQ<63>MEM_A_DQ<63>

MAKE_BASE=TRUE










MEM_A_DQS_P<7>MAKE_BASE=TRUE





































=MEM_A_DQ<62>

=MEM_A_DQ<60>

=MEM_A_DQ<63>



=MEM_A_DQS_N<7>

=MEM_A_DQ<61>

=MEM_A_DQ<53>

=MEM_A_DQS_P<7>

=MEM_A_DM<7>



=MEM_A_DQ<52>

=MEM_A_DM<6>=MEM_A_DQS_N<6>=MEM_A_DQS_P<6>


=MEM_A_DQ<40>

=MEM_A_DQ<41>

=MEM_A_DQ<42>


=MEM_A_DM<5>


=MEM_A_DQ<45>




=MEM_A_DM<4>

=MEM_A_DQ<16>


=MEM_A_DQ<20>








MAKE_BASE=TRUEMEM_A_DQS_N<0> MAKE_BASE=TRUEMEM_A_DQS_P<0>


=MEM_A_DQ<13>

=MEM_A_DQ<8>


=MEM_A_DQ<12>



=MEM_A_DQ<1>=MEM_A_DQ<0>=MEM_A_DM<0>



=MEM_A_DM<2>

MAKE_BASE=TRUEMEM_B_DQ<15> MAKE_BASE=TRUEMEM_B_DQ<14>=MEM_A_DQ<11>

=MEM_A_DQ<27>


=MEM_A_DQS_N<2>

=MEM_A_DM<3>

=MEM_A_DQ<24>




=MEM_B_DQ<11>

=MEM_B_DQS_P<4>



MAKE_BASE=TRUEMEM_A_DQ<11> MAKE_BASE=TRUEMEM_A_DQ<10> MAKE_BASE=TRUEMEM_A_DQ<9> MAKE_BASE=TRUEMEM_A_DQ<8>


MAKE_BASE=TRUEMEM_A_DQS_N<1>

32 OF 109

C.0.0

051-8561

28 OF 76

OUT

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

IN

NC

RESET*

A0

A1

A2

SCL

SDA

P0

P1

P2

P5

P6

P7

P3

P4

THRM

VCC

GNDPAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTASCL

SDA

A0

A1

GND

IN

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1


7.69mV / step @ output+3.4mA - -3.4mA (- = sourced)

0.300V - 1.200V (+/- 450mV) 0.75V (DAC: 0x3A)

9.24mV / step @ output

0.000V - 1.191V (0x00 - 0x5C)0.200V - 1.050V (+/- 500mV) 0.7V (DAC: 0x8B)

CPU GTLREF (FSB)

7

10mA max load




Page Notes

- =PPVTT_S3_DDR_BUF

Circuitry.

Circuitry.

- =I2C_PCA9557D_SDA- =I2C_PCA9557D_SCL- =I2C_VREFDACS_SDA- =I2C_VREFDACS_SCL

- =PP3V3_S3_VREFMRGN

C4

MEM A VREF CA

3C

0.000V - 1.501V (0x00 - 0x74)

MEM B VREF DQ

A1 2

B

MEM A VREF DQ

Margined target:

VRef current:DAC step size:

Nominal value

DAC range:

PCA9557D Pin:DAC Channel: D

5

MEM VREG

8.59mV / step @ output

1.998V - 1.002V (+/- 498mV)0.000V - 1.501V (0x00 - 0x74)

buffers at once or VRef source may be overloaded.NOTE: Must not enable more than two SO-DIMM margining

MEM B VREF CA

1.5V (DAC: 0x3A)

D

+33uA - -33uA (- = sourced) +750uA - -528uA (- = sourced)

soft-resets and sleep/wake cycles.

Addr=0x30(WR)/0x31(RD)

RST* on ’platform reset’ so that system

NOTE: Margining will be disabled across all

watchdog will disable margining.

(OD)

Addr=0x98(WR)/0x99(RD)

both at the same time!

NOTE: MEMVREG and FRAMEBUF share a DAC output, cannot enable

Required zero ohm resistors when no VREF margining circuit stuffed

(RSVD for FBVREF)

VREFMRGN:YES - Stuffs VREF Margining

VREFMRGN:NO - Bypasses VREF Margining

57

VREFMRGN:YES

10V20%

402CERM

0.1UFC3310

22.6K

1/16W1%

402MF-LF

PLACE_NEAR=R7320.2:1mm

VREFMRGN:YES

R3342

VREFMRGN:YES

100K5%1/16WMF-LF402

R3340

VREFMRGN:YES

100K

402MF-LF1/16W5%

R3345

10 69

MF-LF402

1%1/16W


267

VREFMRGN:YES

R3344

UCSPMAX4253

VREFMRGN:YES

U3320B1

B4

MAX4253UCSP

VREFMRGN:YES

U3330B1

B4

UCSPMAX4253

VREFMRGN:YES

U3320B1

B4

MAX4253UCSP

VREFMRGN:YES

U3330B1

B4

MAX4253UCSP

VREFMRGN:YES

U3340B1

B4

MAX4253UCSP

VREFMRGN:YES

U3340B1

B4

PLACE_NEAR=J2900.126:2.54mm

1/16W1%

402MF-LF

200

VREFMRGN:YES

R3331

PLACE_NEAR=J3100.126:2.54mm200

MF-LF402

1%1/16W

VREFMRGN:YES

R3333

OMIT

NONENONE

402NONE

SHORTR3300

NONE

402NONE

SHORT

NONE

OMIT

R3310

25

200

MF-LF402

1%1/16W


VREFMRGN:YES

R3321

PLACE_NEAR=R3321.2:1mm1%1/16W

133

402MF-LF

VREFMRGN:YES

R3322

200

MF-LF402

1%1/16W


VREFMRGN:YES

R3323


133

1/16W1%

MF-LF402

VREFMRGN:YES

R3324

5%1/16WMF-LF402

100K

VREFMRGN:YESR3325

VREFMRGN:YES

402

100K5%1/16WMF-LF

R33201

2


133

MF-LF

1%1/16W

402

VREFMRGN:YES

R3332

VREFMRGN:YES

100K5%1/16WMF-LF402

R3330

VREFMRGN:YESCRITICAL

QFNPCA9557U3310

10V20%

402CERM

0.1UF

VREFMRGN:YESC3330


133

MF-LF402

1%1/16W

VREFMRGN:YES

R3334

VREFMRGN:YES

5%100K1/16W

402MF-LF

R3335

38

38

VREFMRGN:YESCRITICAL

MSOP

DAC5574

U3300

38

38

VREFMRGN:YES

0.1UF

CERM402

20%10V

C3301VREFMRGN:YES

2.2UF

CERM402-LF

20%6.3V

C3300

0.1UF

CERM402

10V20%

VREFMRGN:YESC3340

0.1UF10V20%

CERM402

VREFMRGN:YESC3320


FSB/DDR3 Vref Margining

VREFMRGN:NO2 RES,MTL FILM,0,5%,0402,SM,LF116S0004 CRITICALR3331,R3333

VREFMRGN:NOR3321,R33232 RES,MTL FILM,0,5%,0402,SM,LF116S0004 CRITICAL

VOLTAGE=0.75V


PPVREF_S3_MEM_VREFDQ_A



PPVREF_S3_MEM_VREFDQ_B

VOLTAGE=0.75VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPPVREF_S3_MEM_VREFCA_A

VOLTAGE=0.75VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPPVREF_S3_MEM_VREFCA_B

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_BUF

=PPVTT_S3_DDR_BUF

VREFMRGN_CA_SODIMMB_BUF

PCA9557D_RESET_L

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_SODIMMS_CA

VREFMRGN_SODIMMB_DQ

VREFMRGN_CPUGTLREF_EN

VREFMRGN_MEMVREG_ENVREFMRGN_CA_SODIMMB_ENVREFMRGN_CA_SODIMMA_ENVREFMRGN_DQ_SODIMMB_ENVREFMRGN_DQ_SODIMMA_EN

=I2C_PCA9557D_SCL=I2C_PCA9557D_SDA

VREFMRGN_SODIMMA_DQ=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

VREFMRGN_MEMVREG_BUF

VREFMRGN_CPUGTLREF_BUF

DDRREG_FB

CPU_GTLREF

=PP3V3_S3_VREFMRGN

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP3V3_S3_VREFMRGN_CTRL

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP3V3_S3_VREFMRGN_DAC

33 OF 109

C.0.0

051-8561

29 OF 76

2

1

1 2

1

2

1

2

1 2

C4

C1

C3

C2

A4

A1

A3

A2

A4

A1

A3

A2

C4

C1

C3

C2

A4

A1

A3

A2

C4

C1

C3

C2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1 2

1

2

15

3

4

5

1

2

6

7

9

12

13

14

16

10

11

17 8

2

1

1 2

1

2

8

3

5

4

2

16

7

9

10

2

1

2

1

2

1

2

1 26

27

26

27

8 57

8

OUT

IN

IN

IN

IN

IN

BI

BI

SYM_VER-1

SYM_VER-1

NCNC

OUT

OUT

OUT

OUT

SG

D

IN

IN

OUT

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE +-

PAD

(OD)

0.7V

DLY




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1


DLY = 60 ms +/- 20%

DO NOT SYNC WITH K84. CHANGED MINI_RESET_CONN_L CIRCUIT FROM SCHMITT TRIGGER TO SLG PART COPIED FROM K69. R3453 IS DIFFERENT FROM K6

BLUETOOTH

155S0367

CHANNEL

RDS(ON)

MOSFET

3V S3 WLAN FET

TPCP8102

P-TYPE

0.727 A (EDP)

20-30 MOHM @2.5V

(AP_CLKREQ_Q_L)

516S0582

(AP_RESET_CONN_L)

606 MA NOMINAL MAX727 MA PEAK

LOADING

Supervisor & CLKREQ# Isolation

AIRPORT

7 16

62

C3430

0.1uF

PLACE_NEAR=J3401.17:2MM

X5R 40210% 16V

9

9

C3431PLACE_NEAR=J3401.15:2MM

0.1uF

16V10% 402X5R

9

9

C3421

10V20%

402CERM

0.1uF

PLACE_NEAR=Q3450.5:2MM

18 72

18 72

10V20%

805X5R

10UF

PLACE_NEAR=Q3450.7:2MM

C3420

L3401DLP11S

90-OHM-100MAPLACE_NEAR=J3401.11:2MM

CRITICAL

L3403CRITICAL

PLACE_NEAR=J3401.23:2MM90-OHMDLP0NS

7 9 75

7 9 75

R3452

SENS_R:ENGCRITICAL

0.002

MF1206

1%1/4W

46 75

46 75

L3404

0603

FERR-120-OHM-3A

C3432

402

10%16VCERM

0.01UF

PLACE_NEAR=L3406.1:2MM

L3406

0402-LFPLACE_NEAR=J3401.27:2MM

FERR-120-OHM-1.5A

J3401CRITICAL

F-ST-SM500913-0302

TPCP810223V1K-SM

Q3450CRITICAL

25

19 62

16

0.1uF

CERM402

20%10V

C3440232K

MF-LF402

1%1/16W

R3453

1/16W5%

402

100K

MF-LF

R3440

TDFNSLG4AP016V

CRITICAL

U3440

1%100K1/16WMF-LF402

R3454

C3450

16V10%

402X5R

0.1UF

C34510.033UF

X5R402

10%16V

R345033K

MF-LF402

5%1/16W

R345110K1/16W5%

402MF-LF

C34220.1uF

CERM

20%10VPLACE_NEAR=J3401.29:2MM

402


X16 WIRELESS CONNECTOR

SENS_R:PRODRES,0OHM,5%,1/4W,MF-LF,1206101S0245 1 R3452

AP_CLKREQ_Q_L

P3V3WLAN_VMON

ISNS_AIRPORT_N

ISNS_AIRPORT_P

AP_RESET_CONN_L

PP3V3_WLAN_F

AP_RESET_L

PP3V3_WLAN_FMIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.5 mmVOLTAGE=3.3V

PM_WLAN_EN_LP3V3WLAN_SS

=PP3V3_S3_WLAN

USB_BT_N

PCIE_CLK100M_MINI_CONN_N

CONN_USB2_BT_N

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP3V3_S3_BT_F

USB_BT_P

PCIE_WAKE_L

PCIE_CLK100M_MINI_N

CONN_USB2_BT_P

PCIE_CLK100M_MINI_P

CONN_PCIE_MINI_D2R_P

CONN_PCIE_MINI_D2R_N

CONN_PCIE_MINI_R2D_P

CONN_PCIE_MINI_R2D_N

PCIE_CLK100M_MINI_CONN_P

=PP3V3_S3_BT

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

VOLTAGE=3.3VMIN_NECK_WIDTH=0.5 mmMIN_LINE_WIDTH=1 mmPP3V3_WLAN_RPP3V3_WLAN

MIN_NECK_WIDTH=0.5 mmVOLTAGE=3.3V

MIN_LINE_WIDTH=1 mm

=PP3V3_S3_WLAN

AP_CLKREQ_LAP_PWR_EN

34 OF 109

C.0.0

051-8561

30 OF 76

1 2

1 2

2

1

2

1

4 3

1 2

4 3

1 2

43

2121

2

1

2 1

4

6

8

10

12

7

5

1

3

11

9

22

24

26

28 27

25

23

21

29

14

16

18

20

17

15

19

13

30

2

3132

3334

78

56

4

31

2

2

11

2

1

2

4

8

6

3

59

7

1

2

1

2

1 2

2

1

1 2

1

2

2

1

7

7

30 46

30 46

8 30

7 75

7 75

7

7 75

7 9 75

7 9 75

7 75

8

7

8 30

IN

IN

IN

IN

IN

IN

BI

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

DVDD33

VDDREG

REGOUT

MDI-[0]

RXD[2]/AN0

LED0/PHYAD0

LED2/RXDLY

LED1/PHYAD1

MDI-[3]

RXD[1]/TXDLY

RXD[3]/AN1

MDI-[1]

MDI+[1]

MDI+[3]

MDI+[2]

MDI-[2]

RXCTL

MDC

PHYRSTB*

RSET

CLK125

CKXTAL2

CKXTAL1

MDI+[0]

RXD[0]

GND

MDIO

RXC

TXCTL

AVDD10

DVDD10

ENSWREG

TXD[3]

TXD[2]

TXD[1]

TXD[0]

TXC

AVDD33

FB10

LED

RESET

CLOCK

MANAGEMENT

MEDIA DEPENDENT

RGMII/MII

REFERENCE

OUTIN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Reserved for EMI

HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.

DO NOT SYNC, EXTERNAL 1.05V REGULATOR OPTION

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

RTL8211 25MHz Clock

(19mA typ - Energy Detect)

Alias to =PP3V3_ENET_PHY for internal switcher.

(43mA typ - 1000base-T)

( 7mA typ - Energy Detect)

(221mA typ - 1000base-T)

Alias to GND for external 1.05V supply.

If internal switcher is used, must place 1x 22uF &1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

If internal switcher is not used, VDDREG and REGOUT can float.of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.If internal switcher is used, must place inductor within 5mm

per RealTek request.

NOTE: MCP89 CAN PROVIDE 25MHZ CLOCK, BUT CLOCK RUNS WHENEVER RMGT RAILS ARE POWERED.

Configuration Settings:PHYAD = 01 (PHY Address 00001)AN[1:0] = 11 (Full auto-negotiation)RXDLY = 0 (RXCLK transitions with data)TXDLY = 0 (No TXCLK Delay)

ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.

WF: Marvell numbers, update for Realtek

WF: Marvell numbers, update for Realtek

R37240

MF-LF402

5%1/16W

CERM402

20%10V

NO STUFFC37250.1UF

R37302.49K

MF-LF402

1%1/16W

R37254.7K

MF-LF402

5%1/16W

NO STUFFR3720

10K

MF-LF402

5%1/16W

L37050402-LFFERR-120-OHM-1.5A

CRITICAL

C37050.1UF

X5R402

10%16V

PLACE_NEAR=U3700.6:1.5 MM

C3706PLACE_NEAR=U3700.41:1.5 MM

0.1UF

X5R402

10%16V

C37000.1UF

X5R402

10%16V



0.1UF

X5R402

10%16V

C3702


0.1UF

X5R402

10%16V

9 73

9 73

9 73

9 73

9 73

9 73

18 73

9 73

31 73

32 73

32 73

32 73

32 73

32 73

32 73

32 73

32 73

18 73

18 73

18 73

18 73

18 73

18 73

R37554.7K

MF-LF402

5%1/16W

4.7KR3756

MF-LF402

5%1/16W

9

MF-LF

R37524.7K

402

5%1/16W

R37574.7K

MF-LF402

5%1/16W

R37504.7K

MF-LF402

5%1/16W

R37514.7K

MF-LF402

5%1/16W

X5R

10%6.3V

402

C37152.2UF


0.1UF

X5R402

16V10%

C3716

L3715

PLACE_NEAR=U3700.28:5 MMPLACE_NEAR=U3700.36:5 MM

CRITICAL

FERR-120-OHM-1.5A0402-LF


0.1UF

X5R402

10%16V


0.1UF

X5R402

10%16V

C37142.2UF

X5R402

10%6.3V

C3790NO STUFF

10PF

CERM402

5%50V

R37960

MF-LF4021/16W5%

9 73

U3700RTL8251CA-VB-GR

TQFP

CRITICAL

31 73

R3746

PLACEMENT_NOTE=Place close to U1400

22

MF-LF402

5%1/16W

9 73

ENET1V05:INT

PLACE_NEAR=L3720.2:5 MM

C372022UF

CERM-X5R805

20%6.3V

C3722

PLACE_NEAR=U3700.44:5 MM

22UF

CERM-X5R805

20%6.3V

ENET1V05:INT

C37230.1UF

X5R402

10%16V

PLACE_NEAR=U3700.45:5 MMENET1V05:INT

ENET1V05:INT

C3721


0.1UF

X5R402

10%16V

ENET1V05:INTL3720

4.7UH-0.91A

PLE031B-SM

CRITICAL


R3721

PLACE_NEAR=C3721.1:3 MM

0 MF-LF402 5% 1/16W

ENET1V05:INT

R37220

MF-LF402

5%1/16W

ENET1V05:EXT

R3731

402MF-LF1/16W5%22

R3790 0402MF-LF1/16W5%

MF-LF1/16W5%0

402R3791

MF-LF1/16W5%0

402R3792

MF-LF1/16W5%0

402R3793

MF-LF1/16W5%0

402R3794

05% 1/16W MF-LF 402

R3795


Ethernet PHY (RTL8211CL)

=RTL8211_REGOUT

ENET_RXD<2>

DIDT=TRUE

RTL8211_REGOUT_L

VOLTAGE=1.05V


ENET_CLK125M_RXCLK

=PP3V3_ENET_PHY

RTL8211_PHYAD0

ENET_MDI_N<0>

RTL8211_PHYAD1

ENET_MDI_N<2>ENET_MDI_P<2>

ENET_MDI_N<1>

PP1V05_ENET_PHYAVDDMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

=PP3V3_ENET_PHY_VDDREG

ENET_CLK125M_TXCLK_R

RTL8211_PHYRST_L

ENET_MDIO

RTL8211_CLK125

MCP_CLK25M_BUF0_R

RTL8211_CLK25M_CKXTAL1

ENET_TX_CTRL

ENET_MDI_P<0>ENET_MDC

ENET_TXD<3>ENET_TXD<2>

ENET_RESET_L

ENET_TXD<1>ENET_TXD<0>

=RTL8211_ENSWREG

ENET_MDI_P<3>

RTL8211_CLK25M_CKXTAL1

RTL8211_RXDLY

=PP1V05_ENET_PHY

RTL8211_RSET

ENET_MDI_N<3>

ENET_MDI_P<1>

PP3V3_ENET_PHYAVDD

VOLTAGE=3.3V


ENET_CLK125M_TXCLK

PP1V05_ENET_PHYAVDD_R

VOLTAGE=1.05V


TP_RTL8211_CKXTAL2

ENET_CLK125M_RXCLK_R

ENET_RXD<0>ENET_RXD_R<0>ENET_RXD<1>ENET_RXD_R<1>

ENET_RXD_R<2>ENET_RXD<3>ENET_RXD_R<3>

ENET_RX_CTRLENET_RXCTL_R

37 OF 109

C.0.0

051-8561

31 OF 76

1 2

2

1

1

2

1

2

1

2

1

2

2

1

2

1

2

1

2

1

2

1

1

2

1

2

1

2

1

2

1

2

1

2

2

1

2

1

1

2

2

1

2

1

2

1

2

1

1 2

15

21

37

44

45

48

2

17

34

38

35

12

16

18

41

5

4

11

8

9

13

30

29

46

32

43

42

1

14

20

33

477

31

19

27

40

10

36

28

39

26

25

24

23

22

6 3

1 2

2

1

2

1

2

1

2

1

21

1 2

1

2

1

2

1 2

1 2

1 2

1 2

1 2

1 2

8

8 9

8

73

8

73

73

73

73

73

73

BI

BI

BI

BI

BI

BI

BI

BI

IO

NC

NC

IO

NC

IO

IO

NC

GND

IO

NC

NC

IO

NC

IO

IO

NC

GND

PINSSHIELD

TRAN_N0

TRAN_N3

TRAN_P3

TRAN_N1

TRAN_N2

TRAN_P2

TRAN_P1

TRAN_P0ENET_MDI

RX

TX

RX

TX




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

ETHERNET CONNECTOR

514-0704

mirrored on opposite

DO NOT SYNC FROM K6, WITH K84’S CONNECTOR

sides of the board

- COPY THIS PAGE FROM K36 CSA.39

D3900.1:D3900.5:

D3901.1:D3901.5:

Transformers should be

ENET_MDI_x<1> pinswapped for layout

31 73

31 73

31 73

31 73

31 73

31 73

31 73

31 73

3

D3901 PLACE_NEAR=T3901.2:4 MM

CRITICAL

SLP2510P8

ENET_ESD

RCLAMP0524P

PLACE_NEAR=T3902.6:4 MM

3

D3900


ENET_ESDCRITICAL

RCLAMP0524PSLP2510P8


J3900F-R-TH1

RJ45-10/100TX-K83

CRITICAL

0.1UFC3902

X5R16V

402

10%

PLACE_NEAR=T3901.3:2.54 MM

C3900

X5R

10%

402

16V

0.1UF


C390110%16VX5R

0.1UF

402


C390310%

X5R16V

402

0.1UF


1/16W

R390075

MF-LF1% 402

R39011% 1/16W MF-LF 402

75

R39021% 1/16W 402MF-LF

75

R39034021/16W

751% MF-LF

1206

C39101000PF10%2KV

CRITICAL

CERM

TLA-6T213HF

T3902CRITICAL

SM

T3901SM

CRITICAL

TLA-6T213HF


ETHERNET CONNECTOR

ENET_MDI_TRAN_P<2>

ENET_CENTER_TAP<2>

ENET_CENTER_TAP<1>


ENET_BOB_SMITH_CAPMIN_LINE_WIDTH=0.6MM

ENET_MDI_P<0>

ENET_MDI_N<2>

ENET_MDI_N<3>

ENET_MDI_P<3>

ENET_MDI_P<2>

ENET_MDI_TRAN_P<3>

ENET_CENTER_TAP<3>

ENET_MDI_N<0>

ENET_CENTER_TAP<0>

ENET_MDI_TRAN_N<2>

ENET_CONN_CTAP

ENET_MDI_N<1>

ENET_MDI_P<1> ENET_MDI_TRAN_P<1>

ENET_MDI_TRAN_N<1>

ENET_MDI_TRAN_N<3>

ENET_MDI_TRAN_N<0>

ENET_MDI_TRAN_P<0>

39 OF 109

C.0.0

051-8561

32 OF 76

1102945 761102945 76

1

2

3

5

6

8

4

7

10

9

11

12

2

1

2

1

2

1

2

1

1 2

1 2

1 2

1 2

2

1

1

3

2

12

11

9

8

7

4

5

6

10

1

3

2

12

11

9

8

7

4

5

6

10

73

73

73

73

73

73

73

73

OUT

OUT

OUT

OUT

SG

D

NC

OUT

OUT

IN

IN

OUT

SYM_VER-1

IN

SYM_VER-1

SYM_VER-1

OUT

OUT

IN

IN

D

SG

D

SG

SYM_VER-1





36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Use 0-ohm resistors and NOSTUFF caps if not using

516S0616

SATA HDD

516S0616

ODD Power Control

Indicates disc presence

PLACEMENT_NOTE: Place R4585,R4586,C4585,C4586 on the same side.

Resistors should be on inside, with SATA passing straight through.

Passive de-emphasis filter

SATA ODD

NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.

518S0519

SIL

R45314.7

MF-LF

4025% 1/16W

C4531

10%50V

0.001UF

402CERM

M-RT-SM

CRITICAL

78171-0002J4502

F-ST-SM54722-0164

CRITICAL

J4501

1206MF

1/4W1%

0.002

SENS_R:ENG CRITICAL

R4598

1206

1/4W1%

0.002

CRITICAL

MF

R4599

SENS_R:ENG

46 75

46 75

46 75

46 75

23V1K-SM

TPCP8102

CRITICALQ4590

18 71

18 71

18 71

18 71

7 35

5%

402

1/16W

33K

MF-LF

R4590

CRITICAL

90-OHM-100MAFL4502

DLP11S

MF-LF1% 1/16W

40227.4

R4586

27.4 1%MF-LF 402

R45851/16W

47PF 5% 50VCERM

C4586402

5% 50V402CERM47PF

C4585

FERR-1000-OHML4530

0402

FERR-1000-OHML4531

0402

19

CRITICAL

DLP11S

FL4520


90-OHM-100MA

90-OHM-100MA

CRITICAL

DLP11S

FL4525


18 71

18 71

18 71

18 71

SSM6N15FEAPESOT563

Q4596

100K5%

1/16WMF-LF

402

R4597

SSM6N15FEAPESOT563

Q4596

100K

MF-LF

5%1/16W

402

R4596

402

5%1/16W

100K

MF-LF

R4595 402CERM

10%0.068UF10V

C4595

402

16V

0.01UF

CERM

10%

C4596

10% 402CERM0.01UF 16V

C4521PLACE_NEAR=C4520:3MM

10%0.01UF 402CERM16V

PLACE_NEAR=U1400.AJ2:3MM

C4520

PLACE_NEAR=FL4525.3:3MM

4020.01UF 16V CERM10%

C4526

PLACE_NEAR=C4526:3MM

0.01UF 10% CERM16V 402

C4525

PLACE_NEAR=J4501.9:3mm

CRITICAL

0603

FERR-70-OHM-4AL4500

CRITICAL

90-OHM-100MADLP11S

FL4501

PLACE_NEAR=L4500.2:2mm

0.1UF

402

20%10VCERM

2

1

C4502

0.01UF 10% 16V CERM

C4516402

402CERM10% 16V

C45100.01UF

0.01UF 16V10% CERM

C4511402

402CERM0.01UF 16V

C451510%

F-ST-SM

CRITICAL

54722-0164J4500

101S0245 SENS_R:PRODRES,0OHM,5%,1/4W,MF-LF,12062 R4599,R4598

SATA ConnectorsSYNC_MASTER=MASTER SYNC_DATE=MASTER

SATA_HDD_D2R_FILT_N SATA_HDD_D2R_N

SATA_HDD_R2D_UF_P

ISNS_HDD_N

ODD_PWR_SS

SATA_ODD_D2R_N

SATA_ODD_R2D_C_P

SATA_ODD_D2R_P

SATA_ODD_R2D_N

=PP3V3_S0_ODD

ODD_PWR_EN_L

ISNS_ODD_P

=PP3V3_S0_ODD

ODD_PWR_EN_LS5V_L

ODD_PWR_EN

SMC_ODD_DETECT

PP5V_SW_ODD_RMIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.4mmVOLTAGE=5V

ISNS_ODD_N

SATA_HDD_R2D_UF_N

SATA_HDD_R2D_P

SATA_HDD_R2D_N

SATA_HDD_D2R_C_N

SATA_HDD_D2R_C_P

ISNS_HDD_P

SATA_ODD_R2D_P

SATA_ODD_D2R_C_N

SATA_ODD_D2R_UF_N

SATA_ODD_D2R_UF_P

=PP5V_S0_HDD

SATA_ODD_R2D_C_N

SATA_HDD_R2D_C_P

VOLTAGE=5VMIN_NECK_WIDTH=0.4mmMIN_LINE_WIDTH=0.6mmPP5V_S0_HDD_R

SATA_HDD_R2D_C_N

SATA_HDD_D2R_UF_P

SATA_HDD_D2R_UF_N

SATA_ODD_R2D_UF_N

PP5V_S0_HDD_FLT

VOLTAGE=5VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6mm

=PP5V_S3_ODD

SATA_ODD_D2R_C_P

SATA_HDD_D2R_PSATA_HDD_D2R_FILT_P

SATA_ODD_R2D_UF_P

MIN_LINE_WIDTH=0.6mmPP5V_SW_ODDMIN_NECK_WIDTH=0.4mmVOLTAGE=5V

SYS_LED_RETURN_UF

SYS_LED_ANODE_UFSYS_LED_ANODE_RSYS_LED_ANODE

45 OF 109

C.0.0

051-8561




PLACE_NEAR=J4501.14:3MMPLACE_NEAR=C4510.1:3MM

PLACE_NEAR=C4516.1:3MM

33 OF 76

12

2

14

21

3

15131197531

161412108642

2

1 3

4

4321

78

56

4

312

1

2

43

12

1 2

1 2

1 2

1 2

21

21

43

12

4 3

1 2

3

45

1

2

6

12

1

2

1 2

2

1

1 2

1 2

1 2

1 2

1 2

21

43

12

1 2

1 2

1 2

1 2

15

13

11

9

7

5

3

1

16

14

12

10

8

6

4

2

75

75

7 71

8 33

8 33

75

7 71

7 71

7 71

7 71

7 71

7 71

75

75

8

75

75

75

7

8

7 71

75

75

7 46

7 36

OUT

BI

BI

SYM_VER-1

IN

OUT

IN

SYM_VER-1

BI

BI

OUT

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

IN

OUT2

TPADGND

OUT1

OC1*

EN2

EN1

OC2*

IN

IO

IO

NC

GND

VBUS

NC

IO

IO

NC

GND

VBUS

NC




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Place L4600 and L4605 at connector pin

U4690.6:U4690.7:

Can NOSTUFF one of C4616 or C4696, BUT NOT BOTH

We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.

CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION

Port Power Switch

We can add protection to 5V if we want, but leaving NC for now

USB/SMC Debug Mux

SEL=1 Choose USBSEL=0 Choose SMC

USB PORT A (FRONT PORT)

USB PORT B (BACK PORT)

D4610.4D4610.5

514-0705

D4600.5D4600.4

514-0705

POR IS METAL USB CONNECTOR PARTS

DO NOT SYNC WITH K84. UPDATED PLACE NEAR NOTESUPDATED SMC_DEBUG BOMOPTION, STUFFED C4690

CRITICAL

USBF-RT-TH-K84

J4610

FERR-220-OHM-2.5A

PLACE_NEAR=J4600.1:3 mm

0603

CRITICAL

L4605

POLY-TANTCASE-B2-SM

100UF

6.3V20%

C4696CRITICAL

603X5R

6.3V

10UF20%

C4695

10V

0.1UF

402CERM

20%

C4691

18

18 72

18 72

SMC_DEBUG:YES

0.1UF

CERM10V

402

20%

C4650

MF-LF402

10K5%1/16W

R4650

PLACE_NEAR=D4600.3:2 mm

90-OHM

CRITICAL

DLP0NS

PLACE_NEAR=D4600.2:2 MM

L4600

35 36 37

35 36 37

35

5%

MF-LF1/16W

SMC_DEBUG:NO

0

402

R4651

MF-LF1/16W5%

402

0

SMC_DEBUG:NO

R4652

20%

402

0.01uF

16VCERM

C4605

0.01uF

CERM

20%16V

402

C4615

FERR-220-OHM-2.5A

PLACE_NEAR=J4610.1:3 MM

0603

CRITICAL

L4615

90-OHM

CRITICAL

DLP0NS

PLACE_NEAR=D4610.3:2 mmPLACE_NEAR=D4610.2:2 MM

L4610

C461710UF20%6.3VX5R603

NOSTUFF

CRITICAL

CASE-B2-SM

C4616100UF20%

POLY-TANT6.3V

18 72

18 72

18

10UF20%

X5R6.3V

603

C4690

CRITICAL

TQFN

SMC_DEBUG:YES

PI3USB102ZLEU4650

62

PLACE_NEAR:J4610.1:3 MM

CRITICAL

TPS2064DGN

MSOP

U4690 PLACE_NEAR:J4600.1:3 MM

RCLAMP0502NSLP1210N6

CRITICAL NOSTUFF

PLACE_NEAR=J4600.2:2 MMPLACE_NEAR=J4600.3:2 MM

D4600

1

6

PLACE_NEAR=J4610.2:2 MMPLACE_NEAR=J4610.3:2 MM

NOSTUFF

RCLAMP0502N

CRITICALSLP1210N6

D4610

1

6

CRITICAL

USBF-RT-TH-K84

J4600

SYNC_DATE=(10/03/2009)

External USB ConnectorsSYNC_MASTER=(K84_MLB)

USB_EXTA_MUXED_P

VOLTAGE=5VMIN_NECK_WIDTH=0.5 mmMIN_LINE_WIDTH=0.5 mmPP5V_S3_RTUSB_B_F

USB_EXTA_MUXED_N

PP5V_S3_RTUSB_B_ILIMMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.5 mmVOLTAGE=5V

USB_EXTA_OC_L

USB_EXTB_OC_L

=PP5V_S3_EXTUSB

=USB_PWR_EN

=PP3V42_G3H_SMCUSBMUX

PP5V_S3_RTUSB_A_ILIMMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.5 mmVOLTAGE=5V

SMC_TX_L

SMC_RX_L

USB_DEBUGPRT_EN_L

USB_EXTB_P

USB_EXTB_N

USB_EXTA_N

USB_EXTA_P

CONN_USB_EXTB_P

CONN_USB_EXTB_N

CONN_USB_EXTA_P

CONN_USB_EXTA_N

VOLTAGE=5VMIN_NECK_WIDTH=0.5 mmMIN_LINE_WIDTH=0.5 mmPP5V_S3_RTUSB_A_F

46 OF 109

C.0.0

051-8561

34 OF 76

1

2

4

3

5

6

7

8

21

1

22

1

2

1

2

11

2

4 3

1 2

1 2

1 2

2

1

2

1

21

4 3

1 2

2

11

22

1

93

108

7

6

1

2

5

4

6

91

7

8

4

3

5

2

2534

2534

1

2

4

3

5

6

7

8

72 75

72 75

8

8

75

75

75

75

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

OUT

BI

IN

IN

OUT

BI

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

BI

BI

BI

BI

BI

BI

OUT

OUT

IN

IN

OUT

ININ

BI

BI

OUT

IN

OUT

OUT

NC

OUT

OUT

OUTNC

NCNCNC

NC

NC

NC

NCNC

NCNCNC

NC

NC

NC

NC

NCNC

NCNC

NC

NCNC

IN

OUT

OUT

P13

P14

P15

P16 P66

P10

P11

P12

P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P36

P37

P40

P41

P42

P43

P44

P45

P46

P47

P50

P51

P52

P60

P61

P62

P63

P64

P65

P67

P70

P71

P72

P73

P74

P75

P76

P77

P80

P81

P84

P85

P86

P90

P91

P92

P93

P94

P95

P96

P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0

PA1

PA2

PA3

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE0

PE1

PE2

PE3

PE4

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PH0

PH1

PH2

PH3

PH4

PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREFAVCC

EXTAL

XTAL

(3 OF 3)

IN

NC

IN

BI

BI

BI

BI

IN

IN

IN

OUT

BI

IN

IN

IN

BI

BI

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating,

(OC)(OC)

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

(OC)

(OC)

(OC)

(OC)(OC)

(DEBUG_SW_2)(DEBUG_SW_1)

(OC)

(OC)(OC)

(OC)(OC)

(OC)

those designated as inputs require pull-ups.

(OC)

(EXCARD_PWR_EN)

(EXCARD_CP)

(EXCARD_OC_L)

(See below)

(SMC_PECI)(SMC_PECI_VREF)(SMC_PECI_VSTP)

H8S2117-R:

SMC_IG_THROTTLE_L for MG systems.

SMC_PB3:

Otherwise, TP/NC okay.

(OC)

(OC)

If SMS interrupt is not used, pull up to SMC rail.

NOTE: P94 and P95 are shorted in some platforms.

6.3V20%

CERM805

22UFC4902

19 37

36 37 55

36 43

6.3V

0.47UF

402

10%

CERM-X5R

BYPASS=U4900.E1:D2:5 mm

C4907

20%

CERM

0.1UF

402

10V

C4903

20%

CERM402

10V

0.1UF

BYPASS=U4900.M12:L9:5 mm

C4920

4.7

5%

MF-LF402


1/16W

R4999

20%

CERM10V

0.1UF

402

C4904

SMXW4900

19

58

20%

CERM

0.1UF10V

402

C4905

19

62

25 62

36

20%0.1UF

402

10VCERM

C4906

40

39

36

36

40

39

40

23

36

9 36 54

34 35 36 37

34 35 36 37

7 62

38

10K

MF-LF

5%1/16W

402

R4909

37

37

MF-LF

10K5%1/16W

402

R4901

1/16W5%

MF-LF

10K

402

R4902NO STUFF

0

MF-LF

5%1/16W

402

R490310K

MF-LF

5%1/16W

402

R4998

34

54

19

7 33

19

42

36

36

36

36

36

36

42

45

45

36

45

36

36

36

36 37

36

36 37

36 37

7 36 37

36 43 54

38

38

38

38

38

38

36

36

36

34 35 36 37

34 35 36 37

36 36

7 19 37

19 26 27

25

37

19

19 37

36

45

19 36 62

36

36

36

OMIT

LGA-HFH8S2117U4900

H8S2117LGA-HF

OMIT

U4900

H8S2117LGA-HF

OMIT

U4900

36

7 19 36 62

19 37 72

19 37 72

19 37 72

19 37 72

19 37 72

25

25 72

9

38

7 19 62 66

19

25 72

38

38

36


SMC

SMC_LID

SMB_B_S0_DATA

SMC_RESET_L


VOLTAGE=3.3V

PP3V3_S5_SMC_AVCCMIN_NECK_WIDTH=0.10 MM

SMC_EXTALSMC_XTAL

GND_SMC_AVSS

SMC_TRST_L

SMC_MD1SMC_KBC_MDE

SMC_NMI

SMC_PA5MEM_EVENT_L

SMC_PA0SMC_PA1

PM_SYSRST_LUSB_DEBUGPRT_EN_L

SYS_ONEWIRE

SMC_RUNTIME_SCI_LSMC_ODD_DETECT

SMC_GFX_OVERTEMP_L

SMC_FAN_2_CTLSMC_FAN_3_CTLSMC_FAN_0_TACHSMC_FAN_1_TACHSMC_FAN_2_TACHSMC_FAN_3_TACH

SMS_X_AXIS

SMC_ANALOG_IDSMC_NB_CORE_ISENSE

SMC_ADC15

SMC_TCK

=SMC_SMS_INTSMB_BSA_DATASMB_BSA_CLKSMB_A_S3_DATASMB_A_S3_CLK

SMC_PROCHOT

RSMRST_PWRGD

SMC_PROCHOT_3_3_L

SMC_RSTGATE_LALL_SYS_PWRGD

SMC_BMON_MUX_SEL

LPC_AD<0>

LPC_FRAME_L

LPC_CLK33M_SMC

SMB_MGMT_DATASMS_ONOFF_L

SMC_GFX_THROTTLE_LSMC_SYS_KBDLED

SMC_RX_LSMB_0_S0_CLK

SMC_PM_G2_EN

SMC_ADAPTER_EN

SMC_BIL_BUTTON_L

SMC_GPU_ISENSE

SMC_RX_LSMB_MGMT_CLK

PM_SLP_S5_LPM_CLK32K_SUSCLKSMB_0_S0_DATA

SMC_TMS

PM_BATLOW_L

SMC_THRMTRIP

SMC_P10

PM_RSMRST_LIMVP_VR_ONPM_PWRBTN_L

SMC_TX_L

SMC_PB6

SMB_B_S0_CLK

SMC_TDISMC_TDO

SMC_SYS_LED

SMC_PB4SMC_PB3

SMC_PH3

PM_SLP_S4_L

SMC_MCP_SAFE_MODE

PM_CLKRUN_L

SMC_BATT_ISENSESMC_PBUS_VSENSESMC_DCIN_ISENSESMC_GPU_VSENSE

SMC_NB_MISC_ISENSE

SMC_WAKE_SCI_L

LPC_PWRDWN_L

PM_SLP_S3_LSMC_BS_ALRT_LSMC_BC_ACOKSMC_ONOFF_L

SMC_CASE_OPEN

SMC_G3H_POWERON_L

SMC_FAN_0_CTLSMC_FAN_1_CTL

SMC_ADC14SMC_NB_DDR_ISENSE

SMS_Z_AXISSMS_Y_AXIS

SMC_P24

SMC_TX_L

LPC_SERIRQ

LPC_AD<1>

SMC_P20

LPC_AD<3>LPC_AD<2>

SMC_P41

SMC_LRESET_L

SMC_VCL

PP3V3_S5_AVREF_SMC=PP3V3_S5_SMC

SMC_CPU_ISENSESMC_CPU_VSENSE

49 OF 109

C.0.0

051-8561

35 OF 76

2

1

2

1

2

1

2

1

1 2

2

1

12

2

1

2

1

1

2

1

2

1

2

1

2

1

2

B13

D11

C13

C12 J11

B12

A13

A12

D10

D13

E11

D12

F11

E13

E12

F13

E10

A9

D9

C8

B7

A8

D7

D6

D4

A5

B4

A1

C2

B2

C1

C3

G2

F3

E4

L13

K12

K11

J12

K13

J10

H12

N10

M11

L10

N11

N12

M13

N13

L12

A7

B6

A6

B5

C6

J4

G3

H2

G1

H4

G4

F4

F1

D8

D5

C7

L1

N2

N3

N1

M3

M2

K3

L2

B8

C9

B9

A10

C10

B10

C11

A11

G11

G13

F12

H13

G10

G12

H11

J13

M10

N9

K10

L8

M9

N8

K9

L7

K1

J3

K2

J1

K4

K5

N5

M6

L5

M5

N4

L4

M4

M8

N7

K8

K7

K6

N6

M7

L6

E2

F2

J2

A4

B3

C4

D3

F10

E3

C5

B11

L3

D2

E1

H10

M1

B1

E5

H1

D1

H3

L9

L11

M12

A2

A3

36

36

23 36 39 40

36

36

36

40

36

36

36

36

36

23

36

36

7 36

8 36

D

S G

IN

OUT

BI

IN

D

S G

IN

IN

IN

IN

IN OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN OUT

OUT

OUT

OUT

OUT

OUT

IN

E

Q2

C

BD

Q1

GS

OUT

G

D

S

OUT

IN

REFOUT

MR1*

THRMGND

RESET*

DELAY

MR2*

VINV+

SN0903048

PAD

IN

IN

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Unused Pins

SMC Aliases

PLACEMENT_NOTEs:

SMC Crystal Circuit

SMC Pull-downs

MR1* and MR2* must both be low to cause manual reset.

Debug Power "Buttons"

R5030,R5031,R5032 CHANGED FOR DIMMER LED

System (Sleep) LED Circuit

Used on mobiles to support SMC reset via keyboard.

TO CPU

SMC FSB to 3.3V Level Shifting

TO SMC

(IPU)

Mobiles: 3.42VDesktops: 5V

(IPU)

NOTE: Internal pull-ups are to VIN, not V+.

SMC Reset "Button", Supervisor & AVREF Supply

Target Current: 7.5 mA

SMC Pull-ups

Q5059SSM6N15FEAPESOT563

R50701/16W5% 402

10KMF-LFR5071

1/16W5% 402MF-LF100K

R5073 10KMF-LF 4025% 1/16WR5074MF-LF 4025% 1/16W

100K

R5076MF-LF 402

100K1/16W5%

R5077 10KMF-LF 4025% 1/16WR5078 10KMF-LF 4025% 1/16WR5079MF-LF

10K4025% 1/16WR5080

MF-LF 4025% 1/16W10K

R5085 10K4025% MF-LF1/16WR5086 10K

MF-LF 4025% 1/16W

R5088 10KMF-LF 4025% 1/16W

R5090 100KMF-LF 4021/16W5%

35

10 14 69

Place R5015 on BOTTOM side

R5015

SILK_PART=PWR_BTN

0

MF-LF603

5%1/10W

OMIT

R5062

1/16W5%

402MF-LF

3.3K10 14 69

35

Q5059SSM6N15FEAPESOT563

R5091 100KMF-LF 4025% 1/16WR5092 100KMF-LF 4025% 1/16W

R5089 10K1/16W5% 402MF-LF

R5081 10KMF-LF 4025% 1/16W

R5010

1/16W

0

402

5%

MF-LF Y50105X3.2-SM

20.00MHZ

CRITICAL

50V

C5011

CERM

15pF

402

5%

C5010

50V5%

402CERM

15pF

R5087 470KMF-LF 4025% 1/16WR5093MF-LF1/16W 402

10K5%

Place R5014 on TOP side

R50145%

SILK_PART=PWR_BTN

0

MF-LF603

1/10W

OMIT

35

35

35

35

35 19

35

35

35

35

35

35

35

35

35

35

R5096

402MF-LF

0

1/16W5%

35 19

35

35

35

R5095MF-LF 4025% 1/16W

10K

R5094 10KMF-LF 4025% 1/16W

35

35

35

R5032

402MF-LF1/16W

5.49K1%

402

R5031

MF-LF1/16W

1.74K1%

402MF-LF

R503066.51/16W1%

DMB54D0UVQ5030SOT-563

33

Q5060DMB53D0UVSOT-563

R5061

402

100K5%1/16WMF-LF

Q5060DMB53D0UVSOT-563

R5060

MF-LF

10K

402

5%1/16W

35

19

U5010

DFN

VREF-3.3V-VDET-3.0V

43

35 36 43

R50005%

402MF-LF1/16W

1K

C5026

16VCERM

0.01UF

402

10%

C5025

6.3V20%

603X5R

10uF

C5001

CERM402

10%16V

0.01UFR5001

SILK_PART=SMC_RST

OMIT

0

MF-LF603

5%1/10W

PLACEMENT_NOTE=Place R5001 on BOTTOM side

35 37 55

C5020

CERM-X5R

0.47UF

402

10%6.3V

35 36

12R5098402

100K5% 1/16W MF-LF

35 36 43

SYNC_DATE=(10/27/2009)

SMC SupportSYNC_MASTER=(T27_MLB)

SMC_P10

SMC_P20

SMC_P41

SMC_PB3

SMC_PH3

SMC_FAN_1_CTLMAKE_BASE=TRUETP_SMC_FAN_1_CTL

MAKE_BASE=TRUETP_SMC_P20MAKE_BASE=TRUETP_SMC_P10

TP_SMC_RSTGATE_LMAKE_BASE=TRUE

SMC_FAN_3_TACH

SMC_FAN_2_TACH

SMC_FAN_3_CTL

SYS_LED_L

TP_SMC_GPU_VSENSEMAKE_BASE=TRUE

SMC_GPU_ISENSE

SMC_GPU_VSENSE

SMC_ANALOG_ID

SMC_IG_THROTTLE_LMAKE_BASE=TRUE

SMC_NB_DDR_ISENSE

TP_SMC_GPU_1V8_ISENSEMAKE_BASE=TRUETP_SMC_GPU_ISENSEMAKE_BASE=TRUE

SMC_NB_CORE_ISENSE

SMC_ADC15

SMC_ADC14

SMS_INT_L

SMC_BIL_BUTTON_L

SMC_TDO

NO_TEST=TRUENC_SMC_FAN_2_TACHMAKE_BASE=TRUE

NO_TEST=TRUENC_SMC_FAN_3_TACHMAKE_BASE=TRUE

SMC_EXTAL

SMC_RX_L

SMC_THRMTRIP

=PP3V3_S5_SMC

=PP3V3_S0_SMC

PM_SLP_S4_L

MCP_SPKR

SYS_LED_ILIM

=PP5V_S3_SYSLED

SYS_LED_L_VDIV

SYS_LED_ANODE

SMC_G3H_POWERON_L

SMC_SYS_LED

SMC_FAN_1_TACH

SMC_RESET_L

PM_THRMTRIP_L

CPU_PROCHOT_L

SMC_PROCHOT

CPU_PROCHOT_L_R

CPU_PROCHOT_BUF

=PP3V3_S0_SMC

SMC_PROCHOT_3_3_L

SMC_ONOFF_L

SMC_XTAL_R

NC_SMC_FAN_2_CTLNO_TEST=TRUEMAKE_BASE=TRUE

SMC_FAN_2_CTL

=PPVIN_S5_SMCVREF

SMC_ONOFF_L

SMC_MANUAL_RST_L

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mmGND_SMC_AVSSMIN_NECK_WIDTH=0.1 mm

SMC_TPAD_RST_L

PP3V3_S5_AVREF_SMCMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.1 mmVOLTAGE=3.3V

NC_SMC_FAN_3_CTLNO_TEST=TRUEMAKE_BASE=TRUE

SMC_MCP_VSENSEMAKE_BASE=TRUESMC_CPU_FSB_ISENSEMAKE_BASE=TRUESMC_MCP_CORE_ISENSEMAKE_BASE=TRUESMC_MCP_DDR_ISENSEMAKE_BASE=TRUE

SMC_BS_ALRT_LSMC_ADAPTER_ENSMC_CASE_OPEN

SMC_PA5

TP_SMC_P41MAKE_BASE=TRUETP_SMC_PB3MAKE_BASE=TRUETP_SMC_PH3MAKE_BASE=TRUE

SMC_RSTGATE_L

SMC_GFX_THROTTLE_L

=SMC_SMS_INTSMS_INT_LMAKE_BASE=TRUE

SMC_G3H_POWERON_LMAKE_BASE=TRUE

MCP_WAKE_REQ_L

SMC_MCP_SAFE_MODE

SMC_TMS

SMC_TDISMC_TCK

SMC_BC_ACOK

SMC_GFX_OVERTEMP_L

SMC_ONOFF_LSMC_LIDSMC_TX_L

SMC_PA0SMC_PA1SMC_PB4SMC_PB6

=PP3V3_S5_SMC

SMC_XTAL

TP_SMC_FAN_1_TACHMAKE_BASE=TRUE

50 OF 109

C.0.0

051-8561

36 OF 76

3

4 5

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1 2

6

1 2

1 2

1 2

1 2

1 2

1 2

2

1

1 2

1 2

1 2

1 2

1

2

1 2

1 2

1 2

1

2

1

2

1

2

1 2 3

5 46

4

5

3

1

2

6

2

1

1

2

8

6

92

5

4

7

31 1

2

2

1

2

1

2

11

2

2

1

36

35

35 37 35

34 35 37

8 35 36

8 36

7 19 35 62

8

35 36

8 36

8

23 35 39 40

7 35

39

40

40

40

35

19 35 62

35

35

35 36

7 35 37

35 37

35 37

9 35 54

35

35 36 43

35 43 54

34 35 37

35

35

35

35

8 35 36

35

OUTIN

E0/NC0

SCL

SDAE2

E1

WC*

VCC

VSS

IN

BI

NC

BI

OUT

OUT

OUT

IN

IN

IN

OUTIN

OUTIN

IN

BI

BI

BI

OUT

BI

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

INOUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

LPC+SPI Connector

516S0573

EFI Debug ROM

SPI Bus Series Termination

Write: 0xAC/0xAERead: 0xAD/0xAF

LPCPLUS

5%1/16WMF-LF

402

47R5126

47 72

47

MF-LF

5%1/16W

402

R512215

1/16W5%

MF-LF402

R511219 72

402MF-LF1/16W

5%

LPCPLUS

47R5127

LPCPLUS

5%1/16WMF-LF

402

0R5128

EFI_DEBUG

SO8N

CRITICAL

M24M01-RU5101

0

402

1/16W5%

MF-LF

EFI_DEBUG

R5101

MF-LF

5%1/16W

402

0

NO STUFFR5104

0

402

1/16W5%

MF-LF

NO STUFFR5102

1/16W5%

MF-LF402

0

EFI_DEBUG

R5103EFI_DEBUG

20%10V

CERM

0.1UF

402

C5101

38

38

CRITICALLPCPLUS_CON

M-ST-SM55909-0374J5100

19 35 72

7 35 36

35 36

35

25

34 35 36

35

47 72

402MF-LF1/16W5%

15R5110

19 72

47 72

1/16W5%

MF-LF402

15R5111

19 72

25 72

19 35 72

19 35 72

19 35 72

7 19 47

7 19 35

19 35

35 36

35 36 55

35

35 36

34 35 36

7 19

19 35

19 35 72

47 72 15

402MF-LF

5%1/16W

R51237 19 72

47

402

1/16W5%

MF-LF

R5120

LPCPLUS

5%1/16WMF-LF

402

47R5125

1/16W

47

MF-LF

5%

402

R5121

LPC+SPI Debug ConnectorSYNC_MASTER=(T27_MLB) SYNC_DATE=(12/15/2009)

SPI_MOSISPI_MOSI_R

SPI_CLKSPI_CLK_R

SPI_CS0_LSPI_CS0_R_L

SPI_MISO SPI_MLB_MISO

SPI_MLB_MOSI

SPI_MLB_CLK

SPI_MLB_CS_L

SPI_ALT_MISOSPI_ALT_MOSISPI_ALT_CLKSPI_ALT_CS_L

SMC_TX_LSMC_MD1SMC_TRST_L

LPCPLUS_RESET_LSMC_TDO

PM_CLKRUN_LSMC_TMS

LPC_FRAME_L

LPC_AD<1>LPC_AD<0>

SPI_ALT_MOSISPI_ALT_MISO

=PP3V3_S5_LPCPLUS=PP5V_S0_LPCPLUS

LPC_CLK33M_LPCPLUSLPC_AD<2>LPC_AD<3>

SPIROM_USE_MLBSPI_ALT_CLKSPI_ALT_CS_LLPC_SERIRQLPC_PWRDWN_LSMC_TDISMC_TCKSMC_RESET_LSMC_NMISMC_RX_LLPCPLUS_GPIO

=I2C_DEBUGROM_SCL

=I2C_DEBUGROM_SDADEBUGROM_E2DEBUGROM_E1

=PP3V3_S0_DEBUGROM

51 OF 109

C.0.0

051-8561

37 OF 76

1

2

1 21 2

1

2

1

2

8

4

1

6

53

2

7

1

2

1

2

1

2

1

22

1

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

3

1

5

9

7

15

11

13

17

19

21

23

25

27

29

31 32

33 34

1 2

1 2

1 2

1 2

1

2

1 2

7 72

7 72

7 72

37 72

37 72

37 72

37 72

37 72

37 72

8

8

37 72

37 72

8

NBC




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Prod Temp(Write: 0x98 Read: 0x99)

EMC1413: U5515

U4900

SMC "0" SMBus Connections SMC "Battery A" SMBus Connections

PCA9557: U3310

SMC "B" SMBus Connections

(Write: 0x98 Read: 0x99)

Margin Control(Write: 0x30 Read: 0x31)

at 0x10/0x11, probably not used.

access internal thermal sensorsMCP89 SMBus 1 is slave port to

(Write: 0xE0 Read: 0xE1)

Another slave port is available

Read: 0xAD/0xAF)

(MASTER)U4900

NOTE: SMC RMT bus remains powered and may be active in S3 state

Debug Temp

DAC5574: U3300

(WRITE: 0X98 READ: 0X99)TMP442A: U5535

SMC

TrackpadSMCJ5800

Battery

Battery Temp - (Write: 0x90 Read: 0x91)

SMC "Management" SMBus Connections

SMC

(Not stuffed in production)

Debug Devices

EFI Debug Serial

(Write: 0xAC/0xAE

U1400MCP89

MCP89 SMBus "0" Connections

(Write: 0xA2 Read: 0xA3)

Battery Charger

(Write: 0xA0 Read: 0xA1)J2900U1400

(MASTER)

SMCU4900

(MASTER)

SMCU4900

(MASTER)U4900

ISL6259 - U7000

(See Table)J3100

MCP89

M24M01: U5101

CD3275: U6880

Debug ADC

SO-DIMM "A"

SO-DIMM "B"

Vref DACs(Write: 0x72 Read: 0x73)

Mikey

(MASTER)

(MASTER)

MCP89 SMBus "1" Connections

BATTERYJ6950

Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Manager - (Write: 0x16 Read: 0x17)


The bus formerly known as "Battery B"

(Write: 0x10 Read: 0x11)LT2309: U6000

SMC "A" SMBus Connections


=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDASMBUS_SMC_B_S0_SDAMAKE_BASE=TRUE

=I2C_VREFDACS_SDA

SMBUS_MCP_0_DATAMAKE_BASE=TRUE

SMBUS_MCP_0_CLKMAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDAMAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_A_S3

SMBUS_SMC_A_S3_SCLMAKE_BASE=TRUE

SMB_A_S3_DATA

SMB_0_S0_CLKMAKE_BASE=TRUESMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUESMBUS_SMC_B_S0_SCL

=I2C_TPAD_SCL

MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA

=PP3V3_S0_SMBUS_SMC_0_S0

=I2C_MCPTHMSNS_SDA

=I2C_MCPTHMSNS_SCL

=I2C_TPAD_SDA

SMB_MGMT_DATA=I2C_PCA9557D_SCL

=I2C_VREFDACS_SCL


SMBUS_MCP_1_DATAMAKE_BASE=TRUE

SMBUS_MCP_1_CLKMAKE_BASE=TRUE

=I2C_SODIMMB_SDA

SMB_B_S0_CLK

=I2C_MIKEY_SDA

=I2C_SODIMMA_SDA

=I2C_SODIMMA_SCL

SMB_0_S0_DATA SMB_BSA_DATA

SMB_BSA_CLK

SMB_MGMT_CLK =I2C_SMC_ADCS_SCL

=I2C_SMC_ADCS_SDA

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S3_SMBUS_SMC_MGMT

MAKE_BASE=TRUESMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDAMAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_B_S0

SMB_B_S0_DATA

=SMBUS_CHGR_SDA

=I2C_MIKEY_SCL

=I2C_SODIMMB_SCL

=SMBUS_BATT_SDA

=I2C_PCA9557D_SDA


=I2C_DEBUGROM_SDA

=I2C_DEBUGROM_SCL

=SMBUS_BATT_SCL

=SMBUS_CHGR_SCLMAKE_BASE=TRUESMBUS_SMC_BSA_SCL

MAKE_BASE=TRUESMBUS_SMC_BSA_SDA

SMB_A_S3_CLK

K87 SMBus ConnectionsSYNC_DATE=MASTERSYNC_MASTER=MASTER

5%

MF-LF1/16W

0

402

R5235

402

5%1/16WMF-LF

0R5236

402

5%1/16W

1K

MF-LF

R52011K5%

1/16W

402MF-LF

R5200

4.7K5%1/16W

402MF-LF

R5291

402

1/16W

4.7K

MF-LF

5%

R5290

NO STUFF

5%

MF-LF1/16W

402

2.0KR5230

NO STUFF

5%2.0K1/16WMF-LF402

R5231

MF-LF402

5%1/16W

10KR5250

402

5%1/16WMF-LF

10KR5251

MF-LF402

5%1/16W

1KR5270

402

5%

MF-LF1/16W

1KR5271

1/16W

4.7K5%

MF-LF402

R52604.7K

402

5%1/16WMF-LF

R5261

1%2.61K

402

1/16WMF-LF

R5281

MF-LF

1%2.61K

402

1/16W

R5280

52 OF 109

C.0.0

051-8561

38 OF 76

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

41

41 74

29

72 19 13

72 19 13

74 7

8

74 7

35

35 74

74

44

74

8

41

41

44

35 29

29

8

72 19

72 19

27

35

53

26

26

35 35

35

35 46

46

8

8

74

74

8

35

55

53

27

54

29

8

37

37

54

55 74 7

74 7

35

OUT

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT




36

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Enables PBUS VSense

Place RC close to SMC

divider when high.

MCP Voltage Sense / Filter

CPU Voltage Sense / Filter

PBUS Voltage Sense Enable & Filter



RTHEVENIN = 4573 Ohms

=PBUSVSENS_EN

PBUSVSENS_EN_L

PBUSVSENS_EN_L_DIV

PPBUS_G3H

SMC_MCP_VSENSE

GND_SMC_AVSS

SMC_PBUS_VSENSE

GND_SMC_AVSS

SMC_CPU_VSENSE

GND_SMC_AVSS

CPUVSENSE_IN

MCPVSENSE_IN

PPVCORE_S0_CPU

PPVCORE_S0_MCP

PBUS_G3H_VSENSE


Voltage Sensing

XW5309

PLACE_NEAR=U1000.AA13:19.05 mm

SM

C530920%6.3VX5R402

0.22UF

R53094.53K

1/16WMF-LF

1%

402

35

XW5359

PLACE_NEAR=U1400.AB22:5 mm

SM

Q5315SOT-963

NTUD3169CZ

R5386

402MF-LF1/16W

1%5.49K

R5385

402MF-LF1/16W

1%27.4K

C538520%6.3VX5R402

0.22UF

35

R5315

402MF-LF1/16W

1%100K

R5316

402MF-LF1/16W

1%100K

62

R53594.53K

1/16WMF-LF

1%

402C535920%6.3VX5R402

0.22UF

36

53 OF 109

C.0.0

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2

1

1 2

1

2

1

2 2

1

1

2

1

2

6

2

1

3

5

4

1 2

1 2

2

1

1 2

8 7

40 39 36 35 23

40 39 36 35 23

40 39 36 35 23

8 7

8 7

OUT

V+

REFIN+

IN- OUT

GND

OUT

OUTIN

V+

REFIN+

IN- OUT

GND

IN

OUT

IN OUT

VER 1

VCC

A

1

0

B1

GND

B0

SELIN

IN

IN

IN

OUT

IN

OUTIN-

IN+ REF

V+

GND

IN

IN

IN

+IN

-IN

V+

V-




36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MCP/CPU 1.05V AND CPU VCore High-Side Current Sense / Filter

MCP MEM VDD Current Sense / Filter

INA213 Gain: 50xISL6259 Gain: 36x

(50V/V)

For production, stuff BMON_PROD

Sense R is R7525, 1mOhm

(Sense R "output")

Max Vdiff = 24.8mV

(100V/V)Gain: 100x

Max VOut: 2.48V

R7593 at the same time!NOTE: Do not stuff R5415 and

PLACEMENT_NOTEs:

(For R and C)

MCP VCore Current Sense Filter

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(For R and C)From charger

DC-IN (AMON) Current Sense Filter

PLACEMENT_NOTEs:

(For R and C)

across R7008

For engineering, stuff BMON_ENG

Battery (BMON) Current Sense, MUX & Filter

NOTE: R5401/C5490 changed due to low source/sink current of ISL6259.

Scale: 10A / V

(For R’s and C)

PLACEMENT_NOTEs:

CPU VCore Load Side Current Sense / Filter

(Sense R "input")

battery to PBUS (battery discharge)NOTE: Monitoring current from

(50V/V)

Charger/Load side

Battery side

MCPDDR_SENSE_B

MCPDDR_SENSE_E

MCPDDRFET_SENSE

MCPDDRFET_KELVIN

=PP3V3_S0_MCPDDRISNS

MCPDDR_SENSE_AMP

=PPBUS_S5_CPUREGS_ISNSISNS_CPUVTT_P

ISNS_CPUVTT_N

MCPCORES0_VO

MCPCORES0_ISP_R

MCPCORE_IOUT

=PP3V3_S0_MCPCOREISNS MCPCORES0_IMON

MCPDDR_SENSE_C SMC_MCP_DDR_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

=PP3V3_S0_CPUVTTISNS

BMON_AMUX_OUT

CHGR_BMON

=PP3V42_G3H_BMON_ISNS

SMC_CPU_FSB_ISENSE

SMC_BMON_MUX_SEL

CPUVTT_IOUT

BMON_INA_OUTCHGR_CSO_R_P

GND_SMC_AVSS

GND_SMC_AVSS

SMC_CPU_ISENSE

GND_SMC_AVSS

SMC_MCP_CORE_ISENSE

IMVP6_IMON

SMC_DCIN_ISENSECHGR_AMON

SMC_BATT_ISENSE

GND_SMC_AVSS

=PPBUS_S5_CPUREGS_ISNS_R

CHGR_CSO_R_N


Current Sensing

SC70-5

U5400OPA330

CERM16V20%0.022UF

402

C5490

CRITICAL

0612-1MF1W

0.5%0.01

R5492

59

59

59

5%

MF-LF1/16W

0

402

R5415402

20%10VCERM

0.1uFC5420

INA214SC70

U5420

74 55

36

Place close to SMC

0.22UF

X5R

20%6.3V

402

C5435

Place close to SMC

MF-LF402

1%1/16W

R54174.53K

CERM402

20%10V

0.1uFC5400

402

0

MF-LF

5%1/16W

R54112

1

C5434

X5R

10%16V

402

0.1UF

NO STUFF

R5410

MF-LF

0

402

5%1/16W

21

21

SOD

Q54012SA2154MFV-YAE

118

MF-LF402

1%1/16W

R5412

74 55

35

BMON:ENG

SC70NC7SB3157P6XG

U5413Place close to SMC

6.3V20%

402X5R

0.22UFC5487

R5481

Place close to SMC

4.53K

MF-LF402

1%1/16W

35

1/16W1%

402MF-LF

6.19K

Place close to SMC

R5471

17.4K

MF-LF402

1%1/16W

Place close to SMC

R5480

58

Place close to SMC

0.22UF

X5R402

20%6.3V

C5470

35

1/16W1%

402MF-LF

Place close to SMC

45.3KR5401

0.1uF

CERM402

20%10V

BMON:ENGC5459

100K

MF-LF402

5%1/16W

BMON:ENGR5423

PLACEMENT_NOTE=Place R5431 next to U5413

1/16W5%

MF-LF

0

402

BMON:PROD

R54312 155

CKPLUS_WAIVE=PdifPr_badTerm

CKPLUS_WAIVE=NdifPr_badTerm

PLACEMENT_NOTE=Place near sense resistor

SC70INA213

BMON:ENG

U540310V20%

402CERM

0.1uF

BMON:ENGC5418

1/16W1%

402MF-LF

4.53K

Place close to SMC

R5416

Place close to SMC

1/16W1%

402MF-LF

4.53KR5418

55 35

Place close to SMC

6.3V20%

402X5R

0.22UFC5436

36

INA213SC70

U540210V20%

402CERM

0.1uFC5417

6.3V20%

402X5R

0.22UF

Place close to SMC

C5472

36

54 OF 109

C.0.0

051-8561

40 OF 76

2

1

2

1

23

14

5 6

2

1

1 2

1 2

2

1

23

14

5 6

1

2

2

1

1 2

2

11

2

1 2

1 2

2

1

2

3

1

4

6

5

1

2

2

1

3

1

2

2

1

2

1

1 2

2

1

65

4 1

32

2

1

1 2

2

1 3

4

2

1

2

5

4

1

3

8

8

75

75

8

40 39 36 35 23

40 39 36 35 23

8

8

40 39 36 35 23

40 39 36 35 23

40 39 36 35 23

40 39 36 35 23

8

BI

BI

THRM_PADDN2/DP3

DP2/DN3

VDD

SMDATA

SMCLKGND

DN1

DP1 THERM*/ADDR

ALERT*

SDA

SCL

GND

V+

DXP1

DXN1

DXP2

DXN2BI

BI

BI

BI

BI

BI




36

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DR


SHEET

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D

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DETECT FIN-STACK TEMPERATURE

PLACEMENT NOTE: PLACE U5535 NEAR MCP

MCP DIE/CPU DIE/MCP PROXIMITY THERMAL SENSOR

DETECT MCP DIE TEMPERATURE

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

APN 353S2795

DETECT CPU DIE TEMPERATURE

PLACEMENT NOTE: PLACE U5515 NEAR CPU

CPU PROXIMITY/HDD FLEX AREA/FINSTACK THERMAL SENSORINTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE

DETECT HDD TEMPERATURE

APN 353S2571

CPUTHMSNS_D2_N

CPU_THERMD_P

MCP_THMDIODE_P

CPU_THERMD_N

=PP3V3_S0_MCPTHMSNS

CPUTHMSNS_ALERT_L

=I2C_CPUTHMSNS_SCL

=PP3V3_S0_CPUTHMSNS

CPUTHMSNS_THERM_L


VOLTAGE=3.3V

PP3V3_S0_CPUTHMSNS_R

=I2C_MCPTHMSNS_SDA

=I2C_MCPTHMSNS_SCL

VOLTAGE=3.3V

PP3V3_S0_MCPTHMSNS_R


=I2C_CPUTHMSNS_SDA

CPUTHMSNS_D2_P

CPUTHMSNS_D1_N

CPUTHMSNS_D1_P

MCP_THMDIODE_N


Thermal Sensors

0.0022uF

CERM402

10%50V

C5520

1/16W5%

402MF-LF

47R5515

10V20%

402CERM

0.1uFC5515

75 19

75 19

MCP_T_DIODE_SENSOR

100PF5%

50VCERM402

C5522

75 10

75 10

MCP_T_DIODE_SENSOR

100PF5%

50VCERM402

C5540

1/16W5%

402

47

MCP_T_DIODE_SENSOR

MF-LF

R5535

10V20%

402CERM

0.1uF

MCP_T_DIODE_SENSOR

C5535

38

38

SOT23-8TMP442A

MCP_T_DIODE_SENSOR

U5535

SOT732-3

Q5502BC846BMXXH

PLACEMENT_NOTE=PLACE CLOSE TO J4501 IN A CONVENIENT LOCATION DFNEMC1413

CRITICAL

U5515

BC846BMXXHSOT732-3

Q5501

50V10%

402CERM

0.0022uFC5521

1/16W1%

402MF-LF

10KR5516

1/16W5%

402MF-LF

10KR5517

38

38

55 OF 109

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41 OF 76

1

2

1

2

2

1

1

2

3

11

5

4

1

9

10

6

3

2 7

81

2

3

6

7

5

8

1

2

3

4

2

1

1 2

2

1

2

1

2

1

1 2

2

1

75

8

8

75

75

75

D

GS

NC

NC

IN

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

518S0521

5V DCTACH

GNDMOTOR CONTROL

SMC_FAN_0_TACH

SMC_FAN_0_CTL

FAN_RT_TACH

=PP3V3_S0_FAN_RT=PP5V_S0_FAN_RT

FAN_RT_PWM


Fan Connector

35

35

J560178171-0004

M-RT-SM

CRITICAL

Q5660

SOD-VESM-HFSSM3K15FV

R5661

402MF-LF1/16W

5%100K

R5660

402MF-LF1/16W

5%47K

R5665

402

5%

MF-LF1/16W

47K

56 OF 109

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1 2

1

2

1

2

12 3

5

1

2

4

6

37

8

8

7

P2_4

P2_6

VDD

P0_4

P0_2

P2_0P2_2P

0_0

P2_3P2_1P4_7P4_5P4_3P4_1P3_7P3_5P3_3P3_1P5_7P5_5P5_3P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSS

D+D-VDD

P7_0

P1_0

P1_2

P1_4

P1_6 P5_0

P5_2P5_4P5_6P3_0P3_2P3_4

P4_0P4_2P4_4P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PADTHRML

(SYM-VER2)

P0_1

IN

NC

NC

OUT

NC

NC

IN_A1

OUT_B

IN_A3_B2

GNDTHRM

OUT_A

VDD

IN_A2

IN_B1

PAD

(IPD)

(IPD)

(IPD)

(IPD)

IN_A1

OUT_B

IN_A3_B2

GNDTHRM

OUT_A

VDD

IN_A2

IN_B1

PAD

(IPD)

(IPD)

(IPD)

(IPD)

D

SG

D

SG

OUT




36

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DR


SHEET

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A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PIN NAME

Keys ANDed with PSOC power to isolate when PSOC is not powered.

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

SMC Manual Reset & Isolation

36E-3 W

Keyboard Connector

518S0637

- KEYBOARD SCANNER- TRACKPAD PICK BUTTONS- SPI HOST TO Z2

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

THE TPAD BUTTONS WILL BE DISABLE

PLACE THESE COMPONENTS CLOSE TO J5800

LID CLOSE => SMC_LID_LC < 0.50VLID OPEN => SMC_LID_LC ~ 3.42VWHEN THE LID IS CLOSED

TPAD Buttons Disable

96E-6 W

75.2E-6 W

294E-6 W

0.72E-3 W

16.32E-6 W0.255E-6 W

4.7 OHM

1.5 OHM

0.2 OHM 10 OHM

2.55 KOHM

14MA (MAX)

4MA (MAX)

8MA (TYP)

60MA (MAX)60MA (MAX)3V3 LDO VDD

VOUT

80UAV+TMP102

- USB INTERFACES TO MLB

PSOC USB CONTROLLER10UA

IC CURRENT R_SNS V_SNS POWER

0.0255 V0.204 V

0.6 V0.012 V

0.012 V0.021 V

0.0188 V18V BOOSTER VIN

VDDPSOC

337S2983

ISSP SDATA/I2C SDA

(PP3V3_S3_PSOC)

ISSP SCLK/I2C SCL

Pull-up in U5010.

WS_LEFT_OPTION_KEY

=PP3V3_S3_TPAD

=PP3V42_G3H_TPAD

WS_CONTROL_KBD

WS_LEFT_OPTION_KBD

WS_LEFT_SHIFT_KBD

WS_CONTROL_KEY

WS_LEFT_SHIFT_KEY

WS_KBD16_NUM

WS_KBD15_C

WS_KBD16N

WS_KBD15_CAP

WS_KBD8

WS_KBD23WS_KBD22

WS_KBD19WS_KBD20WS_KBD21

WS_KBD9WS_KBD10

WS_KBD12WS_KBD11

WS_KBD13WS_KBD14

WS_KBD17WS_KBD18

WS_KBD4WS_KBD3WS_KBD2WS_KBD1

=PP3V3_S3_TPAD


WS_KBD22

WS_KBD18

WS_KBD23

WS_LEFT_OPTION_KEYWS_LEFT_SHIFT_KEY

PICKB_L

Z2_HOST_INTNBUTTON_DISABLE

WS_KBD5WS_KBD4

WS_KBD6

WS_KBD17WS_KBD16N

WS_KBD14WS_KBD15_C

WS_KBD12WS_KBD13

WS_KBD11WS_KBD10

WS_KBD8WS_KBD7WS_KBD1WS_KBD2WS_KBD3

WS_CONTROL_KEY

PSOC_MOSI

USB_TPAD_P

USB_TPAD_N

=PP3V3_S3_TPAD

Z2_CLKIN

=PP3V42_G3H_TPAD

WS_KBD_ONOFF_L

WS_LEFT_SHIFT_KBDWS_LEFT_OPTION_KBDWS_CONTROL_KBD

WS_KBD9

USB_TPAD_R_P

TP_ISSP_SDATA_P1_0

SMC_ONOFF_L

Z2_KEY_ACT_L

Z2_RESETZ2_DEBUG3

PSOC_MISOPSOC_F_CS_L

TP_PSOC_SDA

TP_P4_5

TP_P7_7


VOLTAGE=3.3V

PP3V3_S3_PSOC

USB_TPAD_R_N

TP_ISSP_SCLK_P1_1TP_PSOC_P1_3

TP_PSOC_SCL

PSOC_SCLK

Z2_CS_LZ2_MISO

Z2_MOSIZ2_SCLK

SMC_LID

BUTTON_DISABLE

SMC_TPAD_RST_L

SMC_TPAD_RST


WELLSPRING 1SYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010

36

Q5701SSM6N15FEAPE

SOT563

Q5701SOT563

SSM6N15FEAPE

U5750

CRITICAL

SLG4AP006TDFN

C57500.1UF

402

10%16VX7R-CERM

C57550.1UF

402

10%16VX7R-CERMU5755

TDFNSLG4AP006

CRITICAL

12

R57041.5

1/16WMF-LF

5%

402

36 35

J5713

F-RT-SM

FF14-30A-R11B-B-3H

CRITICAL

R571510K

1/16WMF-LF

1%

402

R5714LED:K6_K69

402

1%

MF-LF1/16W

470

R5710

1/16WMF-LF

5%

402

1K

C5710

CERM10V

402

PLACEMENT_NOTE=NEAR J5713

0.1UF20%

54 36 35

R570124

1/16WMF-LF

5%

402

U5701MLF

CY8C24794

OMITCRITICAL

R5702

402

5%

MF-LF1/16W

24C57014.7UF

603X5R6.3V20%

BYPASS=U5701.22:19:11 mm

C57025%50VCERM402

BYPASS=U5701.22:19:5 mm

100PFC570310%16VX7R-CERM402

0.1UF

BYPASS=U5701.22:19:8 mm

C5704100PF

402CERM50V5%

BYPASS=U5701.49:50:5 mm

C570510%16VX7R-CERM402

0.1UF

BYPASS=U5701.49:50:8 mm

C570620%6.3VX5R603

4.7UF

BYPASS=U5701.49:50:11 mm

57 OF 109

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2

1

2

1

2

1

2

1

2

1

2

1

1 2

57

44

47

48

52

51

50

49

42

41

39

40

37

38

36

35

34

33

32

31

30

29

28

26

27

25

24

23

22

21

20

19

18

17

16

15

1

2

4

3

7

5

6

8

9

10

11

12

14

13

45

46

43

53

54

55

56

1 2

2

1

1 2

1 2

1 2

21

22

32

31

1

2

5

4

3

6

7

10

9

8

20

19

17

18

16

15

14

13

12

11

23

24

25

26

27

28

29

30

2

8

7

5 9

4

1

3

6

2

1

2

1

2

8

7

5 9

4

1

3

6

6

12

3

45

43

44 43 8

43 8

43 7

43 7

43 7

43

43

7

43

43

7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

44 43 8

43 7

43 7

43 7

43 7

43 7

43 7

43

43

44 7

44 7

43

43 7

43 7

43 7

43 7

43

43 7

43

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43 7

43

44 7

72 18

72 18

44 43 8

44 7

43 8

7

43 7

43 7

43 7

43 7

75

44 7

44 7

44 7

44 7

44 7

75

44 7

44 7

44 7

44 7

44 7

43

43 7

43 7

43 7

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD GND

NC

NC




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BOOSTER +18.5VDC FOR SENSORSBOOSTER DESIGN CONSIDERATION:

- R5812,R5813,C5818 MODIFIED- STARTUP TIME LESS THAN 2MS

- RIPPLE TO MEET ERS- DROOP LINE REGULATION

- 100-300 KHZ CLEAN SPECTRUM

- POWER CONSUMPTION

516S0689

IPD Flex Connector

DO NOT SYNC FROM T27. REMOVED KEYBOARD BKLIGHT CIRCUIT

MIN_LINE_WIDTH=0.50MM

VOLTAGE=18.5VMIN_NECK_WIDTH=0.20MM

PP18V5_S3PP18V5_S3_R

VOLTAGE=18.5VMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM

=PP5V_S3_TPAD

VOLTAGE=5V

MIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

PP5V_S3_P18V5S3_VIN

PP5V_S3_P18V5S3

VOLTAGE=5VMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM

Z2_RESETPSOC_F_CS_LPICKB_LPSOC_MISOPSOC_MOSIPSOC_SCLK=I2C_TPAD_SDA=I2C_TPAD_SCL

PP18V5_S3

Z2_KEY_ACT_LZ2_DEBUG3

Z2_CLKIN

Z2_BOOST_EN

SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MMP18V5S3_SW

Z2_CS_L

Z2_MOSIZ2_MISOZ2_SCLKZ2_BOOST_ENZ2_HOST_INTN

=PP3V3_S3_TPAD

P18V5S3_FB

WELLSPRING 2SYNC_MASTER=MASTER SYNC_DATE=MASTER

402

OMIT

NONENONE

NONE

SHORTR5806

402

OMIT

NONENONE

NONE

SHORTR5805

71.5K1%1/16WMF-LF402

R5813

402MF-LF1/16W1%1MR5812

5%

402

39PF50VCERM

C5818

402MF-LF1/16W1%100KR5811

3.3UH-870MA

VLF3010AT-SM-HF

CRITICALL5801

TPS61045QFN

CRITICAL

U5805

16V

2.2UF

603X5R

10%

C581710%

X7R-CERM402

0.1UF16V

C5816

25V

1UF

603-1X5R

10%

C5819

B0520WSXG

SOD-323

CRITICALD5802

CRITICAL

M-ST-SM55560-0228J5800

58 OF 109

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22

20

18

16

14

12

10

8

6

4

2

3

21

19

17

15

13

11

9

7

5

1

1 2

2

1

2

1

2

1

5

7 69

1

2

3

4

8

21

1

2

2

11

2

1

2

12

1 2

44 7

8

43 7

43 7

43 7

43 7

43 7

43 7

38

38

44 7

43 7

43 7

43 7

44 7

43 7

43 7

43 7

43 7

44 7

43 7

43 8

OUT

OUT

OUT

IN

GND

SEL0

VDD

ST

SEL1

DNC

AZ

AY

AX

AMUX

NCNC




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8 7 5 4 2 1

C5923.1:C5924.1:C5925.1:

PLACE_NEARs:

in correct orientation

C4950-C4952 CAP VALUES WILL BE USED TO GET CUT-OFF FREQUENCY OF ~146HZ

DO NOT SYNC WITH K84. REMOVED NO STUFF ON C5923,C5924,C5925. ADDED PLACE NEARS

Desired orientation when

placed on board top-side:

Front of system

Analog SMSR5921 PULLS UP SEL PINS TO ENTER STANDBY MODE WHEN PIN IS NOT BEING DRIVEN BY SMC

+X

+Y

Circle indicates pin 1 location when placed

+Z (up)

SMS_Y_AXIS

SMS_X_AXIS

SMS_Z_AXIS

MIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MMVOLTAGE=3.3V

PP3V3_S3_SMS_FILT

SMS_PWRDNMAKE_BASE=TRUE

SMS_ONOFF_L

=PP3V3_S3_SMS

SMSSYNC_MASTER=MASTER SYNC_DATE=MASTER

10K

MF-LF402

5%1/16W

R5921

1/16W5%

402MF-LF

10R5922

PLACE_NEAR=U4900.K10:2.54MM

X5R

0.033UF

402

10%16V

C5925

PLACE_NEAR=U4900.N9:2.54MM

402

16V10%

X5R

0.033UFC5924

0.01UF

CERM402

10%16V

C5926

BMA141LGA

CRITICAL

U5920

35

16V10%

402X5R

0.1UFC5922

35

35

35

PLACE_NEAR=U4900.M10:2.54MM

0.033UFC5923

16V10%

402X5R

59 OF 109

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2

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4

12

1 2

3

5

6

7

8

9

10

11

2

1

2

1

2

1

1 2

1

2

8

COM

GNDTHRM

DVDDAVDD

AD0

AD1

SDA

SCL

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

VREF

REFCOMP

PAD

BI

IN

IN

IN

V+

REFIN+

IN- OUT

GND

+IN

-IN

V+

V-

+IN

-IN

V+

V-

+IN

-IN

V+

V-

IN

IN

IN

IN

IN

IN




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8 7 5 4 2 1

GAIN: 561X

GAIN: 845X

DIVIDER: ~ 2/5DIVIDER: ~ 2/3

GAIN: 200X

GAIN: 1239X

DIVIDER: 3/40

ADC RANGE: 0V TO 4.096V

LSB: 0.001V

I2C ADDRESS: 0X10 / 0X11

ADC_CH3 unused, so pulling down.

ISNS_ODD_IOUT

=PP5V_S3_DEBUG_ISNS

PLACE_NEAR=J4500.9:25.4mmPP5V_SW_ODD

ISNS_HDD_R_P

ISNS_ODD_R_N

ADC_CH7

ADC_CH7

ADC_SCL =I2C_SMC_ADCS_SCLADC_SDA

=PP5V_S3_DEBUG_ADC_DVDD

ISNS_LCDBKLT_IOUT

ISNS_HDD_P

ISNS_ODD_N

ISNS_AIRPORT_P

P5V_SW_ODD_XW

ADC_CH4

ADC_CH5

ADC_REFCOMP

ADC_CH6

ADC_CH2

P3V3_WLAN_F_XW

PVOUT_S0_LCDBKLT_XW

ADC_CH5

ISNS_HDD_N

PLACE_NEAR=J3401.22:25.4mmPP3V3_WLAN_F

ISNS_AIRPORT_R_P

ISNS_AIRPORT_N

ISNS_LCDBKLT_P

=PP5V_S3_DEBUG_ISNS

ADC_CH0

ADC_CH6

P3V3_WLAN_F_DIV

ISNS_LCDBKLT_N

ADC_VREF

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=5V

PP5V_S3_DEBUG_ADC_DVDD_FILT

ADC_CH0

PP5V_S3_DEBUG_ADC_AVDD_FILTMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=5V

ISNS_HDD_IOUT

ISNS_AIRPORT_R_N

=PP5V_S3_DEBUG_ISNS

ISNS_HDD_R_N

ISNS_ODD_R_PISNS_ODD_P

PVOUT_S0_LCDBKLT_DIV

PPVOUT_S0_LCDBKLT

ADC_CH1P5V_SW_ODD_DIV

ADC_CH4

ADC_CH3

ADC_CH2

ADC_CH1

=PP5V_S3_DEBUG_ADC_AVDD

=I2C_SMC_ADCS_SDA

ISNS_AIRPORT_IOUT

DEBUG SENSORS AND ADCSYNC_MASTER=MASTER SYNC_DATE=MASTER

402

DEBUG_ADC

412

1/16WMF-LF

1%

R6061

DEBUG_ADC

402

499

1/16W1%

MF-LF

R6050

402

1%1/16W

499

DEBUG_ADC

MF-LF

R6051

75 33

75 33

75 33

75 33

DEBUG_ADC

CERM402-LF

6.3V20%2.2UFC6006

NO STUFF

402CERM

470PF

50V10%

C6062348K

402

1/16WMF-LF

DEBUG_ADC

1%

R6062

NO STUFF

CERM50V

402

10%

470PFC6063MF-LF

402

1%1/16W

348K

DEBUG_ADC

R6063

NO STUFF

402

470PF10%50V

CERM

C6052

1/16W

402MF-LF

1%280K

DEBUG_ADCR6052

NO STUFF

10%

CERM

470PF

402

50V

C6053402

1%1/16WMF-LF

280K

DEBUG_ADC

R6053

402

1/16WMF-LF

226K

DEBUG_ADC

1%

R6064

20%10V

402

0.1UF

CERM

DEBUG_ADC

C6051

402MF-LF

226K

DEBUG_ADC

1/16W1%

R6054

DEBUG_ADC

20%0.1UF

CERM402

10V

C6000

402X5R

2.2UF

DEBUG_ADC

10%6.3V

PLACEMENT_NOTE=PLACE RC NEAR U6000

C6064

6.3VX5R

10%2.2UF

DEBUG_ADC

402


C6054

DEBUG_ADC

0.1UF

CERM402

20%10V

C6004

226K

MF-LF

1%1/16W

DEBUG_ADC

402

R6034

402

2.2UF

X5R

10%

DEBUG_ADC

6.3V


C603475 30

DEBUG_ADC

0.1UF

10V20%

402CERM

C6030

301K

MF-LF

DEBUG_ADC

402

1/16W1%

R6033

402MF-LF1/16W1%

243

DEBUG_ADC

R6030

243

DEBUG_ADC

1%

MF-LF402

1/16W

R6031

NO STUFF

50V

470PF

CERM

10%

402

C6033

301K

MF-LF402

1%1/16W

DEBUG_ADCR6032NO STUFF

470PF

50V10%

CERM402

C6032

75 30

CERM402

20%10V

0.1UF

DEBUG_ADC

C6002

1/16W1%

DEBUG_ADC

402

681K

MF-LF

R6021

1%

DEBUG_ADC

1M

MF-LF1/16W

402

R6020

R6022

DEBUG_ADC

402

1%1/16W

226K

MF-LF


DEBUG_ADC

402X5R6.3V

2.2UF10%

C6022


402X5R

2.2UF10%

DEBUG_ADC

6.3V

C6012

DEBUG_ADC

402

1%1/16WMF-LF

226KR6012

DEBUG_ADC

MF-LF1/16W1%

402

1MR6011

DEBUG_ADC

402

634K1%1/16WMF-LF

R6010

PLACEMENT_NOTE=PLACE NEAR Q4590

SM

OMIT

XW6020

PLACEMENT_NOTE=PLACE NEAR Q3450

SM

OMIT

XW6010

20%

603X5R6.3V

10UF

DEBUG_ADC

C6001

402

1/16WMF-LF

5%1K

R6005DEBUG_ADC

DEBUG_ADC

10

1/16W5%

402MF-LF

R6004

MF-LF402

1/16W

10

5%

DEBUG_ADCR6003

DEBUG_ADC

0.1UF

CERM10V20%

402

C6061

20%6.3VX5R603

10UF

DEBUG_ADC

C6003

SC70-5OPA330

DEBUG_ADC

U6030

OPA330

DEBUG_ADC

SC70-5

U6061

DEBUG_ADC

SC70-5OPA330U6051

DEBUG_ADC

MF-LF402

1/16W5%

33

PLACEMENT_NOTE=PLACE CLOSE TO U4900R6002MF-LF1/16W5%

402

DEBUG_ADC

PLACEMENT_NOTE=PLACE CLOSE TO U4900

33R6001

DEBUG_ADC

INA210SC70

U6050

MF-LF

DEBUG_ADC

1%1/16W

402

75KR6081

1%1/16W

402

1M

MF-LF

DEBUG_ADC

R6080

10UF

X5R603

20%6.3V

DEBUG_ADC

C6005

SM

OMIT


XW6080

402

1/16WMF-LF

1%

226K

DEBUG_ADC

R6082

DEBUG_ADC


6.3V10%

X5R

2.2UF

402

C6082

DEBUG_ADC

10VCERM

20%

402

0.1UFC6050

75 67

75 67

38

MF-LF402

1%1/16W

226K

DEBUG_ADC

R6074

402X5R


2.2UF10%6.3V

DEBUG_ADC

C6074

402

1%1/16WMF-LF

412

DEBUG_ADC

R6060

38 LTC2309

DEBUG_ADC

QFN

U6000

60 OF 109

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051-8561

46 OF 76

6

11

109

18

20

25

19

21

13

12

14

15

17

16

22

23

24

1

2

3

4

5

7

8

1 2

2

1

1 2

2

1

2

1

1 2

1 2

2

1

1

2

1

2

23

14

5 6

1 2

1 2

2

5

4

1

3

2

5

4

1

3

2

5

4

1

3

2

1

2

1

1 2 1 2

1

2

2

11 2 1 2

1

2

1

2

1 2

2

1

2

1

1 2

1

2

1

2

2

1

2

11

2

1 2

1 2

1 2

1 2

2

1

2

1

1 2

2

1

2

1

2

1

2

1

1 2

2

1

1 2

1 2

1 2

1

2

2

1

1 2

1 2

1

2

2

1

2

1

1 2

1 2

1 2

46 8

33 7

75

75

46

46

8

46

46

46

46

46

30

75

46 8

46

46

46

75

46 8

75

75

67 64 7

46

46

46

46

8

OUTIN

IN IN

IN

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1




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Frequency

0

0

1

1

SPI_MOSI SPI_CLK

0

1

0

1

MCP89 SPI Frequency Select

62.5 MHz

41.7 MHz

25.0 MHz

31.2 MHz

NOTE: 42 & 62 MHz use FAST_READ command.

ROM will ignore SPI cycles.NOTE: If HOLD* is asserted

SPIROM_USE_MLB

SPI_MLB_CS_LSPI_MLB_MISO

SPI_WP_L

SPI_MLB_CLK

=PP3V3_S5_ROM

SPI_MLB_MOSI

SPI ROMSYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010

R615010K

5%1/16WMF-LF

402

SPI:31MHZ&SPI:62MHZ

R615210K

5%1/16WMF-LF

402

SPI:25MHZ&SPI:41MHZ

R6153

402MF-LF1/16W5%10K

SPI:25MHZ&SPI:31MHZ

R6151

402MF-LF1/16W5%10K

SPI:41MHZ&SPI:62MHZ

U610032MBIT

MX25L3205DM2I-12G

SOP

OMIT

CRITICAL

37 19 7

72 37 72 37

72 37 72 37

R61013.3K5%1/16WMF-LF402

C610020%10V

CERM402

0.1UF

61 OF 109

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2

11

2

48

3

1

5

7

6

2

1

2

1

2

1

2

1

2

8

IN

IN

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

OUTOUT

NR/FB

NC

IN

EN

GND

OUT

OUT

OUT

IN

IN

IN

OUT

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REFVD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC

FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+

MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI

SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+

LINEOUT_L2-

LINEOUT_R2+

/SPDIF_OUT2

OUT

IN




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8 7 5 4 2 1

4.5V POWER SUPPLY FOR CODEC

VD MUST BE LESS THAN OR EQUAL TO VL_HD

APPLE P/N 353S2281

EXT MIC CODEC INPUT

SUB SPKR AMP. SIG. SOURCE

GPIO1 = HP AMP CONTROL

GPIO3 = SPKR AMP SHDN CONTROL

APPLE P/N 353S2355AUDIO CODEC

NC

NC

NCNC

DIFF FSINPUT= 2.45VRMS

DAC1 FSOUTPUT= 1.34VRMSSE FSINPUT= 1.22VRMS

DAC2/3 FSOUTPUTSE= 1.34VRMSDAC2/3 FSOUTPUTDIFF= 2.67VRMS

NOTES ON CODEC I/O

GPIO0 = ANALOG SW CONTROL

NC

NC

BI MIC CODEC INPUT

LFT. SPKR AMP. SIG. SOURCE

RT. SPKR AMP. SIG. SOURCE

HDA_SDIN0 HDA_SDIN_CODEC

HDA_SYNC

HDA_BIT_CLK

GND_AUDIO_HP_AMP

CS4206_FLYP

AUD_GPIO_3

GND_AUDIO_HP_AMPVOLTAGE=0V


4V5_REG_EN

=PP5V_S3_AUDIO

GND_AUDIO_CODECVOLTAGE=0VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MM

AUD_SENSE_A

GND_AUDIO_CODEC

4V5_REG_IN

MIN_NECK_WIDTH=0.2MMVOLTAGE=5V


AUD_GPIO_1

VOLTAGE=4.5VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

PP4V5_AUDIO_ANALOG


PP1V8R1V5_S0_AUDIO_DIG

VOLTAGE=1.5V


=PP3V3R1V5_S0_AUDIO

PP4V5_AUDIO_ANALOG

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM AUD_HP_PORT_R

AUD_GPIO_0

CS4206_FN

CS4206_FP

=PP5V_S3_AUDIO

TP_AUD_GPIO_2

CS4206_FLYC

=PP1V8R1V5_S0_AUDIO

4V5_NR

=PP3V3_S0_AUDIO

AUD_MIC_IN_R_N

VBIAS_DAC

CS4206_VREF_ADC

PP4V5_AUDIO_ANALOG

CS4206_FLYN

TP_AUD_DMIC_CLK

GND_AUDIO_CODEC

GND_AUDIO_HP_AMP

AUD_MIC_IN_L_P

AUD_LI_P_R

AUD_LI_REF

AUD_LI_P_L

AUD_LO2_R_N

AUD_LO2_R_P

AUD_MIC_IN_L_N

AUD_CODEC_MICBIAS

AUD_MIC_IN_R_P

=PP3V3_S0_AUDIO

AUD_LO1_R_P

CS4206_VCOM

AUD_LO1_R_N

TP_AUD_LO1_N_L

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM AUD_HP_PORT_REF

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM AUD_HP_PORT_L

TP_AUD_LO1_P_L

AUD_LO2_L_N

AUD_LO2_L_P

AUD_SPDIF_OUT_CHIP

HDA_RST_L

AUD_SPDIF_OUT

TP_AUD_SPDIF_IN

HDA_SDOUT

SYNC_MASTER=AUDIO

AUDIO: CODEC/REGULATOR

SYNC_DATE=02/16/2010

22

5%1/16WMF-LF

R6211

402

53 52 48 8

16VX5R

10%0.1UF

402

C6226

52

CS4206ACNZCQFN

CRITICAL

U6201

50

49

49

49

MF-LF

5%

402

39R6212

1/16W

FERR-220-OHM

0402

L6201

R6201

NOSTUFF

5%

MF-LF

0

1/16W

402

XW6200SM

51

51

51

16V10%

402X7R-CERM

0.1UFC6202

SONTPS71745U6200

CRITICAL

X5R402-1

10V10%1UF

C6216

48 7

52

48 7

8

48 7

52

53 52 48 8

52 50 48 8

C6219

2012-LLP

16V

10UF

TANT-POLY

20%10UF

16V20%

TANT-POLY2012-LLP

C6217

10UF

16V

2012-LLP

20%

TANT-POLY

C6225

C62180.1UF

X5R

10%

402

16V

NOSTUFF

MF-LF1/16W5%

402

100KR6213

1%

MF-LF402

1/16W

2.67KR6210

X5R16V10%

402

0.1UFC6214

C6211

16V

0.1UF10%

X5R402

16VX5R402

0.1UF10%

C6215

C6200

402X5R10V10%1UF

1/16W

402MF-LF

1%

R62002.21K

0402

FERR-220-OHML6200

X5R

1UF

402

10V10%

C6203

1UF

402X5R10V10%

C6201

20%

603-1X5R6.3V

10UF CRITICAL

C6213

53

53

53

53

53

51

51

51

50

50

51

53

72 19

72 19

72 19

72 19

72 19

C6210

X5R-1

4.7UF20%

402

4V

0603-SM

1UF

TANT

20%16V

C6224

603-1X5R6.3V20%

10UF

CRITICAL

C6220

6.3VCERM

20%

402-LF

2.2UFC6223

6.3V20%

CERM

2.2UF

402-LF

C6222

SMXW6201

603-1X5R

20%

CRITICAL

6.3V

C622110UF

62 OF 109

C.0.0

051-8561

48 OF 76

2

1

1 2

2

1

2

1

2

1

1

2

2

1

2

1

2

1

2

1

21

1 2

2

1

2

1

2

1

2

1

1

2

1

2

2

1

1

2

1

2

1

2

2

1

1

3

5

2

6

4

2

1

1 2

1 2

21

1 2

3

13

12

2

44

14

11

34

29

45

24

9

15

41

37

36

33

48

22

43

42

47

35

49

46

40

39

28

26

25

23

21

18

17

16

10

7

4

38

8

5

1

6

20

19

27

31

30

32

2

1

1 2 72

52 50 48

52 50 48

53 52 49 48

53 52 49 48

8

52 50 48 8

53 52 49 48

52 50 48

IN

IN

IN

OUT

OUT

OUT

IN




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PAGE


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345678

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8 7 5 4 2 1

VIN = 2VRMS, CODEC VIN = 1.14 VRMS

LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS

FC_HP = 3.6 HZNET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)

FC_LP = 43KHZ

GND_AUDIO_CODEC

AUD_LI_R_DIVMIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

AUD_LI_L

MIN_NECK_WIDTH=.1MMMIN_LINE_WIDTH=.1MM

AUD_LI_P_RMIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

AUD_LI_R

AUD_LI_P_LMIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MMAUD_LI_L_DIV

AUD_LI_GNDMIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM AUD_LI_REF

MIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

AUDIO: LINE INPUT FILTER

R6300101%

402MF-LF1/16W

C6313NOSTUFF

50VCERM402

820PF10%

C6303NOSTUFF

50VCERM402

820PF10%

R6312

MF-LF1/16W

402

1%21.5K

R6302

MF-LF1/16W

402

1%21.5K

R6311

MF-LF1/16W

402

1%

7.87K

R6301

MF-LF1/16W

402

1%

7.87K

C63112.2UF

402

10V20%

X5R-CERM

CRITICAL

C6312

20%

402

10V

2.2UF

CRITICAL

X5R-CERM

C6302

20%10V

2.2UF

X5R-CERM402

CRITICAL

C6301

402

10V

2.2UF

CRITICAL

X5R-CERM

20%

53 52 48

48

48

48

52

52

52

63 OF 109

C.0.0

051-8561

49 OF 76

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1

2

2

1

2

1

1

2

SVSS

INL

SHDN*

INR

VDD

PVSS

PGND

SGND

THRM

OUTR

OUTL

C1P

C1N

PAD

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN




36

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345678

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8 7 5 4 2 1

NC

CS4206 HP OUTPUT ZOBEL NETWORK

NC

HP/LO AMP

MAX9724 GAIN/FILTER COMPONENTS

AV_PB = -1V/V, FC_LPF = 35.2KHZ

APN: 353S1637

NOSTUFFCRITICAL

0.1UF10%

X7R-CERM

16V

402

C6500

NOSTUFF

MF-LF

5%

1/16W

402

39

R6500

NOSTUFFCRITICAL

402

X7R-CERM

16V10%

0.1UF

C6510

NOSTUFFR6510

1/16W

MF-LF

402

395%

CRITICAL

MAX9724ATQFN

U6500

402X5R10V10%1UF

CRITICAL

C6522

CRITICAL

10V10%1UF

X5R402

C6523

CRITICAL

10VX5R

10%1UF

402

C6524

6.3V20%10UF

X5R603

C6521

402X7R-CERM16V10%0.1UFC6520

FERR-120-OHM-1.5A

0402-LF

L6520

5%

MF-LF1/16W

100K

402

R6522

1/16WMF-LF

13.7K

1%

402

R6531

1/16W1%

13.7K

MF-LF402

R6530

MF-LF1/16W

13.7K

1%

402

R6533MF-LF1/16W

13.7K

1%

402

R6532

330PF

402

5%

CRITICAL

COG50V

C6530

50VCOG

330PF

5%

CRITICAL

402

C6531

5%

0

1/16W

402

MF-LF

R6520

48 50

48 50

48

50 52

50 52

50 52

50 52

MF-LF

1%2.21K1/16W

402

R6523

1%2.21K1/16WMF-LF402

R6524

48 50

48 50 52

48 50

SYNC_DATE=02/16/2010SYNC_MASTER=AUDIO

AUDIO: HEADPHONE FILTER

AUD_LO_AMP_INL_M

MAX9724_SVSS

MAX9724_C1N

AUD_LO_AMP_OUTLMIN_LINE_WIDTH=0.2MM


GND_AUDIO_HP_AMP

MAX9724_C1PAUD_LO_AMP_INR_M

MIN_NECK_WIDTH=0.2MMAUD_PP5V_F


AUD_GPIO_1_R

AUD_HP_ZOBEL_R

AUD_LO_AMP_INR_M

AUD_HP_PORT_R

GND_AUDIO_HP_AMP

AUD_LO_AMP_OUTRAUD_HP_PORT_R

AUD_HP_PORT_L

AUD_GPIO_1


MIN_LINE_WIDTH=0.2MMAUD_LO_AMP_OUTR

AUD_LO_AMP_OUTL

AUD_HP_ZOBEL_L

AUD_HP_PORT_L

=PP5V_S3_AUDIO

AUD_LO_AMP_INL_M

65 OF 109

C.0.0

051-8561

50 OF 76

2

1

1

2

2

1

1

2

9

6

5

8

12

427

13

10

11

1

3

2

1

2

1

2

1

2

1

2

1

21

1

2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

2 1

2

50

48 50 52

50

50

8 48 52

50

IN

IN

IN

IN

IN

IN

IN

IN-

SD*

IN+ OUTA

PVDD

GNDPGND

OUTB

VDD

IN-

SD*

IN+ OUTA

PVDD

GNDPGND

OUTB

VDD

IN-

SD*

IN+ OUTA

PVDD

GNDPGND

OUTB

VDD

OUT

OUT

OUT

OUT

OUT

OUT




36

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8 7 5 4 2 1

GAINSUBSATELLITE

ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

APN:353S2621

APN:353S2621

796Hz < HPF FC < 936Hz80 Hz < HPF FC < 94 Hz

ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

APN:353S2621ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

SPRK AMP. INPUT REFERRED CLIP POINT = ~-6dBFS6DB (2V/V)

AUD_LO2_L_N

LM48311_SUB_P

SPKRAMP_INSUB_N

SPKRAMP_INSUB_PAUD_LO1_R_P

SPKRAMP_SHDN

AUD_LO1_R_N

AUD_LO2_L_P

SPKRAMP_SUB_P_OUTMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 mm

AUD_LO2_R_N

LM48311_SUB_N

SPKRAMP_INR_P

SPKRAMP_INR_N

AUD_LO2_R_P

LM48311_L_PSPKRAMP_INL_P

SPKRAMP_INL_N

LM48311_L_N

=PP5V_S3_AUDIO_AMP

SPKRAMP_SHDN


SPKRAMP_SUB_N_OUTMIN_NECK_WIDTH=0.20 MM

SPKRAMP_L_P_OUTMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 mm

SPKRAMP_L_N_OUTMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 mm

=PP5V_S3_AUDIO_AMP

MIN_NECK_WIDTH=0.20 MMSPKRAMP_R_N_OUT


MIN_LINE_WIDTH=0.30 mmMIN_NECK_WIDTH=0.20 MMSPKRAMP_R_P_OUT

LM48311_R_P

AUD_GPIO_3

SPKRAMP_SHDN

LM48311_R_N

=PP5V_S3_AUDIO_AMP


AUDI0: SPEAKER AMP

C6602

16VCERM402

0.01UF10%

10%

X7R25V

CRITICAL

C66310.01UF

402

X7R25V

0.01UF

CRITICALC6611

10%

402

0.01UFC6630CRITICAL

X7R25V10%

402

X7R25V

C6610CRITICAL

0.01UF

10%

402

52 7

52 7

52 7

52 7

52 7

52 7

20%

CRITICAL

C6605

TANT16.3V47UF

2012-LLP

U6630CRITICAL

LM48311BGA

C6601CRITICAL

47UF20%6.3VTANT12012-LLPU6610

BGALM48311

CRITICAL

U6620CRITICAL

BGALM48311

48

0402

FERR-1000-OHML6631

48

FERR-1000-OHML6621

0402

X5R

0.1UF

16V

402

10%

CRITICAL

C6621

48

FERR-1000-OHM

0402

L6611

MF-LF

R6611

4021/16W5%100K

C6620

X5R10%

40216V

CRITICAL

0.1UF

48

R6610

5%MF-LF

0

4021/16W

C6603CRITICAL

47UF20%6.3VTANT12012-LLP

1UF

402

10%X5R10V

C6608

1UF

40210VX5R10%

C6609

48

L6630

0402

FERR-1000-OHM

0402

L6610FERR-1000-OHM

L6620

0402

FERR-1000-OHM

1UF

40210V

C6607

X5R10%

48

48

66 OF 109

C.0.0

051-8561

51 OF 76

2

1

21

21

21

2

1

2

1

1

2

1 2

1 2

1

2

21

1 221

21

C1

A2

A1 A3

B1B2

C2B3

C3

C1

A2

A1 A3

B1B2

C2B3

C3

1

2

C1

A2

A1 A3

B1B2

C2B3

C3

1

2

1 2

1 2

1 2

1 2

51

51 8

51

51 8

51

51 8

IN

IN

IN

IN

OUT

OUT

OUT

BI

BI

BI

BI

IN

IN

IN

OPERATING VOLTAGE 3.3

B - VCC

SHELL

SHIELDPINS

HP DETECT

GND

PHS DETECT

AUDIO

A - VIN

POF

C - GND

OUT

VCC

COM1

COM2

EN*

NC1

CB

NO1

NEG

GND

NO2

NC2

OUT

IN

OUT

IN

IN

OUT

OUT

CRITICAL BOM OPTIONTABLE_5_HEAD

PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM

TABLE_5_ITEM




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8 7 5 4 2 1

AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX

DO NOT SYNC K84. UPDATED PLACE NEARS

GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED

ANALOG AUDIO IO SWITCH

SPEAKER CONNECTORSAPN:518S0519

LEFT PIEZO

RT. PIEZO

DYN. FULL RANGE

GND STUFFING OPTIONS FOR CMOS SWITCH

APN:518S0520MIC CONNECTOR

GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED

APN:514-0750

AUD_LO_AMP_OUTL

AUD_IP_PERPH_DET_JACK

=PP3V3_S0_AUDIO

AUD_SWITCH_GND

SPKRAMP_R_N_OUT

SPKRAMP_R_P_OUT_CONN

=PP5V_S3_AUDIO

SPKRAMP_SUB_P_OUT_CONN

AUD_HP_PORT_REFMIN_LINE_WIDTH=0.4MM

AUD_CONNJ1_SLEEVEMIN_NECK_WIDTH=0.2MM

BI_MIC_P

BI_MIC_N

HS_MIC_P

AUD_CONN_GND

AUD_CONNJ1_TIPDET

AUD_J1_TIPDET_R

BI_MIC_SHIELD

AUD_LI_GND

SPKRAMP_L_N_OUT

HS_MIC_N

AUD_IP_PERPH_DET

AUD_CONN_R

AUD_J1_SLEEVEDET_R

GND_AUDIO_HP_AMP

SPKRAMP_R_N_OUT_CONN

SPKRAMP_L_P_OUT

AUD_CONN_L

AUD_CONN_GND


SPKRAMP_SUB_P_OUT

AUD_LI_R

AUD_LI_L

SWITCH_CP

SPKRAMP_SUB_N_OUT_CONN

MIN_NECK_WIDTH=0.15MM AUD_CONN_LMIN_LINE_WIDTH=0.2MM

AUD_LO_AMP_OUTR

AUD_GPIO_0

SPKRAMP_R_P_OUT

SPKRAMP_SUB_N_OUT

MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.15MM AUD_CONN_R

GND_AUDIO_CODEC

AUD_CONNJ1_MIC

AUD_CONNJ1_SLEEVEDETAUD_CONNJ1_TIPAUD_CONNJ1_RING

AUD_SPDIF_OUT

353S2803 CRITICALU67001 NEW_AUDIO_SWITCHIC, MAX14560, Dual SPDT

1 U6700 CRITICAL353S2536 OLD_AUDIO_SWITCHIC, MAX14504, Dual SPDT


AUDIO: JACK

C6701

402

5%50V

100PF

CERM

R6701

1/16W5%

MF-LF402

4.7

R6700

5%

10K

MF-LF1/16W

402

53

53

L6704CRITICAL

0402

FERR-220-OHM

L6705

0402

FERR-220-OHM

CRITICAL

L6703CRITICAL

FERR-120-OHM-1.5A

0402-LF

48

603

0

5%1/10WMF-LF

R6710

0

MF-LF603

5%1/10W

R6709

R6708

603

1/10WMF-LF

0

5%

MF-LF1/10W

R6707

603

5%

050

49

50

49

MAX14560EWC+WLP

OMIT

U6700

CRITICAL

J6704CRITICAL

78171-0003M-RT-SM

L6706FERR-1000-OHM

040253

DZ6702CRITICAL

4026.8V-100PF

J6700

CRITICALF-RT-TH

AUDIO-JACK-TRANS-CFR-K86K87

100PF

NOSTUFF

402

5%

C6707

50VCERM CERM

100PF

402

C6706NOSTUFF

5%50V

C6705

402

5%100PF

CERM50V

NOSTUFF NOSTUFF

C67045%

CERM50V

402

100PF

100PF5%

C6703NOSTUFF

CERM402

50V

NOSTUFF

C6702

CERM402

100PF5%50V

5%

OLD_AUDIO_SWITCH

1/16W

R6713

MF-LF

24K

402

R67121/16W

OLD_AUDIO_SWITCH

24K

402

5%MF-LF

XW6702SM

PLACE_NEAR=J6700:3MM

51 7

51 7

J6703CRITICAL

78171-0002M-RT-SM

48

1/16W

0R6727

MF-LF

5%

402

NOSTUFF

C6710

402X5R

1UF10V10%

R67215%

MF-LF1/16W

100K

402

52

52

1/16W

402

5%

MF-LF

0R6715

R6714

MF-LF

0

402

1/16W5%

52

52

XW6701SM


XW6700SM


C6711

CERM50V

402

10%0.0033UF

48

DZ6701402

CRITICAL

6.8V-100PF

75 53

75 53

L6701FERR-1000-OHM

0402

L6702FERR-1000-OHM

0402

J6701CRITICAL

78171-0003M-RT-SM

DZ6705402

CRITICAL

6.8V-100PF

DZ6700CRITICAL

4026.8V-100PF

DZ67034026.8V-100PF

CRITICAL

DZ67046.8V-100PF

CRITICAL

402

J670278171-0002

M-RT-SM

CRITICAL

51 7

51 7

51 7

51 7

C6700

402

6.3V

1UF10%

CERM

67 OF 109

C.0.0

051-8561

52 OF 76

2

1

4

2

1

3

1

21

2

1

21

2

5

1

3

2

4

21

21

1

2

2

1

1 2

1 2

1 2

1 2

1

2

2

1

1 2

4

21

3

1 2

1

2

1

2

2

1

2

1

2

1

2

1

2

1

2

1

82

435

671

91011

121314

1

2

21

5

1

32

4A3

C3

B4

B1

B2

C4

C2

A4

A2B3

A1

C1

1 2

1 2

1 2

1 2

21

21

21

1 2

1 2

2

1

53 48 8

50 48 8

75 53 7

75 53 7

52

53 7

49

50 48

52

53 49 48

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

IN

BI

IN

OUT

OUT

IN

GND THMENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASSINT*

SCL

D

SGD

SG




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Apple Inc.

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345678

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8 7 5 4 2 1

PIN COMPLEX

PORT B RIGHT(BUILT-IN MIC)

HP=80HZ

HP=80HZ, LP=8.82KHZPORT B LEFT(HEADSET MIC)

PULLUPS ON MCP PAGE

0X0C (12)

MCP79 GPIO_17 (PERIPH DETECT)

PORT B DETECT(SPDIF DELEGATE)

PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA

VOLUME

0X05 (5)

0X03 (03)

0X0D (13,B,RIGHT)

CONVERTER

0X0A (10)

0X10 (16)

BUILT-IN MIC

SATELLITES

LINE IN

HP/LINE OUT 0X02 (2)

0X05 (5)

0X04 (4)

CODEC INPUT SIGNAL PATHS

FUNCTION

FUNCTION

0X03 (3)

N/A

GPIO_3

0X06 (6)

NC

0X0D (B)

0X09 (A)

DET ASSIGNMENTMUTE CONTROL

0X0B (11)

0X09 (9,A)

0X09 (A) AND UI ELEMENT

N/A

SUB

SPDIF OUT

0X04 (4) N/A

N/A

CONVERTER

0X02 (2)

HEADSET MIC

0X06 (6)

GPIO_3

0X0D (13,V22,B,LEFT)

GPIO_0 AND GPIO_1

GPIO_0 AND GPIO_1

VREF/ENABLE

N/A

NC

MIC_BIAS (80%)

MCP79 GPIO_38MCP79 GPIO_4 (LOAD DETECT)

DET ASSIGNMENT

PORT A DETECT (HEADPHONES)

APN:353S2256

DRC MIKEY

0X08 (8)

APN:376S0613

EXTRACTION NOTIFICATION CKT

PIN COMPLEX

CODEC OUTPUT SIGNAL PATHS

=I2C_MIKEY_SCL

AUD_I2C_INT_L

HS_MIC_BIAS

HS_SW_DET

GND_AUDIO_CODEC

AUD_IPHS_SWITCH_EN

HS_RX_BP

HS_MIC_N

GND_AUDIO_CODEC BI_MIC_LO_F

AUD_MIC_IN_L_P

AUD_MIC_IN_L_N

AUD_PERPH_DET_R

BI_MIC_SHIELD

AUD_MIC_IN_R_N

GND_AUDIO_CODEC

BI_MIC_HI_F

BI_MIC_N

HS_MIC_P

=PP3V3_S0_AUDIO

=I2C_MIKEY_SDA

MIC_BIAS_FILT

HS_MIC_HI_RC

AUD_J1_TIPDET_INV

AUD_IP_PERPH_DET

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

AUD_J1_SLEEVEDET_R

AUD_J1_SLEEVEDET_INV

AUD_IP_PERIPHERAL_DET

PERPH_DET_FILT

GND_AUDIO_CODEC

AUD_J1_SLEEVEDET_R

AUD_OUTJACK_INSERT_L

PP3V3_S0_AUDIO_F

AUD_J1_DET_RCAUD_J1_TIPDET_R

PP3V3_S0_AUDIO_F

AUD_PORTA_DET_L AUD_PORTB_DET_L

AUD_SENSE_A

GND_AUDIO_CODEC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.10MMMIN_NECK_WIDTH=0.10MM

PP3V3_S0_HS_RX

BI_MIC_PAUD_MIC_IN_R_P


VOLTAGE=3.3VPP3V3_S0_AUDIO_F

GND_AUDIO_CODEC

AUD_CODEC_MICBIAS

GND_AUDIO_CODEC

AUDIO: JACK TRANSLATORSSYNC_DATE=02/16/2010SYNC_MASTER=AUDIO

R6885NOSTUFF

10K

402

1/16WMF-LF

5%

R6862

402

1/16W5%300K

MIKEY

MF-LF

R68015%1/16W

300K

402MF-LF

R6865

MF-LF1/16W5%

402

100K

MIKEY

R6864220K

MIKEY

402

5%1/16WMF-LF

C6860

10VCERM402

20%0.1UF

MIKEY

R6860MIKEY

5%1/16W

15K

MF-LF402

Q6802SSM6N15FEAPE

MIKEY

SOT563

Q6802MIKEY

SOT563SSM6N15FEAPE

C6880

402

CRITICAL

CERM

1UF10%6.3V

MIKEY

U6880

MIKEY

DRCCD3275

53 52 48 8

L6862FERR-1000-OHM

0402

C6861

402 CERM

0.1UF20%10V

R6861MIKEY

0

MF-LF1/16W5%

402

17

R68532.4K

MF

1%1/16W

402-1

R6850100

MF-LF1/16W1%

402

C6851

X5R

CRITICAL

0.1UF

10%

402

25V

48

C6886

X5R

CRITICALMIKEY

0.1UF

10%25V

402

R6884

1/16WMF-LF

5%

2.2K

MIKEY

402

19

38

38

19 C68822.2UF

6.3VTANT402

CRITICAL

MIKEY

20%

L6880

0402

MIKEY

FERR-1000-OHM

C6881

CERM40210%

0.01UF

MIKEY

16V

R6880NOSTUFF

402

5%

MF-LF

100K

1/16W

R6881

MIKEY

402

1%

MF-LF

1K

1/16W

48

XW6880

PLACE_NEAR=C6886:3MM

SM

C6883CRITICAL

0.1UF

X5R

10%25V

MIKEY

402R6883100K5%

MIKEY

402MF-LF1/16W

C6884

X7R 40225V

MIKEY

0.0082UF10%

CRITICAL

C6885MIKEY

27PF

CRITICAL40250V5%

CERM

R68822.2K

1/16W5%

MIKEY

402MF-LF

75 52

75 52

L6850FERR-1000-OHM

0402

L6851FERR-1000-OHM

0402

C6852CRITICAL

402TANT6.3V20%2.2UF

75 52 7

52 7

75 52 7

48

48

48

XW6851


SM

R6852

402

100K5%1/16WMF-LF

C6853

402 CERM

0.001UF50V

CRITICAL

10%

C6850

10%25V

402X5R

0.1UF

CRITICAL

C6854

50VCERM 4025%27PF

CRITICAL

R68512.4K

1/16W1%

402-1MF

Q6801

SOT563SSM6N15FEAPE

Q6801SSM6N15FEAPE

SOT563

Q6800

SOT563SSM6N15FEAPE

Q6800SSM6N15FEAPE

SOT563

R6805

402

20.0K1%

MF-LF1/16W

53 52

48

C6802

16VCERM

0.01UF10%

402

R6804

5%

MF-LF1/16W

220K

402

R6803

MF-LF402

220K

1/16W5%

R6806

MF-LF

1%1/16W

39.2K

402

52

R6802

5%

402MF-LF1/16W

47K

C680110V20%

CERM

0.1UF

402

68 OF 109

C.0.0

051-8561

53 OF 76

2

1

1 2

1

2

1 2

1

2

2

1

1

2

3

45

6

12

3

45

6

12

1 2

2

1

1 2

2

11

2

1 2

1

2

21

21

1

2

2

1

2

11

2

1 2

1 2

1

2

1

22

1

21

1

2

1 2

1 2

1 2

1 2

1 2

1 2

2

1

21

9

11

8

4

3

5

1

2

107

6

2

1

6

12

3

45

1 2

2

1

1

21

2

1

2

1

2

1

2

53 52 49 48

53 52 49 48

53 52 49 48

53 52 48 8

52

53 52 49 48

53 52

53 52 49 48

53

53

53 52 49 48

53

53 52 49 48

53 52 49 48

VCC

EXTINT

NCGND

BI

Y

B

A

P3

P4

P5

P6

P7

P8

P1

P2

P9

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

NC

OUT





36

BRANCH

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Vout = 3.425V

250MA MAX OUTPUT

(Switcher limit)

339S0114

<Rb>

DO NOT SYNC WITH K84. R6900,C6960,SIGNAL NAMES CHANGED. HALL EFFECT CONNECTOR CHANGED.

- Conn APN:518S0788- MCO: 056-3515- PCBF: 820-2801- BOM: 639-0680

Assembly APN: 339S0114

BATTERY CONNECTOR

Vout = 1.25V * (1 + Ra / Rb)

Supply needs to guarantee 3.31V delivered to SMC VRef generator

518-0359

NC

<Ra>

3.425V "G3Hot" Supply

PN: 607-6831 for WCPM. PN: 339S0114 for schematic/board layout

PROTO 1: STUFFING K87 HALL EFFECT ASSEMBLY ONTO K87 PADSPROTO 0: STUFFING K84 CONNECTOR ONTO MODIFIED K84 PADS

518S0656

1-Wire OverVoltage Protection

HALL EFFECT ASSEMBLY

MagSafe DC Power Jack


SWITCH_NODE=TRUE

DIDT=TRUEP3V42G3H_SW

SMC_BC_ACOK_VCC

ADAPTER_SENSE

SMC_LID

=PP3V42_G3H_HALL

=SMBUS_BATT_SDA

P3V42G3H_FB

PPVBAT_G3H_CONN

SMC_LID_R

SYS_DETECT_L

=PP3V42_G3H_ONEWIRE

P3V42G3H_BOOSTDIDT=TRUEMIN_LINE_WIDTH=0.3 mm

VOLTAGE=18.5V

PPDCIN_G3H_OR_PBUS_RMIN_NECK_WIDTH=0.3 mm

PPDCIN_G3H_OR_PBUS

SMC_BC_ACOK

ADAPTER_SENSE_R

SYS_ONEWIRE

=PP18V5_DCIN_CONNPP18V5_DCIN_FUSEMIN_NECK_WIDTH=0.20mmMIN_LINE_WIDTH=1mm

VOLTAGE=18.5V

=SMBUS_BATT_SCL

=PP3V42_G3H_REG

SUB ASSY - HALL EFFECT, K86 K87 J6955 CRITICAL607-6831 1

SYNC_MASTER=MASTER

DC-In & Battery Connectors

SYNC_DATE=MASTER

C6971

25VNP0-C0G402

1000PF5%

C6972

25VNP0-C0G402

1000PF5%

C69701000PF5%25VNP0-C0G402

43 36 35

HALLEFFECT-ASSY-K87J6955

F-ST-SM

OMITR6905

1

1/8W5%

805MF-LF

C6990

25V10%

805

BYPASS=U6990.6:5:2 MMX5R-CERM

2.2UF

U6990LT3470A

DFN

CRITICAL

402

5%50VCERM

C699522pF

0.22uF

X5R6.3V20%

402

C6994

1%200K

MF-LF402

1/16W

R6996CERM805

20%6.3V

CRITICALC699922UF

R6995

402

1%1/16W

348K

MF-LF

33UH

CRITICAL

CDPH4D19FHF-SM

L6995

25V10%

603-1X5R

1UF


C6960

NO STUFF

100K

MF-LF402

1%1/16W

R6900

BAT-K24M-RT-TH

J6950CRITICAL

R69292.0K1/16W

1

5%

MF-LF402

2

402

1/16W

0

MF-LF

5%

R6961

C6955

CERM

NOSTUFF

0.001UF

402

10%50V

1/16W5%

402MF-LF

10KR6950

TC7SZ08AFEAPE

U6901

SOT665

35

MAX9940SC70-5

U6900

PLACEMENT_NOTE=PLACE NEAR U6901

CERM10V20%

402

0.1UFC6908

SC-75

NOSTUFFCRITICAL

D6950RCLAMP2402B

CRITICAL

1206-1

F69056AMP-24V

0.1UF

X5R402

10%25V


C6950

402

0

MF-LF

5%1/16W

R6928

J690078048-0573

M-RT-SM

CRITICAL

603CERM

20%

C69050.01UF50V

69 OF 109

C.0.0

051-8561

54 OF 76

2

13

2

1

4

5 1 2

2

1

21

3

21

2

1

1

54

2 3

3

5

1

4

2

1

2

2

1

12

3

4

5

6

7

8

1

2

9

10

11

12

13

1

2

2

1

21

1

2

2

1

1

2

2

1

2

1

4

36

2

8

57

1

9

2

1

1 2

1

43

2

65

2

1

7

8

38

55 7

7

7

8

55

36 35 9

8 7

38

8

OUT

OUT

IN

BI

OUT

IN

D

G

S

S

D

G

D

G

S

D

G

S

IN

AMON

BMON

ACOK

LGATE

PHASE

BOOT

SGATE

AGATE

CSIP

CSIN

DCIN

VNEG

CSOP

CSON

THRM_PAD

PGND

VDDPVDD

BGATE

UGATE

ICOMP

VCOMP

ACIN

SDA

VFRQ

CELL

VHST

SCL

SMB_RST_N




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

FROM ADAPTER

* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE

30mA max load

APN 353S2929

36V/V

ACIN pin threshold is 3.2V, +/- 50mV

Reverse-Current Protection

(PPVBAT_G3H_CHGR_R)

K87 NOTES : R7050 APN 107S0075

(CHGR_DCIN)

(CHGR_CSO_P)

(CHGR_BGATE)

(GND)

(CHGR_CSO_N)

(OD)

TO SYSTEM

This node is powered

(PPVBAT_G3H_CHGR_R)

* PBUS through Q7085,

through body diodes:

* DCIN through Q7080.

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

Charger TOP FETs and

Q7055.

Inrush Limiter

TO/FROM BATTERY

Max Current = 8A

f = 400 kHz

(CHGR_SGATE) (CHGR_AGATE)

Divider sets ACIN threshold at 13.55V

Input impedance of ~40K meets

20V/V

(AGND)

K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT

sparkitecture requirements

Float CELL for 1S

DIDT=TRUEGATE_NODE=TRUE

CHGR_LGATE

DIDT=TRUE

CHGR_UGATEGATE_NODE=TRUE

CHGR_RST_L


CHGR_SGATE

PP5V1_CHGR_VDDP

VOLTAGE=5.1VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm

CHGR_CSI_R_N

CHGR_VFRQ


DIDT=TRUESWITCH_NODE=TRUE

CHGR_PHASE

CHGR_BGATE

DIDT=TRUE

CHGR_BOOT

CHGR_AMON

CHGR_BMON

CHGR_CSI_N

=SMBUS_CHGR_SDA

=SMBUS_CHGR_SCL

CHGR_PHASE_RCDIDT=TRUE

PPVBAT_G3H_CHGR_REG


VOLTAGE=12.6V

=PPBUS_G3H

PPVBAT_G3H_CONNMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mmVOLTAGE=12.6V

MIN_NECK_WIDTH=0.3 mmMIN_LINE_WIDTH=0.3 mmCHGR_SGATE_DIV

GND_CHGR_AGND


PPDCIN_G3H_CHGRMIN_LINE_WIDTH=0.6 mm

CHGR_CSI_R_P

CHGR_CSO_R_P

CHGR_CSO_R_N

CHGR_DCIN_D_R

CHGR_AGATE_DIVMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.4 mmMIN_LINE_WIDTH=0.6 mmPPDCIN_G3H_INRUSH

VOLTAGE=18.5V

CHGR_VCOMP

PPDCIN_G3H_OR_PBUS

VOLTAGE=18.5V


CHGR_CSO_N

CHGR_VCOMP_R

=CHGR_ACOK

CHGR_DCIN

=PP3V42_G3H_CHGR

SMC_RESET_L

CHGR_VNEG

CHGR_CSO_P

CHGR_CELL

CHGR_VNEG_R


CHGR_AGATE

CHGR_CSI_P



PP5V1_CHGR_VDD

=PPDCIN_S5_CHGR

VOLTAGE=0VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmGND_CHGR_AGND

CHGR_ACIN

MIN_NECK_WIDTH=0.4 mmMIN_LINE_WIDTH=0.6 mmPPVBAT_G3H_CHGR_R

VOLTAGE=12.6V

CHGR_ICOMP

PBus Supply & Battery Charger

SYNC_MASTER=(K6_MLB) SYNC_DATE=(11/06/2009)

TQFNU7000

CRITICAL

ISL6259

37 36 35

MF-LF402

1/16W

R70000

5%

SO-8CRITICALSI7149DP

Q7080 Q7085SI7149DP

SO-8 CRITICAL

L7030CRITICAL

4.7UH-9.5A

IHLP4040DZ-SM

C7036

X5R25V10%1UF

603-1

C7035

X5R25V10%

603-1

1UF

MF-LF

R7005

402

20

5%1/16W

C7040CRITICAL

20%39UF-0.027OHM

POLY16V

B1A-SM

Q7030

LFPAK-SM

RJK0332DPB-01

CRITICALR7012

1%1K

402MF-LF1/16W

1%470KR7085

1/16WMF-LF

402

1/16W5%100K

402MF-LF

R70800.1UF

10%

X5R25V

402

C7085

D7005BAT30CWFILM

CRITICAL

SOT-323

NO STUFFR7013

1K

MF-LF

1%

402

1/16W

Q7055

SO-8SI7137DP

CRITICAL

62

NO STUFF R7002

MF-LF

5%100K

402

1/16W

C7045

10%50VX7R402

0.001UF

PLACE_NEAR=L7030.2:2MM

R7039

5%

MF-LF

180

1/10W

603

NO STUFF

470PF10%

C7039

402CERM50V

NO STUFF

C7037

50V

0.001UF10%

402X7R

PLACE_NEAR=Q7030.5:1.5MM

0.5%

R7020CRITICAL

0.021WMF0612-1

R7050

0612-1MF1W

0.010.5%

9

C7026

50VCERM402

10%0.001UF

C7050

X5R16V10%1UF

402

C7011

10%

402CERM16V

0.01UF

38

38

40

40

C7005

20%0.22UF

603X5R25V

R7081

5%

MF-LF1/16W

62K

402

R7086

1%1/16W

402MF-LF

332K

R7052402MF-LF5% 1/16W

0

R7051MF-LF1/16W

2.24025%

F7040

1206

8AMP-24V

CRITICAL

C7031

20%

POLY-TANT25V

22UF

CRITICAL

CASE-D2-SM

C7030

25V20%

POLY-TANT

22UF

CRITICAL

CASE-D2-SM

10

MF-LF

5%1/16W

402

R7021

10R7022

MF-LF1/16W

402

5%

LFPAK-HFRJK0305DPB

CRITICAL

Q7035

C7025

PLACE_NEAR=U7000.25:2mm

CERM10V

0.22UF10%

402

0.047UF

402

C7020

10%

CERM10V

C70220.1UF

25V

402X5R

10%

C70210.1UF

25VX5R402

10%

402

10V10%1UF

X5R

C7001

SM


XW7000


R7010

1/16WMF-LF

30.1K

402

1%

R70014.7

5%

402MF-LF1/16W

C7000

10V10%1UF

402-1X5R

C7002

10%

X5R

1UF

10V

402

402

1/16W

56.2KR7015

1%

MF-LF

50V

0.001UFC7015

10%

CERM402

3.01KR7016

1%

MF-LF402

1/16W

C7016470PF

50VCERM

10%

402

C7042

10%0.068UF

10VCERM402

R7011

402

1/16W

9.31K

MF-LF

1%

70 OF 109

C.0.0

051-8561

55 OF 76

1

2

2

1

2

1

1

2

2

1

1

2

2

1

2

1

1 2

1

2

1 2

2

1

2

1

2

1

2

1

2

1

1 2 3

5

4

1 2

1 2

1

2

1

2

21

1 2

1 2

1

2

1

2

2

1

2

1

2

1

2

1

43

21

1

24

3

2

1

2

1

1

2

2

1

1

2

4

3

521

1

2

3

1

2

2

11

2

1

2

1

2

4

321

5

1

2

1 2

2

1

2

1

21

4

3

521

4

3

5 21

1 2

9

15

14

21

23

25

26

1

28

27

2

8

18

17

29

22

20

19

16

24

5

7

3

10

4

6

12

11

13

74

74

8

54 7

55

74

74 40

74 40

54

74

62 8

74

74

8

55

IN

IN

D

SG

D

SG

S

D

G

G

D

S

D1

G1

S2

G2

S1/D2

DRVH1

SKIPSEL

VBST1

GND THRM_PAD

ENTRIP1

VFB1

VO1

DRVL1

LL1

EN0

VCLK

ENTRIP2

PGOOD

VO2

VFB2

DRVL2

LL2

DRVH2

VBST2

VREG5

VREG3

VREFVIN

TONSEL




36

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REVISION

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DR


SHEET

PAGE TITLE

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Apple Inc.

PAGE


A

B

C

345678

D

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8 7 5 4 2 1

MAX CURRENT = 9.1A

SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.

ROUTING NOTE:

5V_S3/3.3V_S5 POWER SUPPLY

Place XW7201 between Pin 15 and Pin 25 of U7200.

VOUT = (2 * RC / RD) + 2VOUT = (2 * RA / RB) + 2

Place XW7203 by Pin1 OF L7260.

<RA>

Place XW7205 by C7252.

PWM FREQ. = 300 KHZ

Place XW7204 by Pin 2 of L7220.

<RD>

ROUTING NOTE:

<RB>

ROUTING NOTE:

ROUTING NOTE:

ROUTING NOTE:

NOTE: DONT SYNC THIS PAGE FROM T27

NC

PWM FREQ. = 375 KHZ

MAX CURRENT = 13.3A


<RC>

=PP3V3_S5_REG



DIDT=TRUE

3V3S5_LL

P5V3V3_PGOOD

5V_S3_VFB

3V3S5_ENTRIP

5V3V3S5_REG3

GND_5V3V3S5_SGNDVOLTAGE=0V


5V_S3_ENTRIP

MIN_NECK_WIDTH=0.25 MMVOLTAGE=5V

MIN_LINE_WIDTH=0.5 MMPP5V_S5_LDO

5V3V3_REG_EN

=PPVIN_S5_3V3S5

3V3S5VO2

5VS3_3V3S5_VREF

=PPVIN_S3_5VS3

5V_S3_VFB_XW7203

5V_S3_DRVL

DIDT=TRUE

3V3S5_VBSTDIDT=TRUE



3V3S5_VBST_RMIN_NECK_WIDTH=0.2 MM


=P5V3V3_REG_EN

=P3V3S5_EN_L

3V3S5_VFB_R7270

GND_5V3V3S5_SGND

=P5VS3_EN_L

3V3S5_DRVH

MIN_NECK_WIDTH=0.2 MMDIDT=TRUEMIN_LINE_WIDTH=0.6 MM

3V3S5DRVL

DIDT=TRUE

=PPVIN_S3_5VS3


MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

5V_S3_VBST

5V_S3_VO1

DIDT=TRUE


MIN_LINE_WIDTH=0.6 MM5V_S3_DRVH

5V_S3_LL

DIDT=TRUE



=PP5V_S3_REG

5V/3.3V SUPPLYSYNC_MASTER=(K6_MLB) SYNC_DATE=(10/27/2009)

402

10VCERM

10%0.22UFC7271

20%

C72701UF10V

603CERM

603-1

10%

X5R25V

1UFC7272

402


1/16W1%75K

MF-LF

R7272

MF-LF402

86.6K1%1/16W

R7271

TPS51125

CRITICAL

QFN

3V3S5_VFB

U7200

PCMC063T-SM

4.7UH-10A

CRITICAL

L7220

X5R603

10UF20%6.3V

C7290

603-1

1UF10%

X5R25V

C7281

10K1%

402MF-LF1/16W

R7268

1/16W

402MF-LF

1%15.0KR7267

10%16V

0.1UF

X5R402

C7260603-1X5R25V10%1UFC7241

R7269

402

10K1%1/16WMF-LF

1%

402MF-LF1/16W

6.49KR7270

CRITICAL

PCMB104E4R7-SM

4.7UH-13A-15MOHM

L7260

C725020%10UF

X5R603

6.3V

CRITICALWPAKRJK0384DPAQ7220402 5% 1/16W MF-LF

0R7220

CRITICAL

PWRPK-12128SIS426DNQ7261

PWRPK-1212-8-SMSIS424DN

CRITICAL

Q7260

CRITICAL

39UF-0.027OHM20%16VPOLYB1A-SM

C7280

CRITICAL

C7251150UF

6.3V20%

B1A-SMPOLY

220UF20%6.3VELECD1A-SM

CRITICAL

C7291

CRITICAL

C724039UF-0.027OHM

POLYB1A-SM

16V20%

PLACE_NEAR=L7220.2:1.5 MM

0.001UF50VCERM402

20%

C725350VCERM

20%

402

0.001UF


C7293

402

50V

0.001UF

CERM

20%

PLACE_NEAR=Q7220.2:1.5 MM

C7242

50V

402

20%0.001UF

CERM


C7282

C7220

DIDT=TRUE

0.1UF402

16V10%

X5R

1/16W

402

5%100K

MF-LF

R7273

SM

XW7204

SM

XW7205

SM

XW7203

SM

XW7202

SSM6N15FEAPE

SOT563

Q7221

SSM6N15FEAPE

SOT563

Q7221

62

62


XW7201SM

10UF

603

20%

X5R6.3V

C7273

72 OF 109

C.0.0

051-8561

56 OF 76

2

1

1 2

6

12

3

45

12

12

12

12

1

2

12

2

1

2

1

2

1

2

1

1

2

1

2

1

2

1

2

4

3 2 1

5

4

13 2

5

1 2

2

1

3 4 5

6

7

2

1

21

1 21 2

2

1

12

1 2 1 2

2

1

2

1

21

21

14

22

15

25

1

2

24

19

20

13

18

6

23

7

5

12

11

10

9

17

8

316

4

1

2

1

2

2

1

2

1

2

1

8

62

56

8

56 8

62

56

56 8

8

MODE

VDDQSNSCOMP

NC0

NC1

VTTSNS

VTT

VTTREF

PGOOD

S3

S5

VTTGND THRM_PAD GND CS_GNDPGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILTV5IN

SYM (2 OF 2)

IN

IN

OUT

NCNC

S

D

G

G

D

S

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

19A MAX OUTPUT

f = 400 kHz

(DDRREG_DRVH)

SEL_1V5=0: Req = RbVout = 0.75V * (1 + Ra / Req)

(DDRREG_LL)

SEL_1V5=1: Req = Rb || Rc

VOUT = 1.501V

<Ra>

<Rb>

(DDRREG_CSGND)

Vout = VDDQSNS/2

Vout = VTTREF

1.5V/0.75 DDR3 POWER SUPPLY

NOTE: DONT SYNC THIS PAGE FROM T27. C7330 AND C7331 IS CHANGED TO OSCON CAPS

(DDRREG_VDDQSNS)

(DDRREG_DRVL)

(DDRREG_FB)

VTT Enable

VDDQ PGOOD

VDDQ/VTTREF Enable

10mA max load

NOTE: DONT SYNC THIS PAGE FROM K6 REMOVED R7380

=PPDDR_S3_REG


DDRREG_DRVHGATE_NODE=TRUEDIDT=TRUE


DDRREG_VDDQSNS


DIDT=TRUE

DDRREG_VBSTMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.17 mm

DDRREG_CS

=PPVIN_S3_DDRREG

DIDT=TRUEGATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm


DDRREG_DRVL

SWITCH_NODE=TRUEDDRREG_LLDIDT=TRUE MIN_NECK_WIDTH=0.17 mm



GND_DDRREG_SGND

VOLTAGE=0V


DDRREG_FB

DDRREG_CSGNDMIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.1 mm

=PPVTT_S3_DDR_BUF

=PPVTT_S0_DDR_LDO

DDRREG_VTTSNS

VOLTAGE=5VMIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=0.6 mmPP5V_S3_DDRREG_V5FILT

=PPVIN_S0_DDRREG_LDO

=DDRVTT_EN=DDRREG_EN

=PP5V_S3_DDRREG

DDRREG_PGOOD

1.5V/0.75V DDR3 SUPPLYSYNC_MASTER=(K6_MLB) SYNC_DATE=(11/06/2009)

63 8

1%

402

15.0K

MF-LF1/16W

R7321

50V

402X7R

10%0.001UFC7320

CRITICAL

POLYB1A-SM

39UF-0.027OHM

16V20%

C7331

16VPOLYB1A-SM

CRITICAL

20%39UF-0.027OHMC7330

CRITICAL

PWRPK-12128SIS426DNQ7335

Q7330CRITICAL

SIS424DNPWRPK-1212-8-SM

PLACE_NEAR=U7300.3:1 mm

SM

PLACE_NEAR=U7300.25:1 mm

XW7300

1UF10%10VX5R

402-1

C7305

0.001UFC7346

402

10%50VX7R

0.001UF


50VX7R402

10%

C7333

6.3V

10UF20%

603X5R

C7345

TANT

CRITICAL

20%330UF2.5V

CASE-B2-SM

C7340

CRITICAL

CASE-B2-SM

2.5VTANT

330UF20%

C7341

20%6.3VX5R603

10UFC7355


SMXW7345

CRITICAL

1.0UH-13A-5.6MOHM

PCMB065T-SM

L7330

62

10K1%

402MF-LF1/16W

R7310

62

805

10%

X5R10V

4.7UFC7300

62

10%16VX5R402

0.033UFC7350


SMXW7335

SM


XW7360

CRITICAL

22UF

603X5R-CERM

6.3V20%

C736022UF

603X5R-CERM6.3V20%

CRITICALC7361

402MF-LF1/16W

4.7

5%

R7305

CRITICAL

TPS51116QFN

U7300

25V

1UF

603-1X5R

10%

C7332

MF-LF

1%

402

15.0KR7320

1/16W

10%

X5R402

0.1UF

16V

C7325

73 OF 109

C.0.0

051-8561

57 OF 76

1 2

1

2

2

1

4

86

7

12

2

24

5

13

10

11

1

25 3

17

18

16

20

19

21

9

22

23

14

15

1 2

2

1

2

1

1 2

1 2

2

1

2

1

1

2

21

2

1

2

1

1

2

1

2

2

1

2

1

2

1

2

1

1 2

4

321

5

4

1 32

5

1

2

1

2

2

1

1

2

8

29

29 8

8

8

8

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT*

NTC

VR_ON

PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3

VID2

VID4

VID5

VID6

PGND2

VIN VDD PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1

BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPADGND

CLK_EN*

IMON

S

G

D

S

G

D

D

G

S

D

G

S

IN

IN

IN

OUT

OUT

IN





36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MIN_LINE_WIDTH

NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.IMVP6:1PHASE BOM

(IMVP6_VO)

MIN_NECK_WIDTH

DPRSTP*

0 1

DPRSLPVR

MIN_LINE_WIDTH

1-PHASE CCM0

PIMA104E-R36MN0R755

PIMA104E-R36MN0R755

(IMVP6_PHASE1)

(IMVP6_VSUM)

1

1-PHASE DCM

DCR=0.75MOHM

DCR=0.75MOHM

PSI*

(NC)

10

1

1

0

0

1

1-PHASE DCM

(IMVP6_PHASE2)

(IMVP6_ISEN1)

(IMVP6_ISEN2)

ERT-J1VR103J

2-PHASE CCM

OPERATION MODE

0

MIN_NECK_WIDTH

MIN_NECK_WIDTH

MIN_LINE_WIDTH

(IMVP6_VW)

2PHASE

Max Current

(IMVP6_COMP)

PWM Freq.

MIN_NECK_WIDTHMIN_LINE_WIDTH

FROM SMC

R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED

Load Line -2.107 mV/A

300 kHz

-4 mV/A

1PHASE

300 kHz

17.6 A44 A

(GND)

(GND)

(IMVP6_VO)

IMVP6 CPU VCORE REGULATOR

(IMVP6_FB)

PLACEMENT_NOTE=PLACE CLOSE TO PIN 21 OF U7400

XW7400OMIT

SM

R7400

402

1/16W1%10K

MF-LF

IMVP6:2PHASE

R74013.65K

MF-LF1/16W

402

1%

X5R402

10%16V

0.1UFC7415

R7416

402

1%

MF-LF

13.7K

IMVP6:2PHASE

1/16W

1%1/16W

402

10.5K

MF-LF

R7415

IMVP6:2PHASE

10K

402MF-LF

1%1/16W

R7405

402CERM-X5R

0.22uF

6.3V

IMVP6:2PHASE

10%

C7404

R7443IMVP6:2PHASE

3.65K1%

MF-LF1/16W

402

0.1UF

X5R16V

C742710%

402

1/16W

10

MF-LF402

R74205%

R7412

1/16WMF-LF

5%

402

10CERM402

1UF10%6.3V

C7426

CERM

0.01UF

402

10%16V

C7496

R7421

MF-LF

10

402

5%1/16W X5R

402

10%16V

0.1uFC7430

IMVP6:2PHASE

1K

MF-LF

1%1/16W

402

R7413

IMVP6:2PHASE

1/16W

402

1%

MF-LF

1KR7409

IMVP6:2PHASE

1/16W1%

402MF-LF

255R7411

IMVP6:2PHASE

CERM

C7414470PF

402

10%50V

IMVP6:2PHASER741497.6K1/16W1%

402MF-LF

402

25V5%

CERM

IMVP6:2PHASEC7413220PF

0.001UF

CERM402

10%50V

C7407 R74106.81K

MF-LF402

1%1/16W

402MF-LF1/16W

5.90KR7417

IMVP6:2PHASE

1%R74181K

402

1/16W1%

MF-LFCERM50V5%180pFC7429

402

C7428

CERM-X5R402

0.47UF10%6.3V

IMVP6:2PHASE

2

1

C7432

50VCERM

0.001UF

402

20%

R74220

4021/16WMF-LF5%

MF-LF4021/16W

5%R74230

0.047UF

X7R

10%

IMVP6:2PHASEC7434

16V

402

10UF

X5R603

20%6.3V

C7435

402X7R16V10%0.015uFC7405 R7408

147K

MF-LF402

1%1/16W

IMVP6:2PHASE

0.001UF

CERM402

10%50V

C740610%0.001UF

NO STUFF

50V

C7416CERM402

1%

MF-LF402

1/16W

R74303.92K

2

0.22uF10%

6.3VCERM-X5R

4021

C7421

10%6.3V

402CERM-X5R

C7403

IMVP6:2PHASE

0.22uF

MF-LF402

5%1/16W

R74041

1

MF-LF402

5%1/16W

R7407

IMVP6:2PHASE

0603-LF

10KOHM-5%R7431CRITICAL

R74451%

402MF-LF1/16W

499

0

MF-LF402

5%

R7425

1/16W

0

MF-LF402

5%1/16W

R7424

33UF

POLY-TANTCASED2E-SM

16V20%

C7409CRITICAL

39UF-0.027OHM

B1A-SM

16VPOLY

20%

CRITICALC7417

CASED2E-SM

CRITICAL

16V20%33UF

IMVP6:2PHASE

C7408

POLY-TANT

10%25V

603-1X5R

1UFC7418

IMVP6:2PHASE

25V

603-1

1UF

X5R

10%

C7411

QFN

ISL9504BCRZ

U7400CRITICAL

402

1/16W

2.0K

MF-LF

5%

R74470.001UF

CERM402

20%50V

C7420

402

PLACEMENT_NOTE=PLACE C7419 ACROSS PINS 1/2/5/6 OF Q7400 AND PINS 3/4 OF Q7401

50V20%

CERM

0.001UFC7419

IMVP6:2PHASE

0.001UF

CERM402

50V20%

C7422

PLACEMENT_NOTE=PLACE C7422 ACROSS PINS 1/2/5/6 OF Q7402 AND PINS 3/4 OF Q7403

PLACEMENT_NOTE=PLACE C7423 CLOSE TO PIN 2 OF L7401

0.001UF50V20%

402CERM

C7423

16V20%

CRITICAL

POLYB1A-SM

IMVP6:2PHASE

C740139UF-0.027OHM

CRITICAL

IRF6710S1

Q7400

Q7402IRF6710

S1

CRITICALIMVP6:2PHASE

DIRECTFET-MX

CRITICAL

IRF6795Q7401

IMVP6:2PHASE

DIRECTFET-MXIRF6795

CRITICALQ7403

0.36UH-20%-40A-0.00075OHM

CRITICAL

PIMA104E-SM

L7400

0.36UH-20%-40A-0.00075OHMCRITICAL

PIMA104E-SM

IMVP6:2PHASEL7401

PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7400

OMITXW7401SM

SM

OMITXW7402


XW7403


OMIT

SM

OMIT

SMXW7404


20%

CERM50V

402

C74310.001UF

402

C74330.001UF

20%50V

CERM

2

1

IMVP6:1PHASE

402

05%1/16WMF-LF

R7426

10 14 69

10

35

40

25

14 69


IMVP6 CPU VCore Regulator

SYNC_DATE=(11/18/2009)

CAP,CER,.22UF,20,6.3V,X5R,0402 IMVP6:1PHASE132S0080 C74281

RES,MTL FILM,1/16W,255 OHM,1,0402,SMD,LF114S0160 IMVP6:1PHASER74111

RES,MTL FILM,1/16W,1.58K,1,0402,SMD,LF114S0236 1 R7409 IMVP6:1PHASE

RES,MTL FILM,1/16W, 16.9K, 1,0402,SM,LF1 IMVP6:1PHASE114S0336 R7416

RES,MTL FILM,1/16W,8.25K,1,0402,SMD,LF1114S0307 IMVP6:1PHASER7417

131S1027 C74131 IMVP6:1PHASECAP,CER,100PF,5%,50V,CC0402

IMVP6:1PHASECAP CER 470PF,+/-10%,50V,0402,SMD C7406132S4720 1

IMVP6:1PHASERES,MTL FILM,1/16W,97.6K,1,0402,SMD,LF R7414114S0410 1

CAP,CER,1000PF,50V,10%,X7R,0402,SMD132S0045 IMVP6:1PHASEC74141

CAP,X5R,0.1UF,10%,16V,04021132S0099 C7434 IMVP6:1PHASE

IMVP6_VO

IMVP6_VSUM

=PP5V_S0_CPU_IMVP

=PPVIN_S5_CPU_IMVP

CPU_VID<1>

VOLTAGE=3.3V


PP3V3_S0_IMVP6_3V3

CPU_VID<4>

VR_PWRGOOD_DELAY

VOLTAGE=12.6V


PPVIN_S5_IMVP6_VIN

IMVP6_OCSET

DIDT=TRUEIMVP6_UGATE2

IMVP6_ISEN1

DIDT=TRUE

IMVP6_LGATE1

DIDT=TRUE

IMVP6_PHASE2

IMVP6_VDIFF_RC

GND_IMVP6_SGND

PM_DPRSLPVR

VOLTAGE=5VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MMPP5V_S0_IMVP6_VDD

DIDT=TRUE

IMVP6_LGATE2

IMVP6_COMP_RC

CPU_VCCSENSE_N

CPU_VCCSENSE_P

IMVP6_ISEN2 0.25 MM0.25 MM

IMVP6_UGATE2 0.25 MM0.25 MM

0.25 MM0.25 MMIMVP6_LGATE2

0.25 MM0.25 MMIMVP6_BOOT21.5 MM 0.25 MMIMVP6_PHASE2

IMVP6_ISEN1 0.25 MM0.25 MM

IMVP6_PHASE1 1.5 MM 0.25 MM

IMVP6_BOOT1 0.25 MM 0.25 MM

IMVP6_UGATE1 1.5 MM 0.25 MM

CPU_VID<5>

IMVP6_VO_R

CPU_VID<0>

IMVP_DPRSLPVR

IMVP6_IMON

IMVP6_DFB 0.25 MM 0.20 MM

0.25 MM 0.20 MMIMVP6_SOFTIMVP6_RBIAS 0.20 MM0.25 MM

0.25 MM 0.20 MMIMVP6_OCSET

IMVP6_BOOT2DIDT=TRUE

IMVP6_UGATE1

DIDT=TRUE

IMVP6_VR_TT

=PPVIN_S5_CPU_IMVP

=PPVCORE_S0_CPU_REG

CPU_VID<2>

IMVP6_VO1

=PP3V3_S0_IMVP

IMVP6_PHASE2_XW

IMVP6_VO2

IMVP6_BOOT2_RCDIDT=TRUE

DIDT=TRUE

IMVP6_BOOT1

=PP5V_S0_CPU_IMVP

=PPVIN_S5_CPU_IMVP

GND_IMVP6_SGND 0.50 MM 0.20 MM

IMVP6_VO 0.25 MM 0.20 MM

IMVP6_DROOP 0.25 MM 0.20 MM

IMVP6_PHASE1

DIDT=TRUE

IMVP6_VSUM 0.20 MM0.25 MM

IMVP6_NTC

DIDT=TRUEIMVP6_BOOT1_RC

IMVP6_PHASE1_XW

CPU_VID<3>

CPU_DPRSTP_L

CPU_PSI_L

IMVP_VR_ON

CPU_VID<6>

IMVP6_VSEN_N

IMVP6_FB2

IMVP6_VDIFF

IMVP6_FB

IMVP6_VW

IMVP6_RBIAS

IMVP6_SOFT

IMVP6_COMP

VOLTAGE=0VGND_IMVP6_SGND

IMVP6_VSEN_N 0.25 MM 0.25 MM

0.25 MM1.5 MMIMVP6_LGATE1

IMVP6_ISEN2

IMVP6_DFB

IMVP6_DROOP

IMVP6_VSEN_P

IMVP6_FB 0.25 MM 0.20 MM

IMVP6_VW 0.25 MM 0.25 MM

IMVP6_VSEN_P 0.25 MM 0.25 MM

IMVP6_COMP 0.20 MM0.25 MM

IMVP6_FB2 0.25 MM 0.20 MM

IMVP6_VDIFF 0.25 MM 0.20 MM

74 OF 109

C.0.0

051-8561

58 OF 76

12

1 2

1

2

2

1

1

2

1

2

1 2 1 2

1

2

2

1

1 2

1 2

2

1

2

1

1 2

2

1

1 2

1

2 1

2

2

1

1

2

2

1

2

11

2

1 2

1

22

1

2

1

1 2

1 2

2

1

2

1

1 2

1 2

2

1

2

1

1

2

1 2 1 2

1 2

2

1

1

2

1 2

1 2

1

2

1

2

1

2

2

1

2

1

37

46

25

9

10

11

12

4

5

6

44

1

2

15

14

17

16

18

8

19

23

38

40

39

41

42

43

29

20 22 31

30

28

27

24

33

32

35

34

36

26

48

13

7

45

4921

47

3

1

2

2

1

2

1

2

1

2

1

1

2

3

4

2

1

5

6

3

4

2

1

5

6

5

3 4

71 2 6

5

3 4

71 2 6

21

21

2

1

2

1

2

1

2

1

1 2

1

2

58

58

8 58

8 58

11 69

11 69

58

58

58

58

58

58

58

11 69

11 69

58

58

58

58

58

58

58

58

58

11 69

11 69

69

58

58

58

58

58

58

9

8 58

8

11 69

8

58

8 58

8 58

58

58

58

58

58

9

11 69

11 69

58 69

58

58

58

58

58

58

58

58

58 69

58

58

58

58

58 69

58

58

58 69

58

58

58

IN

IN

IN

OUT

OUT

IN

IN

NC

IN

IN

G

D

S

S

D

G

NC

ISP

OCSET

ISN

ICOMP

LGATE

COMP

VDIFF

AF_EN

IMON

VID3

VID2

VDD

BOOT

FB

FDE

PGND

PGOOD PHASE

PVCC

RTN

THRM_PAD

VID0

VID1

VO

VSEN

VSS

VW

UGATE

VINRBIAS

SOFT

VR_ON




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MAX CURRENT: 30.4A

f = 300 kHz

(MCPCORES0_UGATE)

1110 0.9500V 1101 0.9625V

0000 0.9250V 0001 0.9125V

1111 0.9375V

0011 0.8875V

1100 0.9750V

0100 0.8750V

1011 0.7875V 1010 0.8000V

0101 0.8625V 0110 0.8500V 0111 0.8375V

(MCPCORES0_ISN)

(MCPCORES0_ICOMP)

0010 0.9000V

(MCPCORES0_FB)

(MCPCORES0_COMP)

(Q7560 Limit)

(MCPCORES0_VO)

1001 0.8125V 1000 0.8250V

(MCPCORES0_RTN)

(MCPCORES0_PHASE)

(MCPCORES0_VW)

(MCPCORES0_VDIFF)

VID<3:0> VOLTAGE

K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27

(MCPCORES0_VSEN)

=PPVIN_S0_MCPCORE

MCPCORES0_LGATE

DIDT=TRUE


GATE_NODE=TRUE

PP5V_S0_MCPREG_VDDMIN_NECK_WIDTH=0.2 MMVOLTAGE=5V


DIDT=TRUESWITCH_NODE=TRUEMCPCORES0_PHASE


MCPCORES0_UGATEDIDT=TRUE


GATE_NODE=TRUE


DIDT=TRUE

MCPCORES0_BOOT_RMIN_NECK_WIDTH=0.2 MM

VOLTAGE=1V


PPMCPCORE_S0_R

MCPCORES0_ISP_R

=PPMCPCORE_S0_REG

MCPCORES0_VSEN_N

MCPCORES0_IMON=PPMCPCORE_S0_REG

MCPCORES0_COMP_C

MCPCORES0_VSEN_P

MCP_VID<1>

MCP_VID<3>

MCP_VID<0>

MCPCORES0_SOFT

MCPCORES0_VSENMCPCORES0_RTN

=PP5V_S0_MCPREG

MCPCORES0_PGOOD

MCPCORES0_FB

MCP_VID2_REG

MCPCORES0_IMON_R

MCPCORES0_FDE

MCPCORES0_VDIFFMCPCORES0_ISN

MCPCORES0_OCSET

MCPCORES0_ISP

MCPCORES0_ICOMP

MCPCORES0_BOOTDIDT=TRUE


MCPCORES0_VO

MCP_VID3_REG

MCP_VID1_REGMCP_VID0_REG


GND_MCPCORES0_AGNDMIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

MCPCORES0_COMP

MCPCORES0_VW

MCPCORES0_RBIAS

=MCPCORES0_EN

MCP_VID<2>

MCPCORES0_VDIF_C

MCP VCore RegulatorSYNC_MASTER=(K6_MLB) SYNC_DATE=(10/27/2009)

QFN

CRITICAL

ISL9563B

U7500 RJK0365DPA-02WPAK

CRITICAL

Q7560

WPAK

CRITICAL

RJK0208DPAQ7565

19

19

R7594MF-LF 4025%

01/16W

5% 1/16W0

402R7592

MF-LF

402X7R50V10%0.001UFC7577

0.001UF50VX7R402

10%

C7578

R75911/16W

05% 402MF-LF

R7590MF-LF5%

01/16W 402

MF-LF

NOSTUFF5%

0R75934021/16W

75 22

75 22

CASE-D2E-SMPOLY-TANT

16V

68UF20%

CRITICALC7541

40

16VPOLY-TANT

CASE-D2E-SM

20%68UF

CRITICALC7560

CASE-D2E-SMPOLY-TANT

16V

CRITICAL

20%68UF

C7540

0.56UH-31A

FDU1040D-SM

CRITICALL7560

0.0011%1WMF

0612

CRITICALR7525

47PF5%

CERM402

50V

C7575

CERM

5%50V

47PF

402

C7573

100

402MF-LF1/16W1%

R7500

0.001UF10%50VX7R402

C7563

25VX5R

1UF10%

603-1

C7561

20%

X5R

10UF4V

C7567

603

20%2VTANTCASE-B4-SM

CRITICAL

270UFC7565

PLACE_NEAR=R7525.1:1.5MMPLACE_NEAR=L7560.2:1.5MM

10%

402

50VX7R

0.001UFC7569

CASE-B4-SM

2VTANT

270UF20%

CRITICALC7568

X5R

20%4V

10UFC7566

603

6.98K

MF-LF402

1%1/16W

R757610%50V

402X7R

0.001UFC7579

CERM402

10%100V

4700PFC7582

1%1001/16WMF-LF402

R7571

100PF

CERM402

50V5%

C7581

330PFC7580

50VCOG402

5%

1%

402MF-LF1/16W

150KR7577

1/16W1%

402MF-LF

3.01KR7579MF-LF

1/16W1%

402

200R7578

402X5R16V10%1UFC7562MF-LF

603

1/10W5%

2.2R7560

16V

402X5R

1UF10%

C7550

603

5%10V

CERM-X7R

0.22UFC7564

5%

603

1/10WMF-LF

0R75652

1

9.76K

MF-LF402

1/16W1%

R7569

1/16W

402

10K1%

MF-LF

R7573

1/16W1%

402MF-LF

22.1KR7575


SMXW7561

R7561

MF-LF1/16W

5%

402

1K

62

62

147KR7572

1/16WMF-LF

402

1% 0.1UF10%16VX7R-CERM

C7576

402

1/16W1%100

402MF-LF

R7563

10%0.001UF

402X7R50V

C7570402

MF-LF

1%

20

1/16W

R7566

20

MF-LF

1%

402

1/16W

R7568

19

19

75 OF 109

C.0.0

051-8561

59 OF 76

1 2

1 2

2

1

1

2

2

11

2

1

2

1 2

1

2

1

2

1 2

2

1

2

1

1 2

2

1

1 2

1 2

1 2

1 2

1 2

1

2

1 2

2

11

2

2

1

1

2 2

1

1

2

2

1

2

1

2

1

1 2

2

1

2

1

43

2121

1

2

1

2

1

2

1 2

1 2

1 2

2

12

1

1 2

1 2

5

321

4

4

321

5

23

13

3

11

10

21

5

7

30

28

27

26

16

17

6

32

20

31 19

22

9

33

24

25

12

8

15

4

18

141

2

29

8

40

59 8

59 8

8

40

VBST

TON

LL

DRVH

DRVL

V5FILT V5DRV

PGNDGND

EN_PSV

VOUT

TRIP

VFB

THRM_PAD

PGOOD

SYM 2

IN

OUT

S

D

G

S

D

G




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(=PPCPUVTT_S0_REG)

(GND)

ROUTING NOTE:

Vout = 0.75V * (1 + Ra / Rb)

<Ra>

<Rb>

(CPUVTTS0_VFB)

(=PPCPUVTT_S0_REG)


VOUT = 1.052V7.2A MAX OUTPUTF = 320 KHZ

CPUVTT POWER SUPPLY

CPUVTTS0_VSNS

=PPCPUVTT_S0_REG


CPUVTTS0_VBST DIDT=TRUE

CPUVTTS0_TON


CPUVTTS0_DRVLGATE_NODE=TRUE

DIDT=TRUE


VOLTAGE=5V

PP5V_S0_CPUVTTS0_V5FILT

=PP5V_S0_CPUVTTS0


VOLTAGE=0V

GND_CPUVTTS0_SGND

=CPUVTTS0_EN

CPUVTTS0_TRIP

CPUVTTS0_VFB

CPUVTTS0_PGOOD

CPUVTTS0_VOUT


CPUVTTS0_DRVHDIDT=TRUE

GATE_NODE=TRUE

=PPVIN_S0_CPUVTTS0


CPUVTTS0_LLDIDT=TRUE

SWITCH_NODE=TRUE

CPU VTT(1.05V) SUPPLYSYNC_MASTER=(K84_MLB) SYNC_DATE=(02/04/2009)

CRITICAL

CSD58858Q33.3X3.3-QFN

Q7621

3.3X3.3-QFNCSD58858Q3

CRITICALQ7620

2.5V20%

CASE-B2-SMTANT

330UFC7660CRITICAL

OMIT

SM

PLACE_NEAR=C7660.1:2 MM

XW7601

PCMB065T-SM

2.2UH-8.0A

L7620

CRITICAL

50V20%

402CERM

0.001UF


C7661

PLACE_NEAR=Q7620.2:1 MM

0.001UF50V20%

402CERM


C7696

1/16W1%

402MF-LF

301R7601

1/16W1%

402MF-LF

6.04KR7604

62

62

10V10%

402-1X5R

1UFC7601

OMIT

PLACE_NEAR=U7600.15:1MM

SM


XW7600

QFN

TPS51117RGY_QFN14

CRITICALU7600

10%6.3V

603X5R-CERM

4.7UFC7604

50V10%

603-1X7R

0.1UFC7603

B1A-SM

16V20%

POLY

39UF-0.027OHM

CRITICALC7630

1UF10%

603-1

25VX5R

C7695

1/16W1%

402MF-LF

200KR7603

1/16W1%

402MF-LF

20.0KR7671

1/16W1%

402MF-LF

8.06KR7670

NO STUFF

CERM50V5%

402

100PFC7670

SMOMIT


XW76656.3V20%

603X5R

10UFC7665

76 OF 109

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2

12

1

2

11

2

1

2

1

2

2

11

2

2

1

2

1

14

2

12

13

9

4 10

87

1

3

11

5

15

6

1 2

2

1

1

2

1 2

2

1

2

1

21

2

1

1

2

4

321

5

4

321

5

8 8

8

VI

SWENFB

GND

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND THRM_PAD

SS

IN0

IN1

THRML_PAD

EN FB

BIAS

OUT0

OUT1

GND

PG

IN

OUT

OUT

VIN

EN

FB

SW

GNDTHRMPAD

IN




36

BRANCH

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DR


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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Vout = 0.8V * (1 + Ra / Rb)

TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE.

1.8V S0 Switcher

<Rb>

<Ra>

Vout = 0.902VMAX CURRENT = 1.5Af = 1.6MHZ

Vout = 1.05VMax Current = 0.5A

Vout = 1.8V

<Rb>

BOMOPTIONS:

MAX CURRENT = 0.3AF = 1MHZ

Vout = 0.8V * (1 + Ra / Rb)

MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER.MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY.TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE.

K6 NOTES : C7710 AND C7750 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNC’ED FROM T27

FREQ = 1.6MHZVOUT= 1.05V @ 800MA

<Ra>

<Rb>

1.05V S0 MCP PLL LDO

<Ra>

MCP 0.9V S5 (AUXC) Switcher

VOUT = 0.6V * (1 + RA / RB)

1.05V ENET Switcher=PP3V3_ENET_FET

VOLTAGE=3.3V


PP3V3_S0_MCP_PLL_LDO_BIAS

P1V05S0_SW


=PP3V3_S5_P0V9S5

PP1V05_S0_MCP_PLL_REGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

P0V9S5_FB

=PP0V9_S5_REG

DIDT=TRUE

MIN_LINE_WIDTH=0.4 mmP0V9S5_SWMIN_NECK_WIDTH=0.2 mmSWITCH_NODE=TRUE

MCPPLLLDO_SS

MCPPLLLDO_PGOOD

=PP1V05_S0_MCP_PLL_OR=PP1V5_S0_MCP_PLL_VLDO

=PP1V05_S0_MCP_PLL_UF_R

=P1V8S0_EN


P1V8S0_SWMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm

MCPPLLLDO_PGOOD_R

MCPPLLLDO_FB


PP1V5_S0_MCPPLLLDO

VOLTAGE=1.5VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

=P0V9S5_EN

=PP1V8_S0_REG

=PP1V05_S0_REG

=PP3V3_S0_P1V8S0

P1V05S0_FB

=P1V05ENET_EN

P0V9S5_PGOOD

Misc Power SuppliesSYNC_MASTER=MASTER SYNC_DATE=MASTER

EXT1V05

10PF5%50V

CERM402

C7714

62

20%6.3VX5R

10uF

603

EXT1V05C7715

0.1uF

CERM10V20%

402

EXT1V05C7713

10uF

603X5R

6.3V20%

EXT1V05C7710

402

EXT1V05

133K

MF-LF1/16W1%

R7712

402MF-LF1/16W1%100K

EXT1V05

R7711

CERM

5%50V

18PF

402

EXT1V05C7711

CRITICAL

2.2UH-3.25A

IHLP1616BZ-SM

EXT1V05

L7710

UQFNCRITICAL

NCP1529

EXT1V05U7710

20%22UF

CRITICAL

CERM6.3V

805

C7755

01/16W

402MF-LF

5%

MCPPLL_R:LDO

R7750

62

62

62

MCPPLL_LDO

0

1/16WMF-LF

5%

402

R7748

MCPPLL_R:REG

402

5%

MF-LF1/16W

0R7745

MF-LF1/16W

402

0

5%

MCPPLL_R:LDO

R7744

MCPPLL_LDO

4.7UF

402X5R4V20%

C7742

MCPPLL_LDO

402MF-LF1/16W

1%1.37K

R7746

MCPPLL_LDO

402

1UF10%

6.3VCERM

C7740

1001/16W

402

MCPPLL_R:LDO

5%

MF-LF

R7743

MCPPLL_LDO

6.3V10%

CERM402

1UFC7741

MCPPLL_LDO

4.42K

402

1/16W1%

MF-LF

R7747

MCPPLL_LDOCRITICAL

SONTPS74701

U7740

MCPPLL_LDO

402

0.0022UF

CERM

10%50V

C7743

CRITICALDFN

ISL8009BU7750

62

CRITICAL

2.2UH-3.25A

IHLP1616BZ-SM

L7750

5%50V

CERM402

47PFC7751

200K1%1/16W

402MF-LF

R7752

402MF-LF1/16W1%25.5KR7751

CERM

BYPASS=U7750.1:9:2 MM

CRITICAL

22UF6.3V20%

805

C7750

CRITICAL

SOT23-5TPS62202U7760X5R

10uF

603

6.3V20%

C7760

10uF

X5R6.3V20%

603

C7762

CRITICAL

PCAA031B-SM10UH-0.55A-330MOHM

L7760

77 OF 109

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051-8561

61 OF 76

1

22

12

1

2

1

4

3 5

2

1

1

2

1

2

2

1

211

8

6

5

2

3

4

7 9

2

1

7

1

2

11

5 8

4

9

10

6

31

2

2

1

1

2

2

1

1

2

2

1

1 2

1 2

1 2

1

2

2

1

3

6

1

5

2 4 7

21

2

11

2

1

2

2

1

2

1

2

1

2

1

63 62 9 8

8

8

8 8

8

8

8

8

8

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

D

SG

D

S G

D

SG

OUT

IN

NC

D

SG

OUT

D

G S

OUT

VDD

OUT_A*

OUT_A

THRMGND

IN_A

DLY_1C

IN_B

OUT_BDLY (OD,IPU)

(OD,IPU)

(OD,IPU)(IPD)

1.3V

PAD

2:1

-

+

OUTIN

OUT

OUTIN

OUT

IN

THRM_PADGND

V3MON

V4MON RST*

MR*

VDD VDDA

V2MON

Q3

Q2

Q4

Q1

NC

NC

IN OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT




36

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REVISION

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SHEET

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C

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

3.3V w/Divider: 2.345V

S5 Rail Enables & PGOOD

WLAN Enable GenerationNOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

ISL6259 Frequency Select

Worst-Case Thresholds:

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

Q4: 0.660VQ3: 0.640VQ2: 0.XXXV

PM_SLP_S3_LPM_SLP_S4_L

1

0

0

0

1

0

0

1

State

0

1

1

1

SMC_PM_G2_ENABLE

Battery Off (G3Hot)

Run (S0)

Soft-Off (S5)

Sleep (S3)

Pull-up is with power FET.

V2MON: 3.000VV3MON: 0.610VV4MON: 0.610V

Power Control Signals

VDD: 2.9140V

353S2809

Worst-Case Thresholds:

(IPU)

353S2718

VTT Rail Enable Unused PGOOD signal

S0 Rail Enables

VTT rail must ramp up in about

DO NOT SYNC T27, ENET RAILS CHANGED

the same time as MEMVDD rail (Q2300).

ENET Rail Enables

Internal pull-ups 100K +/- 20%

S3 Rail Enables

Threshold: ??

S0 Rail PGOOD Circuitry

S0 Rail PGOOD (ISL Version)

S0 Rail PGOOD (BJT Version)

=P3V3S5_EN_L

MAKE_BASE=TRUEP5VS3_EN_L

P5V3V3_PGOOD

MCPCORES0_PGOOD

PP3V3_S0_VMON

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.2 MM

CPUVTTS0_ENMAKE_BASE=TRUE

P1V5S0_ENMAKE_BASE=TRUE


PM_SLP_S3_L

=P3V3ENET_EN

PM_SLP_S3_L

VMON_3V3_DIV VMON_Q2_BASE

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_PWRCTL

PP3V3_S5

=USB_PWR_ENMAKE_BASE=TRUEDDRREG_EN

MAKE_BASE=TRUESMC_PM_G2_EN

MAKE_BASE=TRUEP3V3S3_EN

MAKE_BASE=TRUEP0V9S5_EN

=DDRREG_EN

=P0V9S5_EN

=P3V3S3_EN

=DDRVTT_EN

AC_OR_S0_L

PM_WLAN_EN_L

AP_PWR_EN

SMC_ADAPTER_EN

VMON_EMITTER

VMON_Q4_BASE

S0PGOOD_BJT_L

MCPPLLLDO_PGOOD

CPUVTTS0_PGOOD

S0PGOOD_BJT

PP1V5_S0 VMON_Q3_BASE

PP1V05_S0

TP_DDRREG_PGOODMAKE_BASE=TRUE

DDRREG_PGOOD

=PP3V42_G3H_CHGR

CHGR_VFRQ

PP3V3_S0

=PP3V3_S0_PWRCTL

PM_SLP_S4_L

PM_SLP_S3_L CHGR_VFRQ_GATE

PP3V3_S0

PP1V5_S0

=PP3V3_ENET_FET

=P1V05ENET_EN

=P5VS3_EN_L

P0V9S5_PGOOD

MAKE_BASE=TRUEPM_SLP_RMGT_L

=P0V9ENET_EN

PM_SLP_S4_L

PM_SLP_S3_R_LMAKE_BASE=TRUE

=PBUSVSENS_EN

=P5VS0_EN

=P3V3S0_EN

=P1V8S0_EN

MAKE_BASE=TRUEMCPCORES0_EN

=P1V5S0_EN

=MCPCORES0_EN

=CPUVTTS0_EN


MAKE_BASE=TRUEMCP_MEM_VDD_EN

P1V05ENET_ENMAKE_BASE=TRUE

S0PGOOD_RST_L

PP5V_S0

PP1V05_S0

MAKE_BASE=TRUEP3V3S5_EN_L

=P5V3V3_REG_EN

S5PGOOD_DLY

MAKE_BASE=TRUERSMRST_PWRGD

MAKE_BASE=TRUEALL_SYS_PWRGD

=PP3V3_S5_VMON

SYNC_MASTER=(T27_MLB)

Power SequencingSYNC_DATE=(10/27/2009)

63

60

59

R78205%

1/16WMF-LF

402

10K

59

R7879100K

5%1/16WMF-LF

402

66 62 35 19 7

60

C78800.47UF

402

6.3V10%

CERM-X5R

C788110%6.3VCERM-X5R402

0.47UFC7882

402

10%6.3V

0.47UF

CERM-X5R

C78830.47UF6.3V

402

10%

CERM-X5R

1

2R7880

402MF-LF1/16W5%22K

1

2R7881

402

33K5%1/16WMF-LF

1

2R7882

402

1/16WMF-LF

15K5%

1

2R788310K5%1/16WMF-LF402

61

R7810

402MF-LF1/16W

5%100K

39

57

C78100.47UF

402CERM-X5R6.3V10%

R7811

MF-LF402

5%1/16W

5.1K

62 36 35 19 7

R7851

402

EXT1V05

10K5%

MF-LF1/16W

61

R7850EXT1V05

15K5%

402

1/16WMF-LF

63

63

63 19

R7826S0PGOOD_BJT

MF-LF

150K1%

1/16W

402

R7872

402

10

MF-LF1/16W5%

NOSTUFF

R7828

402

5%1/16WMF-LF

10

S0PGOOD_BJT

R7827100

5%1/16W

S0PGOOD_BJT

402MF-LF

R7825S0PGOOD_BJT

1/16W

402MF-LF

5%

1K

R7824S0PGOOD_BJT

5%

402

1/16WMF-LF

1K

R7823

MF-LF402

1/16W

S0PGOOD_BJT

1K

5%

R7822S0PGOOD_BJT

1%7.15K

MF-LF1/16W

402

R7821

1/16W

S0PGOOD_BJT

15.0K

402MF-LF

1%

Q7820S0PGOOD_BJT

ASMCC0179

CRITICAL

DFN2015H4-8

U7870TDFN

CRITICAL

ISL88042IRTJJZ

S0PGOOD_ISL

21 19

56

35 7

C780110%

402

16VX5R

0.033UF

56

61

61 35

C784020%

402CERM10V

0.1uF

5%220PF

CERM25V

402

C7841

CRITICAL

TDFNSLG4AP012U7840

55

R7860

402MF-LF1/16W5%10K

VFRQ:LOW

R786110K

5%

MF-LF402

1/16W

VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH

Q7860SSM3K15FV

SOD-VESM-HF

VFRQ:SLPS4&VFRQ:SLPS3

R7863

1/16W

0

402MF-LF

VFRQ:SLPS3

5%

R78640

5%1/16W

402MF-LF

VFRQ:SLPS4

57

Q7891SOT563

SSM6N15FEAPE

S0PGOOD_ISLR7870

1%1/16W

402MF-LF

10K

R787120.0K

S0PGOOD_ISL

1%1/16WMF-LF

402

C7870S0PGOOD_ISL

CERM

0.1uF20%10V

402

57

30

Q7890SSM6N15FEAPE

SOT563

Q7891SOT563SSM6N15FEAPE

Q7890SOT563

SSM6N15FEAPE

30 19

36 35 19

66 62 35 19 7

61

63

C78840.47UF

402CERM-X5R6.3V10%

1

2R7884

1/16W

402MF-LF

5%5.1K

63

R7859

402

5%

MF-LF1/16W

100

34

56

C781210%6.3VCERM-X5R402

NO STUFF

0.47UF

R78120

1/16WMF-LF

5%

402

C7813

402CERM10V

NO STUFF

10%0.068UF

1

2R7813

1/16W5%

402

68K

MF-LF

35 25

56

78 OF 109

C.0.0

051-8561

62 OF 76

2

1

1 2

2

1

12

2

1

3

45

6

1 2

6

12

2

1

1

2

1

2

3

45

1 2

1 2

12

3

1

2

1

2

1

4

3

95

2

7

6

8

2

1

2

1

2

1

94

5

6 8

1

2 7

3

2

7

8

5

1

6 4

3

1

2

1

2

1 2

1 2

1 2

1

2

1 2

1 2

1

21

2

1

2

1 2

2

11

2

2

1

2

1

2

1

2

1

1

2

1

262 8

62 8

75 8 7

75 62 8 7

62 8 7

55 8

75 62 8 7

8

62 36 35 19 7

66 62 35 19 7

75 62 8 7

75 62 8 7

63 61 9 8

8 7

62 8 7

8

SG

D

D

G S

IN

G

DS

D

SG

IN

D

S

G

D

SG

D

SG

IN

D

G S

IN

IN

IN

D

G S

D

G S

S

G

D




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

0.795 A (EDP)

MOSFET

CHANNEL

RDS(ON)

1.569 A (EDP)

48 mOhm @4.5V

FDC638P

13.5 MOHM @4.5V

3.3V S3 FET

LOADING 1.240 A (EDP)

3.3V S0 FET

26 MOHM @4.5V

CHANNEL

RDS(ON)

0.811 A (EDP)

48 mOhm @4.5V

P-TYPE

FDC638P

3.3V S3 FET

(Used to be 5.0V LT S0 FET)

5.0V S0 FET

3.3V S0 FET

=P3V3ENET_EN. Nets separated on

ARB for alternate power options.

Recommend aliasing PM_SLP_RMGT_L and

5.0V LT S0 FET

3.3V ENET FET

I(max) = 1.7A (85C)

DO NOT SYNC FROM K84. ADDED ENET CIRCUITS, REMOVED 1V05 ENET CIRCUIT

0.9V ENET FET

1.5V S0 FET

3.25 A @85C

Rds(on) = 90mOhm max

0.140 A (EDP)

376S0778

@ 2.5V Vgs:

MOBILE:

37 mOhm @2.5V

SI2312BDS

N-Channel

Q7990

Loading

Type

ID(max)

MOSFET

Rds(on)

LOADING

MOSFET

MOSFET

CHANNEL

MOSFET

CHANNEL

LOADING

P-TYPE

TPCP8102

LOADING

P-TYPE

1.5V S0 FET

RDS(ON)

RDS(ON)

P-TYPE

FDC606P

=PP1V5_S0_FET

=PP3V3_S3_FET=PP3V3_S5_P3V3S3FET

P3V3S0_SS

=PP3V3_S5_P3V3S0FET

=PP5V_S3_P5VS0FET

P1V5S0_SSP1V5S0_EN_L

P3V3ENET_SSP3V3ENET_EN_L

P5VS0_SSP5VS0_EN_L

P3V3S0_EN_L

P3V3S3_SSP3V3S3_EN_L

=PP0V9_ENET_FET

=PP0V9_ENET_P0V9ENETFET

=PP3V3_ENET_FET

=PP5V_S0_FET

=P1V5S0_EN

=P3V3S3_EN

=P5VS0_EN

=P3V3S0_EN

=P3V3ENET_EN

P0V9ENET_SS

P0V9ENET_EN_L_RC


P0V9ENET_EN_L

=P0V9ENET_EN

=PPDDR_S3_REG

=PP3V3_S0_FET


POWER FETSSYNC_DATE=MASTERSYNC_MASTER=MASTER

C79100.01UF

CERM402

10%16V

CRITICAL

FDC606P_GSOT-6

Q7930

SSM3K15FVSOD-VESM-HF

Q7905


Q7903

62

62

100K

MF-LF

5%1/16W

402

R7932

1/16W5%

402MF-LF

47KR7930

X5R402

10%16V

0.033UFC7931

0.01UF

CERM402

10%16V

C7930

10K

MF-LF402

5%1/16W

R7912

5%

R7910

1/16W

402MF-LF

47K

62


Q7923

MF-LF

10K5%

1/16W

402

R7922

1/16W

402MF-LF

47K

5%

R7920

0.033UF

X5R402

10%16V

C7921

0.01UF

10%

CERM402

16V

C7920

CRITICAL

FDC638P_GSM

Q7920

62

SSM6N15FEAPESOT563

Q7991

69.8K

MF-LF402

1%1/16W

R7992

10K

MF-LF402

1%1/16W

R7991

100K

MF-LF402

5%1/16W

R7990

SOT563SSM6N15FEAPE

Q7991

0.1UF

CERM402

20%10V

C7990CRITICAL

SI2312BDSSOT23

Q7990

0.01UF

CERM402

10%16V

C7991

62

0.033UF

X5R402

10%16V

C7911

SOT563SSM6N15FEAPE

Q7961

MF-LF

5%1/16W

10K

402

R7962

100K

MF-LF402

1/16W5%

R7960X5R402

10%16V

0.033UFC7961

CRITICAL

NTR4101PSOT-23-HF

Q7960

0.01UF

CERM402

10%16V

C7960

62


Q7947

1/16W

402

47K

MF-LF

5%

R7943

1/16W5%

402MF-LF

47KR7944 0.01UF

CERM402

10%16V

C7943X5R402

10%16V

0.033UFC7942

CRITICAL

23V1K-SM

TPCP8102Q7948

CRITICAL

FDC638P_GSM

Q7910

79 OF 109

C.0.0

051-8561

63 OF 76

5

6

2

1

4

3

78

56

4

31

2

2

1

1 21 2

1

2

1 2

3

12

32

1

2

1

1 2

1

2

3

45

2

1

2

1

2

1

3

2

1

6

12

1 2

1 2

1

2

3

45

5

6

2

1

4

3

1 2

2

1

1 2

1

2

1 2

3

1 2

1

2

1 2

2

1

1 2

1

2

1 2

3

1 2

3

65

21

4

3

1 2

8

8 8

8

8

8

8

62 61 9 8

8

8

57 8

8

8

SYM_VER-1

FOUR GROUNDING VIAS SHOULD BE DISTRIBUTEDALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY

SYM_VER-1

NC

NC

OUT

OUT

GND THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

APN 353S2805

(LVDS DDC POWER)

CAMERA

LVDS CONNECTOR:518S0650LCD CONNECTOR

CAMERA I/F

LED BKLT I/F

LVDS I/F

LVDS_IG_DDC_DATA

LVDS_IG_A_CLK_P


VOLTAGE=5V

PP5V_S3_CAMERA_F

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MMPP3V3_S0_LCD_DDC_F

LVDS_IG_DDC_CLK

=PP3V3_S0_LCD_DDC

LED_RETURN_2

LVDS_IG_A_CLK_F_P

LVDS_IG_A_CLK_N

USB_CAMERA_N

LVDS_IG_A_DATA_P<2>LVDS_IG_A_DATA_N<2>LVDS_IG_A_DATA_P<1>LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<0>LVDS_IG_A_DATA_N<0>

LVDS_IG_A_CLK_F_N

PPVOUT_S0_LCDBKLT

LED_RETURN_6

USB_CAMERA_P

=PP5V_S3_CAMERA

LED_RETURN_5LED_RETURN_4LED_RETURN_3

LED_RETURN_1

USB_CAMERA_CONN_P

USB_CAMERA_CONN_N

=PP3V3_S0_LCD_PANEL

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 MMVOLTAGE=3.3V

PP3V3_SW_LCD_PANEL_F


PP3V3_SW_LCD_PANELVOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MM

LVDS_IG_PANEL_PWR

SYNC_DATE=(10/19/2009)SYNC_MASTER=(K84_MLB)

LVDS CONNECTOR

L9004

0402-LF

FERR-120-OHM-1.5A

R9008

1/16W5%

402MF-LF

100K

R9009

1/16W5%

402MF-LF

100K

U9000FPF1009

CRITICAL

MFET-2X2-8IN


C9017

50V5%

603C0G-CERM

1000PF

72 18

72 18

L9060DLP0NS90-OHM

CRITICAL

PLACEMENT_NOTE=PLACE CLOSE TO J9000.

C9016

10V20%

402CERM

0.1uFPLACE_NEAR=L9050.2:1MM

L9050

0402-LFFERR-120-OHM-1.5A

J9000F-RT-SM

20474-030E-11

CRITICAL

16V10%

402X5R

0.1UFC9009

L9080AMC2012-SM

90-OHM-200MA

CRITICAL

C9010

PLACE_NEAR=J9000.32:1MMPLACE_NEAR=L9004.1:1MM

50V10%

402X7R

0.001UFC9015

PLACE_NEAR=J9000.32:1MMPLACE_NEAR=L9004.1:1MM

50V10%

402X7R

0.001UF

5%

402

R90141K1/16WMF-LF

L9008120-OHM-0.3A-EMI

CRITICAL

0402-LF

16V10%

402X5R

0.1UFC9011

6.3V20%

603X5R

10UFC9012

90 OF 109

C.0.0

051-8561

64 OF 76

2

1

2

1

21

1

2

2

1

2

1

4

3 2

1

2

1

30

29

28

27

26

25

24

23

21

11

16

9

10

6

5

31

33

34

12

13

20

22

17

19

18

8

7

15

14

4

3

2

1

32

2 1

2

1

43

12

2

1

6 7

1

2

3

4

5

1

2

1

2

21

9 7

71 9

7

7

9 7

8

67 7

75 7

71 9

71 9 7

71 9 7

71 9 7

71 9 7

71 9 7

71 9 7

75 7

67 46 7

67 7

8

67 7

67 7

67 7

67 7

75 7

75 7

8

7

9

IN

D

GS

D

GS

D

GS

D

GS




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1


376S0857

376S0857

DP_CA_DET

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

DP_EXT_DDC_CLK

DP_AUX_CH_C_N

DP_EXT_DDC_DATA

DP_AUX_CH_C_P

DISPLAYPORT SUPPORTSYNC_MASTER=K6_MLB SYNC_DATE=02/16/2010

Q9300,Q9302XSTR,FT,N-CH,DUAL,SOT-563376S0859 CRITICAL2

402

10%0.0033UF50V

C9303

CERM

SIGNAL_MODEL=DP_AUXCH_FET

OMITQ9302

SSM6N16FESOT563

SOT563

OMIT


SSM6N16FEQ9302

OMIT


SOT563SSM6N16FEQ9300


OMIT

SOT563SSM6N16FEQ9300

9

402X5R

10%

0.1UFC9301

16V

C9300

16V

0.1UF

10%

402X5R

93 OF 109

C.0.0

051-8561

65 OF 76

1 2

1 2

543

21 6

21 6

543

2

1

71 9

71 9

9

9

OUT

BI

GND

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

GND

DP_PWR

ML_LANE2PAUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P

ML_LANE3N

ML_LANE2N

CONFIG1

CONFIG2

BOT ROW TOP ROWTH PINS SM PINS

SHIELD PINS

IN

IN

IO

NC NC

IO

GND

OUT

IO

NC NC

IO

GND

IO

NC NC

IO

GND

IO

NC NC

IO

GND

IN

IN

IN

IN

IN

IN

G

D

S

G

D

S

SYM_VER-2

SYM_VER-2

SYM_VER-2

SYM_VER-2

G

D

S

G

D

S

BI

IN

IN

OC*

OUT

EN

GND




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DO NOT SYNC. K6 PAGE WITH K84 CONNECTOR

Port Power Switch

DP to DVI/HDMI

Cable Adapter

(CA) has 100k

pull-up to DP_PWR.Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

DP Source must pull

down HPD input with

greater than or equal

to 100K (DPv1.1a).

514-0706

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.50 MMPP3V3_S0_DPPWRMIN_NECK_WIDTH=0.20 MM

DP_EXT_ML_F_N<2>

DP_HPD_Q

DP_EXT_ML_F_N<1>

DP_EXT_ML_F_P<2>

DP_HPD_Q_L

DP_EXT_HPD

=PP5VR3V3_S0_DPCADET=PP3V3_S0_DPCONN

=PP3V3_S0_DPCONN

DP_EXT_CA_DET

DP_CA_DET_Q_L

=PP3V3_S5_DP_PORT_PWR PP3V3_S0_DPILIM

VOLTAGE=3.3V


PM_SLP_S3_L TP_DPPWR_OC_L

DP_EXT_ML_P<3> DP_EXT_ML_C_P<3>

DP_EXT_ML_N<3> DP_EXT_ML_C_N<3>

DP_EXT_ML_P<2>

DP_EXT_ML_N<2>

DP_EXT_ML_N<0>

DP_EXT_ML_C_P<0> DP_EXT_ML_P<0>

DP_EXT_ML_C_N<0>

HDMI_CEC

DP_CA_DET_Q

DP_EXT_ML_F_N<3>DP_EXT_ML_F_P<3>

DP_EXT_AUX_CH_C_N

DP_EXT_AUX_CH_C_P

DP_EXT_ML_F_P<1>

DP_EXT_ML_F_N<0>

DP_EXT_ML_F_P<0>

DP_EXT_ML_C_P<2>

DP_EXT_ML_C_N<2>

DP_EXT_ML_C_P<1> DP_EXT_ML_P<1>

DP_EXT_ML_C_N<1> DP_EXT_ML_N<1>

DisplayPort ConnectorSYNC_MASTER=MASTER SYNC_DATE=MASTER

10UF

X5R

20%6.3V

C9486

603

CRITICAL

22UF

X5R-CERM-1603

6.3V

C948020% 0.1UF

CERM402

20%10V

C9485CRITICAL

100UF

POLY-TANTCASE-B2-SM

20%6.3V

C9487

CRITICAL

TPS2051BSOT23

U9480

62 35 19 7

75 9

0.1UF

CERM402

20%10V

C9481

2N7002DW-X-GSOT-363

Q9441

1M

MF-LF402

5%1/16W

R9422

2N7002DW-X-GSOT-363

Q9441

10K

MF-LF402

5%1/16W

R944510K

MF-LF402

5%1/16W

R9444

12-OHM-100MATCM1210-4SM

FL9403

TCM1210-4SM12-OHM-100MAFL9400

TCM1210-4SM12-OHM-100MAFL9402

TCM1210-4SM

FL940112-OHM-100MA

100K

MF-LF402

5%1/16W

R9442100K

MF-LF402

5%1/16W

R9443

2N7002DW-X-GSOT-363

Q9440

2N7002DW-X-GSOT-363

Q9440

75 9

75 9

100K

MF-LF402

5%1/16W

R9423

FERR-120-OHM-3A

0603

L9400

0.01UF

CERM402

20%16V

C9400

75 9

75 9

75 9

75 9

16V10% 402X5R0.1uFC9412

0.1uF X5R 40210% 16VC9413

16V10% 402X5R0.1uFC9416

16V10% 402X5R0.1uFC9417

DP_ESDCRITICAL


D9410

3


1M

MF-LF402

5%1/16W

R9425


DP_ESDCRITICAL


D9411

3


DP_ESDCRITICAL

RCLAMP0504FSC70-6-1

D9400

2 5

SLP2510P8RCLAMP0524P

CRITICALDP_ESD

D9410

3PLACE_NEAR=J9400.3:3MM

100K

MF-LF402

5%1/16W

R9420

16V10% 402X5R0.1uFC9410

0.1uF X5R 40210% 16VC9411

9

16V10% 402X5R0.1uFC9414

0.1uF X5R 40210% 16VC9415


DP_ESDCRITICAL


D9411

3

100K

MF-LF402

5%1/16W

R9421

75 9

75 9

CRITICAL

MINIDSPLYPRT-K83-GEN2F-RT-THSM

J9400

75 9

9

94 OF 109

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66 OF 76

22

1

7

5

3

9

13

11

8

14

21

20

1516

19

2

18

10

12

17

4

6

1

21

10

2

9

1 2

1 2

1 2

1 2

1

2

4

7

5

6

1

3

6

4

4

7

5

6

1

2

1

10

2

9

1 2

1 2

1 2

1 2

2

1

21

1

2

3

5

4

6

2

1

1

2

1

2

4

32

1

4

32

1

4

32

1

4

3 2

1

1

2

1

2

3

5

4

1

2

6

2

1

2

1

5

3

1

2

4

1

2 2

1

2

1

2

1

75

75

75

8

66 8

66 8

8

75

75

75

75

75

75

75

75

75

75

75

75

75

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

VIN

VDC2

VDC1

EN

WAKE

PWM

COMP

OVP

VOUT

SWB

SWA

FAIL

THRM

PGNDB

PGNDA

GND

ISET

CH1

CH2

CH3

CH4

CH5

CH6

PAD





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VOVP = 6.9V +/- 0.35V

ISET = 153mA / <Riset>

10.2 ohm resistors for currentmeasurement on LED strings.

13.3 Inch, K84 Panel (9 LEDs per string)

<Riset>

ACTUAL: ISET = 19.9mA, OVP = 35.2VTARGET: ISET = 20mA, OVP = 35V

(SGND)OVP = Vovp * (1 + Ra/Rb)

PLACEMENT_NOTEs:

<Rb>

WF: C9711 AND C9717 NOT IN REF SCHEMATIC.

(C9721-C9726)

<Ra>

PLACEMENT_NOTEs:

DO NOT SYNC FROM K84. L9710 CHANGED TO K6/K69

f = 600kHz

(C9710-C9711)

LCDBKLT_VINMIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM

GND_LCDBKLT_SGNDMIN_LINE_WIDTH=0.6 MM

VOLTAGE=0VMIN_NECK_WIDTH=0.24 MM


BKL_MC_CH2MIN_LINE_WIDTH=0.5 mm

LCDBKLT_OVP

LCDBKLT_COMP_RC

PPVIN_BKLMIN_NECK_WIDTH=0.38 MMVOLTAGE=9V


PPBUS_S0_LCDBKLT_PWR

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

LVDS_IG_BKL_PWM_RLVDS_IG_BKL_PWM

MIN_LINE_WIDTH=0.2 MMLCDBKLT_COMPMIN_NECK_WIDTH=0.2 MM


LCDBKLT_ISET


PP5V5_S0_LCDBKLTMIN_LINE_WIDTH=0.3 MM

VOLTAGE=5.5V

BKL_MC_CH6MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm

MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mmBKL_MC_CH5

VOLTAGE=50VMIN_NECK_WIDTH=0.24 MMMIN_LINE_WIDTH=0.5 MMPPVOUT_S0_LCDBKLT

GND_LCDBKLT_PGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 MM


BKL_MC_CH4MIN_LINE_WIDTH=0.5 mm

PPVOUT_S0_LCDBKLT_SWMIN_NECK_WIDTH=0.38 MMMIN_LINE_WIDTH=0.5 MM

SWITCH_NODE=TRUEVOLTAGE=50V

DIDT=TRUE

LCDBKLT_FAIL

MIN_LINE_WIDTH=0.5 mmBKL_MC_CH1MIN_NECK_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mmLED_RETURN_1


LED_RETURN_4MIN_LINE_WIDTH=0.5 mm


LED_RETURN_2


LED_RETURN_6

LED_RETURN_5MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mm


LED_RETURN_3MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=2.5V

PP2V5_S0_LCDBKLT


BKL_MC_CH3

BKLT:ENG103S0198 3 R9717,R9718,R9719RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM


LCD Backlight Driver (MC34845)

RES,MF,0 OHM,5%,1/8W,SMD,LF,0805101S0075 R97001 SENS_R:PROD

103S0198 BKLT:ENG3 R9720,R9721,R9722RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

5%PLACE NEAR U9700

402CERM

100PF50V

NOSTUFFC9721

CRITICAL

LLP

U9700MC34845CEP

100V10%1000PF

X7R603

PLACE_NEAR=XW9701.1:3MMPLACE_NEAR=D9710.2:3MM

C9717

68 9

402

C9706

25VCERM

220PF5%

R9710

MF-LF402

1%7.68K1/16W

603-1

1UF10%

X5R25V

C9711

1M

MF-LF402

1%1/16W

R9715

402

1/16W1%

MF-LF

243KR9716

2.2UF

402

20%10VX5R-CERM

C9701C97002.2UF

10V

402

20%

X5R-CERM

10%25V

805

CRITICAL

X5R

10UF

PLACEMENT_NOTE=PLACE CLOSE TO L9710

C9710

64 7

64 7

64 7

64 7

64 7

64 7

SOD-123

CRITICAL

RB160M-40

PLACE_NEAR=L9710:3MM

D9710

X7R-CERM

4.7UF20%50V

1206

CRITICALC9715

C9799

402

50VCERM

47PF5%

5%MF-LF

BKLT:PROD

402

0

1/16W

R9722

0

1/16W402MF-LF

5%

BKLT:PRODR97215%

0

1/16WMF-LF

BKLT:PROD

402

R9720

0

1/16W5%402MF-LF

BKLT:PRODR9719

BKLT:PROD

0

5%MF-LF

1/16W402

R9718

0

5%402

BKLT:PROD

1/16WMF-LF

R9717

20%

X7R-CERM50V

1206

4.7UF

CRITICALC9716

CRITICAL

33UH-1.8A-110MOHM

1217AS-2SM

L9710

C0G-CERM603


5%1000PF

50V

C9727

R9705

MF-LF402

3.32K1/16W1%

C97050.033UF

10%16VX5R402

SM

OMITXW9701

1%10K

MF-LF402

R9726

1/16W

R9725

402MF-LF

1%

200

1/16W

75 46

75 46

MF-LF

0.020

8050.25W1%

CRITICALSENS_R:ENG

R9700

X5R

10%

402

25V

PLACE_NEAR=L9710:3MM

C97130.1UF

1/16W5%

MF-LF402

10R9730

NOSTUFF

MF-LF

05%

R9702

1/16W

402XW9700

SM

OMITPLACE_NEAR=U9700.25:1MM

PLACEMENT_NOTE=PLACE XW9700 FAR FROM THE NOISY PINS 3 AND 4

NOSTUFF

50VCERM

5%PLACE NEAR U9700100PF

402

C9725

NOSTUFF

100PF50V

CERM

5%

PLACE NEAR U9700

402

C9726

100PF50VCERM

PLACE NEAR U9700

402

5%

NOSTUFFC9723

NOSTUFF

5%50V

402

PLACE NEAR U9700

CERM

100PFC9724

NOSTUFF

50VCERM402

100PF5%

PLACE NEAR U9700

C9722

97 OF 109

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2

1

2

1

2

1

2

1

2

1

1 2

1

2

1

22

1

4321

12

1

2

1 2

2

1

1

2

2

1

21

2

1

1 2

1 2

1 2

1 2

1 2

1 2

2

1

2

1

1 2

2

1

2

1

2

1

1

2

1

2

2

1

1

22

1

2

1

1

23

20

6

18

16

17

22

24

3

4

14

2525

21

13

19

15

7

8

9

10

11

12

2

1

68

64 46 7

OUT

IN

IN

D

SG

D

SG

IN




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MCP79 HAD INTERNAL 10K PULL-UP FOR THESE SIGNALSMCP89 DRIVES THEM LOW

PPBUS S0 LCDBKLT FET

CHANNEL

MOSFET

LOADING

RDS(ON)

0.4 A (EDP)

43 mOhm @4.5V

P-TYPE

FDC638APZ

LVDS_IG_BKL_ONLVDS_IG_BKL_PWM

=PPBUS_S0_LCDBKLT

BKLT_EN_L


VOLTAGE=12.6V

PPBUS_S0_LCDBKLT_FUSED

PBUS_S0_LCDBKLT_EN_DIV

PBUS_S0_LCDBKLT_EN_L


VOLTAGE=12.6V

PPBUS_S0_LCDBKLT_PWR

BKLT_PLT_RST_L

LVDS_IG_BKL_ON

SYNC_DATE=(10/19/2009)

LCD Backlight SupportSYNC_MASTER=(K84_MLB)

68 9

Q9807SSM6N15FEAPE

SOT563

SOT563

Q9807SSM6N15FEAPE

25

R9840

MF-LF402

1/16W

1K5%

NOSTUFF NOSTUFFR98411K

MF-LF402

5%1/16W

Q9806CRITICAL

FDC638APZ_SBMS001SSOT6-HF

8

C98020.1UF

X5R402

10%16V

147K

MF-LF402

1%1/16W

R9809

R9808

1/16W1%

402MF-LF

301K

67

F98002AMP-32V

0402-HF

98 OF 109

C.0.0

051-8561

68 OF 76

21

1

2

1

2

2

1

3

12

56

4

1

2

1

2

6

12

3

45

68 9

67 9

TABLE_SPACING_RULE_ITEM


LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD


TABLE_PHYSICAL_RULE_ITEM






































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All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

FSB 4X signals / groups shown in signal table on right.

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps.Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

FSB 2X signals / groups shown in signal table on right.

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

FSB Clock Constraints

CPU Signal Constraints

MCP FSB COMP Signal ConstraintsSOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

Some signals require 27.4-ohm single-ended impedance.Most CPU signals with impedance requirements are 55-ohm single-ended.

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1

SR DG recommends at least 25 mils, >50 mils preferred

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.


FSB (Front-Side Bus) ConstraintsPHYSICAL

FSB 4X Signal Groups

ELECTRICAL_CONSTRAINT_SET SPACING

NET_TYPE

Signals

Signals within each 4x group should be matched within 5 ps of strobe.

FSB 2X

FSB 1X Signals

CPU / FSB Net Properties

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps.Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right.

Intel Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

(See above)

(FSB_CPURST_L)

(CPU_VCCSENSE)(CPU_VCCSENSE)

?FSB_ADDR * =STANDARD

CPU_ITP * ?=2:1_SPACING

8 MIL* ?MCP_FSB_COMP

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF*CLK_FSB_100D

=3x_DIELECTRIC ?CLK_FSB *

MCP_50S =50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE* =STANDARD =STANDARD

25 MIL*CPU_VCCSENSE ?

25 MILCPU_GTLREF * ?

CPU_AGTL ?* =STANDARD

?CPU_COMP * 25 MIL

8 MILCPU_8MIL ?*

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SECPU_50S * =STANDARD =STANDARD

=27P4_OHM_SE=27P4_OHM_SE* =27P4_OHM_SE =27P4_OHM_SE 7 MIL7 MILCPU_27P4S

=4x_DIELECTRICCLK_FSB ?TOP,BOTTOM

CPU_AGTL ?TOP,BOTTOM =2x_DIELECTRIC

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SEFSB_DSTB_50S * =1:1_DIFFPAIR =1:1_DIFFPAIR

=4x_DIELECTRIC ?FSB_ADSTB TOP,BOTTOM

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SEFSB_50S =STANDARD=STANDARD*

=4x_DIELECTRICFSB_DATA ?TOP,BOTTOM

=5x_DIELECTRIC ?FSB_DSTB TOP,BOTTOM

=3x_DIELECTRIC ?TOP,BOTTOMFSB_ADDR

=3x_DIELECTRIC ?TOP,BOTTOMFSB_1X

=2x_DIELECTRIC ?*FSB_DATA

=3x_DIELECTRIC*FSB_DSTB ?

* ?FSB_1X =STANDARD

=2x_DIELECTRIC* ?FSB_ADSTB


CPU/FSB Constraints

CPU_50S CPU_AGTL FSB_CPUSLP_LFSB_CPUSLP_L

CPU_50S CPU_AGTL FSB_DPWR_LCPU_ASYNC

CPU_50SXDP_TDI CPU_ITP XDP_TDI

FSB_50SFSB_DATA_GROUP0 FSB_DINV_L<0>FSB_DATA

FSB_50SFSB_DATA_GROUP2 FSB_DATA FSB_D_L<47..32>

FSB_DSTB_50S FSB_DSTB_L_N<1>FSB_DSTBFSB_DSTB1

FSB_50S FSB_ADSTB FSB_ADSTB_L<0>FSB_ADSTB0

FSB_50S FSB_BREQ0_LFSB_BREQ0_L FSB_1X

FSB_50S FSB_ADS_LFSB_1X FSB_1X

FSB_50S FSB_ADSTB FSB_ADSTB_L<1>FSB_ADSTB1

FSB_50SFSB_ADDR_GROUP0 FSB_REQ_L<4..0>FSB_ADDR

FSB_50S FSB_ADDRFSB_ADDR_GROUP0 FSB_A_L<16..3>

FSB_DSTB_50S FSB_DSTBFSB_DSTB3 FSB_DSTB_L_N<3>FSB_DSTB_50S FSB_DSTB_L_P<3>FSB_DSTBFSB_DSTB3


FSB_50S FSB_D_L<63..48>FSB_DATA_GROUP3 FSB_DATA

FSB_DSTB_50S FSB_DSTBFSB_DSTB2 FSB_DSTB_L_N<2>FSB_DSTB_50S FSB_DSTB_L_P<2>FSB_DSTBFSB_DSTB2


FSB_DSTB_50SFSB_DSTB1 FSB_DSTB FSB_DSTB_L_P<1>FSB_50SFSB_DATA_GROUP1 FSB_DINV_L<1>FSB_DATA

FSB_50SFSB_DATA_GROUP1 FSB_D_L<31..16>FSB_DATA

FSB_DSTB_50SFSB_DSTB0 FSB_DSTB FSB_DSTB_L_N<0>

FSB_50SFSB_DATA_GROUP0 FSB_D_L<15..0>FSB_DATA

FSB_DSTB_50SFSB_DSTB0 FSB_DSTB_L_P<0>FSB_DSTB

FSB_50SFSB_ADDR_GROUP1 FSB_ADDR FSB_A_L<35..17>

FSB_50S FSB_BNR_LFSB_1XFSB_1X

FSB_50S FSB_BPRI_LFSB_1XFSB_1X

FSB_50S FSB_1X FSB_DBSY_LFSB_1X

FSB_50S FSB_1X FSB_DEFER_LFSB_1X

FSB_50S FSB_1X FSB_DRDY_LFSB_1X

FSB_50S FSB_LOCK_LFSB_1XFSB_1X

FSB_50S FSB_1X FSB_CPURST_LFSB_CPURST_L

FSB_50S FSB_1X FSB_RS_L<2..0>FSB_1X

FSB_50S FSB_TRDY_LFSB_1X FSB_1X

CPU_50S CPU_AGTL CPU_A20M_LCPU_ASYNC

CPU_50S CPU_AGTL CPU_BSEL<2..0>CPU_BSEL

CPU_50S CPU_FERR_LCPU_FERR_L CPU_8MIL

CPU_50S CPU_NMICPU_ASYNC_R CPU_AGTL

CPU_50S CPU_PROCHOT_LCPU_PROCHOT_L CPU_AGTL

CPU_50S CPU_AGTL CPU_PWRGDCPU_PWRGD

CPU_50S CPU_SMI_LCPU_ASYNC CPU_AGTL

CPU_50S CPU_AGTL CPU_DPSLP_LCPU_FROM_SB

CPU_50S CPU_AGTL CPU_DPRSTP_LCPU_DPRSTP_L

CPU_50S CPU_INTRCPU_ASYNC_R CPU_AGTL

CPU_50S CPU_INIT_LCPU_INIT_L CPU_AGTL

CPU_50S CPU_AGTL CPU_IGNNE_LCPU_ASYNC

FSB_50S FSB_HITM_LFSB_1XFSB_1X

FSB_50S FSB_1X FSB_HIT_LFSB_1X

FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_N

FSB_CLK_CPU FSB_CLK_CPU_PCLK_FSBCLK_FSB_100D

FSB_CLK_CPU FSB_CLK_CPU_NCLK_FSBCLK_FSB_100D

FSB_CLK_MCP CLK_FSBCLK_FSB_100D FSB_CLK_MCP_PFSB_CLK_MCP CLK_FSBCLK_FSB_100D FSB_CLK_MCP_N

CPU_50SCPU_IERR_L CPU_IERR_L

CPU_50SPM_DPRSLPVR CPU_AGTL PM_DPRSLPVRCPU_50S CPU_AGTL IMVP_DPRSLPVR

CPU_50SCPU_GTLREF CPU_GTLREFCPU_GTLREF

CPU_50SCPU_COMP CPU_COMP<3>CPU_COMP

CPU_COMP CPU_COMP<2>CPU_27P4S CPU_COMP

CPU_50SCPU_COMP CPU_COMP<1>CPU_COMP

CPU_COMP CPU_COMPCPU_27P4S CPU_COMP<0>

CPU_50SXDP_TMS CPU_ITP XDP_TMSCPU_50SXDP_TDO CPU_ITP XDP_TDO

CPU_50SXDP_TCK CPU_ITP XDP_TCK

CPU_50SXDP_BPM_L XDP_BPM_L<4..0>CPU_ITP

CPU_50S XDP_CPURST_LCPU_ITP

CPU_50SXDP_BPM_L5 CPU_ITP XDP_BPM_L<5>

CPU_50S CPU_VID<6..0>CPU_8MIL

CPU_50S IMVP6_VID<6..0>CPU_8MIL

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_PCPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_N

CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_PCPU_VCCSENSE IMVP6_VSEN_NCPU_27P4S

MCP_50S MCP_BCLK_VML_COMP_VDDMCP_CPU_COMP MCP_FSB_COMP

MCP_50S MCP_BCLK_VML_COMP_GNDMCP_CPU_COMP MCP_FSB_COMP

MCP_50S MCP_CPU_COMP_VCCMCP_CPU_COMP MCP_FSB_COMP

MCP_50S MCP_CPU_COMP_GNDMCP_CPU_COMP MCP_FSB_COMP

CPU_50SXDP_TRST_L CPU_ITP XDP_TRST_L

FSB_CLK_ITP CLK_FSB FSB_CLK_ITP_PCLK_FSB_100D

CPU_50S PM_THRMTRIP_LCPU_8MILPM_THRMTRIP_L

CPU_50S CPU_AGTL CPU_STPCLK_LCPU_ASYNC

100 OF 109

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10 14

10 14

10 13

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7 10 14

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7 10 14

10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

10 14

10 14

10 14

10 14

10 14

7 10 14

10 13 14

10 14

10 14

10 14

9 10

10 14

10 14

10 14 36

10 13 14

10 14

10 14

10 14 58

10 14

10 14

10 14

7 10 14

7 10 14

13 14

10 14

10 14

14

14

10

14 58

58

10 29

10

10

10

10

10 13

10 13

10 13

10 13

13

10 13

11 58

11 58

11 58

58

58

14

14

14

14

10 13

13 14

10 14 36

10 14







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AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM










































Memory Bus ConstraintsPHYSICALELECTRICAL_CONSTRAINT_SET SPACING

NET_TYPE

Memory Net Properties

NV DG says 3x inner, 4x outer








Need to support MEM_*-style wildcards!

MCP MEM COMP Signal Constraints

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.2

DQ signals should be matched within 5 ps of associated DQS pair.

No DQS to clock matching requirement.CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.

All memory signals maximum length is 1.030 ps.CMD/CTRL signals should be matched within 150 ps.

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.3SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

Memory Bus Spacing Group Assignments

DDR3:

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE =STANDARD* =STANDARDMEM_40S

Memory ConstraintsSYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010

=4:1_SPACING ?*MEM_CLK2MEM

?* =2:1_SPACINGMEM_CTRL2CTRL

*MEM_DQS2MEM =3:1_SPACING ?

?* =3:1_SPACINGMEM_DATA2MEM

=3:1_SPACING ?*MEM_CMD2MEM

=1.5:1_SPACING ?*MEM_DATA2DATA

?*MEM_CMD2CMD =1.5:1_SPACING

=2.5:1_SPACING ?*MEM_CTRL2MEM

MEM_CLK MEM_CMD2MEM*MEM_CMD

MEM_CMD2CMDMEM_CMDMEM_CMD *

MEM_CTRL MEM_CMD2MEMMEM_CMD *

MEM_DATA MEM_CMD2MEMMEM_CMD *

MEM_DQS *MEM_CMD MEM_CMD2MEM

MEM_CLKMEM_DATA MEM_DATA2MEM*

MEM_CMD *MEM_DATA MEM_DATA2MEM

MEM_CTRL MEM_DATA2MEM*MEM_DATA

*MEM_DATA MEM_DATA2DATAMEM_DATA

MEM_DQS *MEM_DATA MEM_DATA2MEM

* *MEM_CLK MEM_2OTHER

**MEM_CTRL MEM_2OTHER

* *MEM_CMD MEM_2OTHER

**MEM_DATA MEM_2OTHER

* *MEM_DQS MEM_2OTHER

?*MEM_2OTHER 25 MIL

*MEM_CLK MEM_CLK2MEMMEM_CMD

* MEM_CLK2MEMMEM_CTRLMEM_CLK

* MEM_CLK2MEMMEM_CLKMEM_CLK

MEM_CLK2MEMMEM_CLK *MEM_DATA

*MEM_CLK MEM_CLK2MEMMEM_DQS

*MEM_CLK MEM_CTRL2MEMMEM_CTRL

MEM_CTRL *MEM_CTRL MEM_CTRL2CTRL

MEM_CTRL * MEM_CTRL2MEMMEM_DATA

MEM_CTRL MEM_CTRL2MEM*MEM_CMD

MEM_CTRL2MEM*MEM_CTRL MEM_DQS

MEM_DQS MEM_DQS2MEM*MEM_DATA

MEM_DQS MEM_DQS2MEM*MEM_CLK

MEM_DQS MEM_DQS2MEM*MEM_CTRL

* MEM_DQS2MEMMEM_DQS MEM_CMD

* MEM_DQS2MEMMEM_DQS MEM_DQS

=2x_DIELECTRICMCP_MEM_COMP * ?

MCP_MEM_COMP * =STANDARD =STANDARD=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

MEM_70D =70_OHM_DIFF=70_OHM_DIFF* =70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF

MEM_A_CLK_P<5..0>MEM_A_CLK MEM_CLKMEM_70D

MEM_A_CKE<3..0>MEM_CTRLMEM_40SMEM_A_CKE

MEM_A_CLK_N<5..0>MEM_A_CLK MEM_CLKMEM_70D

MEM_40S MEM_CTRLMEM_B_CNTL MEM_B_CS_L<3..0>MEM_40S MEM_CTRLMEM_B_CNTL MEM_B_ODT<3..0>

MEM_40S MEM_B_A<15..0>MEM_CMDMEM_B_CMD

MEM_40S MEM_CMD MEM_B_BA<2..0>MEM_B_CMD

MEM_40S MEM_CMD MEM_B_RAS_LMEM_B_CMD

MEM_40S MEM_CMD MEM_B_CAS_LMEM_B_CMD

MEM_40S MEM_CMD MEM_B_WE_LMEM_B_CMD

MEM_DATAMEM_40S MEM_B_DQ<7..0>MEM_B_DQ_BYTE0




MEM_DATA MEM_B_DQ<39..32>MEM_40SMEM_B_DQ_BYTE4




MEM_DATAMEM_40S MEM_B_DM<0>MEM_B_DQ_BYTE0








MEM_DQSMEM_70DMEM_B_DQS0 MEM_B_DQS_P<0>MEM_DQS MEM_B_DQS_N<0>MEM_B_DQS0 MEM_70D

MEM_DQSMEM_70D MEM_B_DQS_P<1>MEM_B_DQS1

MEM_DQSMEM_70D MEM_B_DQS_N<1>MEM_B_DQS1






MEM_DQS MEM_B_DQS_N<4>MEM_70DMEM_B_DQS4







MCP_MEM_COMP_VDDMCP_MEM_COMPMCP_MEM_COMP MCP_MEM_COMPMCP_MEM_COMP_GNDMCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MEM_CTRL MEM_A_CS_L<3..0>MEM_A_CNTL MEM_40S

MEM_CTRL MEM_A_ODT<3..0>MEM_A_CNTL MEM_40S

MEM_A_CMD MEM_CMD MEM_A_A<15..0>MEM_40S

MEM_A_CMD MEM_A_RAS_LMEM_CMDMEM_40S

MEM_A_CMD MEM_A_BA<2..0>MEM_CMDMEM_40S

MEM_A_CAS_LMEM_CMDMEM_A_CMD MEM_40S

MEM_CMDMEM_A_CMD MEM_A_WE_LMEM_40S

MEM_DATAMEM_A_DQ_BYTE0 MEM_A_DQ<7..0>MEM_40S

MEM_A_DQ_BYTE2 MEM_A_DQ<23..16>MEM_DATAMEM_40S


MEM_A_DQ<39..32>MEM_DATAMEM_A_DQ_BYTE4 MEM_40S

MEM_DATA MEM_A_DQ<31..24>MEM_A_DQ_BYTE3 MEM_40S

MEM_A_DQ<47..40>MEM_DATAMEM_A_DQ_BYTE5 MEM_40S

MEM_A_DQ_BYTE7 MEM_A_DQ<63..56>MEM_DATAMEM_40S


MEM_DATA MEM_A_DM<1>MEM_A_DQ_BYTE1 MEM_40S



MEM_A_DM<2>MEM_DATAMEM_A_DQ_BYTE2 MEM_40S





MEM_A_DQS0 MEM_DQSMEM_70D MEM_A_DQS_P<0>MEM_A_DQS0 MEM_A_DQS_N<0>MEM_DQSMEM_70D

MEM_A_DQS1 MEM_A_DQS_N<1>MEM_DQSMEM_70D

MEM_70D MEM_A_DQS_P<1>MEM_A_DQS1 MEM_DQS

MEM_70DMEM_A_DQS2 MEM_A_DQS_N<2>MEM_DQS

MEM_A_DQS2 MEM_A_DQS_P<2>MEM_DQSMEM_70D








MEM_70DMEM_A_DQS6 MEM_A_DQS_P<6>MEM_DQS

MEM_70DMEM_A_DQS7 MEM_DQS MEM_A_DQS_N<7>MEM_A_DQS7 MEM_A_DQS_P<7>MEM_DQSMEM_70D

MEM_CLKMEM_B_CLK MEM_B_CLK_N<5..0>MEM_70D

MEM_CLKMEM_B_CLK MEM_B_CLK_P<5..0>MEM_70D

MEM_B_CKE MEM_B_CKE<3..0>MEM_CTRLMEM_40S

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15

15

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36

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PAGE TITLE

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Apple Inc.

PAGE


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345678

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8 7 5 4 2 1
































PCI-ExpressPHYSICAL SPACING

NET_TYPENET_TYPE

MCP89 Net PropertiesELECTRICAL_CONSTRAINT_SET


Analog Video Signal Constraints

- 75-ohm from output of three-pole filter to connector (if possible).

- 37.5-ohm from MCP to first termination resistor.

Digital Video Signal Constraints

NEED PCIe Gen1/Gen2 notes!

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1.

- 50-ohm from first to second termination resistor.

CRT signal single-ended impedence varies by location:

R/G/B signals should be matched as close as possible and < 10 inches.

SATA Interface ConstraintsSOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.2

LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps.NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm.

SATA intra-pair matching should be 1 ps.

DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.Max trace length: LVDS 10 inches, DP 8.5 inches.

Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3.SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.6

PCIE_90D =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF* =90_OHM_DIFF=90_OHM_DIFF

PCIE ?TOP,BOTTOM =4X_DIELECTRIC

20 MILCLK_PCIE ?*

8 MILMCP_PEX_COMP ?*

PCIE =3X_DIELECTRIC ?*

=100_OHM_DIFF=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFF


MCP Constraints 1

CRT_2CRT*CRTCRT

CRT_50S =50_OHM_SE =STANDARD* =STANDARD=50_OHM_SE=50_OHM_SE =50_OHM_SE

CRT * ?20 MIL

TOP,BOTTOM =4x_DIELECTRIC ?DISPLAYPORT

?LVDS =4x_DIELECTRICTOP,BOTTOM

CRT_2CRT ?* 15 MIL

?*CRT_2CLK 50 MIL

MCP_DAC_COMP * ?=2x_DIELECTRIC

CRT_SYNC ?* =4x_DIELECTRIC

* ?CRT_2SWITCHER 250 MIL

?*LVDS =3x_DIELECTRIC

=100_OHM_DIFFLVDS_100D * =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

SATA ?TOP,BOTTOM =4x_DIELECTRIC

* ?SATA_TERMP 8 MIL

?SATA * =3x_DIELECTRIC

*SATA_90D =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=3x_DIELECTRIC* ?DISPLAYPORT

* Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARDMCP_DV_COMP

DP_90D =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF*

PCIEPCIE_90D PCIE_ENET_D2R_NPCIEPCIE_90D PCIE_ENET_D2R_C_PPCIEPCIE_90D PCIE_ENET_D2R_C_N

PCIEPCIE_90D PCIE_FW_R2D_P

PCIE_FW_R2D PCIE_FW_R2D_C_PPCIEPCIE_90D

PCIEPCIE_90D PCIE_FW_R2D_C_NPCIE_FW_D2R PCIE_FW_D2R_PPCIEPCIE_90D

PCIE_FW_D2R_NPCIEPCIE_90D

PCIE_FW_D2R_C_NPCIEPCIE_90D

CLK_PCIE PEG_CLK100M_PCLK_PCIE_100DMCP_PE0_REFCLKPEG_CLK100M_NCLK_PCIECLK_PCIE_100D

CLK_PCIE PCIE_CLK100M_AP_NCLK_PCIE_100D

CLK_PCIE PCIE_CLK100M_ENET_PCLK_PCIE_100DMCP_PE2_REFCLK

CLK_PCIE PCIE_CLK100M_ENET_NCLK_PCIE_100D

CRT_IG_R_C_PRCRTCRT_50SCRT_RED

CRT_50S CRT_IG_G_Y_YCRTCRT_GREEN

CRT_50S CRT CRT_IG_B_COMP_PBCRT_BLUECRT_IG_HSYNCCRT_SYNCCRT_50SCRT_SYNC

CRT_50S CRT_IG_VSYNCCRT_SYNCCRT_SYNC

MCP_TV_DAC_VREFMCP_DAC_COMPMCP_DAC_VREF

MCP_TV_DAC_RSETMCP_DAC_COMPMCP_DAC_RSET

DP_90D DP_IG_ML_P<3..0>DISPLAYPORTDP_EXT_ML

DP_90D DP_IG_ML_N<3..0>DISPLAYPORTDP_EXT_ML

DP_90D DP_IG_AUX_CH_NDISPLAYPORTDP_EXT_AUX_CH

MCP_TMDS0_RSET MCP_TMDS0_RSETMCP_DV_COMP

DP_90D TMDS_IG_TXC_PDISPLAYPORTTMDS_IG_TXC

DP_90D DISPLAYPORT TMDS_IG_TXC_NTMDS_IG_TXC

DP_90D DISPLAYPORT TMDS_IG_TXD_P<5..0>TMDS_IG_TXD

PCIE_CLK100M_FW_NCLK_PCIE_100D CLK_PCIE

PCIE_FW_D2R_C_PPCIEPCIE_90D

PCIE_90D PCIE PEG_D2R_N<15..0>

PEG_D2R_C_N<15..0>PCIEPCIE_90D

PCIE_AP_R2D_C_PPCIE_AP_R2D PCIE_90D PCIE

MCP_SATA_TERMPSATA_TERMPMCP_SATA_TERMP

SATA SATA_ODD_D2R_C_PSATA_90DSATA_ODD_D2R_C_NSATASATA_90D

SATA SATA_ODD_D2R_NSATA_90D

SATA_ODD_D2R_PSATASATA_ODD_D2R SATA_90D

SATA SATA_ODD_R2D_NSATA_90D

SATA SATA_ODD_R2D_C_NSATA_90D

SATA SATA_ODD_R2D_PSATA_90D

SATA_ODD_R2D_C_PSATASATA_ODD_R2D SATA_90D

SATA SATA_HDD_D2R_C_NSATA_90D

SATA SATA_HDD_D2R_C_PSATA_90D

SATA SATA_HDD_D2R_PSATA_HDD_D2R SATA_90D

SATA SATA_HDD_D2R_NSATA_90D

SATA SATA_HDD_R2D_NSATA_90D

SATA_HDD_R2D_PSATASATA_90D

SATA SATA_HDD_R2D_C_NSATA_90D

SATA_HDD_R2D_C_PSATASATA_HDD_R2D SATA_90D

MCP_IFPAB_VPROBEMCP_IFPAB_VPROBE

LVDSLVDS_100DLVDS_IG_B_DATA3 LVDS_IG_B_DATA_N<3>LVDSLVDS_100DLVDS_IG_B_DATA3 LVDS_IG_B_DATA_P<3>

LVDSLVDS_100DLVDS_IG_B_DATA LVDS_IG_B_DATA_P<2..0>LVDS_IG_B_CLK_NLVDSLVDS_100DLVDS_IG_B_CLK

LVDSLVDS_IG_B_CLK LVDS_IG_B_CLK_PLVDS_100D

LVDS_IG_A_DATA_N<2..0>LVDS_IG_A_DATA LVDS_100D LVDS

LVDS_IG_A_CLK_NLVDSLVDS_100DLVDS_IG_A_CLK

LVDS_100DLVDS_IG_A_CLK LVDS_IG_A_CLK_PLVDS

MCP_TMDS0_VPROBE MCP_TMDS0_VPROBE

DP_90D DISPLAYPORT DP_IG_AUX_CH_PDP_EXT_AUX_CH

DP_90DTMDS_IG_TXD DISPLAYPORT TMDS_IG_TXD_N<5..0>

PCIEPCIE_90D PCIE_ENET_R2D_N

PCIEPCIE_90D PCIE_ENET_D2R_PPCIE_ENET_D2R

PCIEPCIE_90D PCIE_ENET_R2D_P

PCIEPCIE_90D PCIE_ENET_R2D_C_N

PEG_D2R_C_P<15..0>PCIEPCIE_90D

PEG_R2D_C_P<15..0>PCIE_90D PCIEPEG_R2D

PEG_D2R_P<15..0>PCIE_90D PCIEPEG_D2R

PCIE_AP_R2D_NPCIEPCIE_90D

PCIE_90D PCIE PEG_R2D_C_N<15..0>

PCIEPCIE_90D PCIE_AP_R2D_P

MCP_IFPAB_RSET MCP_IFPAB_RSETMCP_DV_COMP

LVDS_100DLVDS_IG_B_DATA LVDS LVDS_IG_B_DATA_N<2..0>

MCP_PEX_COMP MCP_PEX0_TERMPMCP_PEX_CLK_COMP

LVDS_100DLVDS_IG_A_DATA3 LVDS_IG_A_DATA_P<3>LVDSLVDS_IG_A_DATA_N<3>LVDSLVDS_IG_A_DATA3 LVDS_100D

LVDS_IG_A_DATA LVDS_100D LVDS_IG_A_DATA_P<2..0>LVDS

CLK_PCIE PCIE_CLK100M_FW_PCLK_PCIE_100DMCP_PE3_REFCLK

PCIEPCIE_90D PCIE_ENET_R2D_C_PPCIE_ENET_R2D

PCIE_FW_R2D_NPCIEPCIE_90D

PCIE_CLK100M_AP_PCLK_PCIECLK_PCIE_100DMCP_PE1_REFCLK

PCIEPCIE_90D PCIE_AP_D2R_NPCIE_AP_D2R_PPCIE_AP_D2R PCIEPCIE_90D

PCIE_AP_R2D_C_NPCIEPCIE_90D

PEG_R2D_N<15..0>PCIE_90D PCIE

PCIE_90D PCIE PEG_R2D_P<15..0>

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9 16

9 16

9 16

9 16

9 16

9 16

9 16

9 16

9 16

9

9

9 65

17 24

9 16

9 16

18

7 33

7 33

18 33

18 33

7 33

18 33

7 33

18 33

7 33

7 33

18 33

18 33

7 33

7 33

18 33

18 33

17 24

7 9 64

9 64

9 64

17 24

9 65

9 16

9 16

9

9

17 24

16

7 9 64

9 16

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36

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D

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Apple Inc.

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C

345678

D

B

8 7 5 4 2 1






SIO Signal Constraints

(SMBUS_SMC_MGMT_SDA)

(SMBUS_SMC_MGMT_SCL)


SPACINGPHYSICAL

LPC Bus Constraints

HD Audio Interface Constraints

SPI Interface Constraints

USB 2.0 Interface Constraints

SMBus Interface Constraints

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

MCP89 Net Properties

=90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF* =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFFUSB_90D

=55_OHM_SE =STANDARD=55_OHM_SE=55_OHM_SE=55_OHM_SELPC_55S * =STANDARD

*CLK_LPC_55S =55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE =STANDARD=STANDARD

LPC ?* =1.5x_DIELECTRIC

CLK_LPC * ?=2x_DIELECTRIC

=2x_DIELECTRICUSB ?*

=55_OHM_SE=55_OHM_SE=55_OHM_SESMB_55S =STANDARD=STANDARD* =55_OHM_SE

SMB * ?=2x_DIELECTRIC

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SEHDA_55S =STANDARD =STANDARD*

MCP_HDA_COMP 8 MIL* ?

?*HDA =2x_DIELECTRIC

* =55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SECLK_SLOW_55S =STANDARD=STANDARD

?CLK_SLOW * =1.5x_DIELECTRIC

=55_OHM_SESPI_55S =55_OHM_SE=55_OHM_SE=55_OHM_SE* =STANDARD =STANDARD

?SPI * =1.5x_DIELECTRIC

MCP_USB_RBIAS * =STANDARD 8 MIL =STANDARD=STANDARD=STANDARD8 MIL

=4x_DIELECTRICTOP,BOTTOM ?USB


MCP Constraints 2

SPI_MLB_MISOSPI_55S SPI

SPI SPI_CLK_RSPI_CLK SPI_55S

USB_WM_PUSB_WM USB_90D USB

USB_SDCARD USB_SDCARD_PUSBUSB_90D

MCP_USB_RBIAS_GNDMCP_USB_RBIASMCP_USB_RBIAS

SMB SMBUS_MCP_0_CLKSMBUS_MCP_0_CLK SMB_55SSMBUS_MCP_0_DATASMBSMBUS_MCP_0_DATA SMB_55SSMBUS_MCP_1_CLKSMBSMB_55SSMBUS_MCP_1_DATASMBSMB_55S

HDA_SYNCHDAHDA_SYNC HDA_55S

HDA_BIT_CLK_RHDAHDA_55S

MCP_HDA_COMP MCP_HDA_PULLDN_COMPMCP_HDA_PULLDN_COMP

CLK_SLOWCLK_SLOW_55S PM_CLK32K_SUSCLK

SPISPI_MISO SPI_55S SPI_MISO

LPC_AD LPC_AD<3..0>LPC_55S LPCLPC_FRAME_LLPC_FRAME_L LPCLPC_55SLPC_RESET_LLPCLPC_RESET_L LPC_55S

MCP_LPC_CLK0 CLK_LPCCLK_LPC_55S LPC_CLK33M_SMC_RCLK_LPCCLK_LPC_55S LPC_CLK33M_SMCCLK_LPCCLK_LPC_55S LPC_CLK33M_LPCPLUS

USB_EXTA USBUSB_90D USB_EXTA_PUSB USB_EXTA_NUSB_90D

USBUSB_90D USB_EXTA_MUXED_P

USBUSB_90DUSB_MINI USB_MINI_PUSB_90D USB USB_EXTA_MUXED_N

USB_MINI_NUSBUSB_90D

USB USB_EXTD_PUSB_90DUSB_EXTD

USB USB_EXTD_NUSB_90D

USB_90D USB USB_BT_N

USB_90DUSB_CAMERA USB USB_CAMERA_P

HDA_SDIN0 HDAHDA_55S HDA_SDIN0

HDA_SYNC_RHDAHDA_55S

HDA_BIT_CLKHDA_BIT_CLK HDAHDA_55S

USB_WM_NUSBUSB_90D

USB_T57_NUSBUSB_90D

USB_90D USB USB_EXTB_NUSB_90D USBUSB_EXTB USB_EXTB_PUSB_90D USB USB_IR_N

USB_IR_PUSBUSB_90DUSB_IR

USBUSB_90D USB_TPAD_NUSBUSB_90D USB_TPAD_PUSB_TPAD

USB_90D USBUSB_BT USB_BT_PUSBUSB_90D USB_CAMERA_N

USB_T57 USB_T57_PUSB_90D USB

USB_EXTC_PUSB_EXTC USBUSB_90D

USB_SDCARD_NUSB_90D USB

USB_90D USB_EXTC_NUSB

MCP_SUS_CLK CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK_R

HDA_55S HDA_SDOUT_RHDA

HDA_SDOUTHDAHDA_SDOUT HDA_55S

HDAHDA_55S HDA_SDIN_CODEC

SPI_CS0_R_LSPI_CS0 SPI_55S SPI

SPI_MOSI_RSPI_MOSI SPISPI_55S

HDA_RST_LHDAHDA_55S

HDA_RST_L HDA_RST_R_LHDAHDA_55S

SPI_55S SPI SPI_CLK

SPI_MOSISPI_55S SPI

SPISPI_55S SPI_CS0_L

SPI_MLB_CLKSPISPI_55SSPI_MLB_MOSISPI_55S SPI

SPI_MLB_CS_LSPISPI_55S

SPI_ALT_CS_LSPI_55S SPI

SPI_ALT_MOSISPISPI_55SSPI_ALT_MISOSPISPI_55S

SPI_ALT_CLKSPI_55S SPI

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19

19

25 35

7 19 37

19 35 37

19 35 37

19 25

19 25

25 35

25 37

18 34

18 34

34 75

9 18

34 75

9 18

9 18

9 18

18 30

18 64

19 48

19

19 48

9 18

9 18

18 34

18 34

9 18

9 18

18 43

18 43

18 30

18 64

9 18

9 18

9 18

9 18

19 25

19

19 48

48

19 37

19 37

19 48

19

7 37

7 37

7 37

37 47

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37 47

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36

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SHEET

PAGE TITLE

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D

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Apple Inc.

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A

B

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345678

D

B

8 7 5 4 2 1

SPACINGPHYSICAL

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

88E1116R (Ethernet PHY) Constraints


NET_TYPE

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

MCP RGMII (Ethernet) Constraints

ENET_MDI * ?25 MIL

12 MILENET_MII * ?

MCP_BUF0_CLK ?* =3:1_SPACING

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF* =100_OHM_DIFFENET_MDI_100D

* =STANDARD=STANDARDENET_MII_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

MCP_MII_COMP * =STANDARD 7.5 MIL =STANDARD=STANDARD7.5 MIL =STANDARD


Ethernet Constraints

ENET_RXD_STRAP ENET_MIIENET_MII_55S ENET_RXD<3..1>

ENET_MDIOENET_MDIO ENET_MIIENET_MII_55S

ENET_CLK125M_RXCLK_RENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S ENET_CLK125M_TXCLK_R

ENET_TXD<0>ENET_TXD0 ENET_MIIENET_MII_55S

ENET_TX_CTRLENET_TXD ENET_MIIENET_MII_55S

ENET_RESET_LENET_MIIENET_MII_55S

ENET_MDI_P<3..0>ENET_MDI ENET_MDIENET_MDI_100D

ENET_MDI_TRAN_P<3..0>ENET_MDIENET_MDI_100DENET_MDI_TRAN_N<3..0>ENET_MDIENET_MDI_100D

ENET_TXD<3..1>ENET_TXD ENET_MIIENET_MII_55S

ENET_TXCLK ENET_MIIENET_MII_55S ENET_CLK125M_TXCLK

ENET_MIIENET_MII_55S ENET_RXCTL_RENET_RXD ENET_MIIENET_MII_55S ENET_RX_CTRL

ENET_MDCENET_MDC ENET_MII_55S ENET_MII

ENET_MDI_N<3..0>ENET_MDIENET_MDI_100D

ENET_CLK125M_RXCLKENET_RXCLK ENET_MIIENET_MII_55S

ENET_PWRDWN_LENET_PWRDWN_L ENET_MIIENET_MII_55S

MCP_BUF0_CLKENET_MII_55S RTL8211_CLK25M_CKXTAL1

ENET_INTR_L ENET_MIIENET_MII_55S ENET_INTR_L

MCP_CLK25M_BUF0 MCP_BUF0_CLKENET_MII_55S MCP_CLK25M_BUF0_R

MCP_MII_COMP_GNDMCP_MII_COMP MCP_MII_COMP

MCP_MII_COMP_VDDMCP_MII_COMP MCP_MII_COMP

ENET_RXD_R<3..0>ENET_MIIENET_MII_55SENET_RXD<0>ENET_MIIENET_MII_55S

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18 31

18 31

31

31

9 31

9 31

9 31

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32

32

9 31

9 31

31

18 31

9 31

31 32

18 31

31

9 31

18

18

31

18 31




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NET_TYPE

PHYSICAL SPACING

SMC SMBus Net PropertiesSPACINGPHYSICAL

NET_TYPE


SMBus Charger Net Properties

SMC ConstraintsSYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010

=STANDARD =STANDARD 0.1 MM 0.1 MM* =STANDARD=STANDARD1TO1_DIFFPAIRSMB_55S SMBUS_SMC_A_S3_SCLSMBUS_SMC_A_S3_SCL SMB

SMBUS_SMC_MGMT_SDASMBUS_SMC_MGMT_SDA SMBSMB_55S

SMBUS_SMC_MGMT_SCLSMBSMB_55SSMBUS_SMC_MGMT_SCL

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCLSMBSMB_55S

SMBUS_SMC_BSA_SDASMBUS_SMC_BSA_SDA SMBSMB_55S

SMBSMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCLSMB_55S

SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDASMBSMB_55S

SMBUS_SMC_B_S0_SDA SMB SMBUS_SMC_B_S0_SDASMB_55S

SMBUS_SMC_B_S0_SCL SMB SMBUS_SMC_B_S0_SCLSMB_55S

SMBUS_SMC_A_S3_SDA SMB_55S SMBUS_SMC_A_S3_SDASMB

CHGR_CSI 1TO1_DIFFPAIR CHGR_CSI_P1TO1_DIFFPAIR CHGR_CSI_N

CHGR_CSI_R_P1TO1_DIFFPAIR

CHGR_CSO_R_N1TO1_DIFFPAIR

CHGR_CSO_N1TO1_DIFFPAIR

CHGR_CSO_P1TO1_DIFFPAIRCHGR_CSO

CHGR_CSI_R_N1TO1_DIFFPAIR

CHGR_CSO_R_P1TO1_DIFFPAIR

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55

40 55

55

55

55

40 55




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OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE




























































GRAPHICS NET PROPERTIES

(DP_EXT_AUX_CH)

MCP Fanout Constraint Relaxations

NET_TYPE

Power Net PropertiesPHYSICAL

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

Misc Net Properties

(PCIE_AP)

PHYSICALELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

NET_TYPE

SPACING

(USB_CAMERA)

(USB_CAMERA)

(USB_EXTA)

(USB_EXTA)

(USB_TPAD)


NET_TYPE

SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET

(USB_TPAD)

(USB_EXTA)

(USB_EXTA)

Audio Net Properties

(DP_EXT_ML)

I277

I296

I297

I298

I299

I300

I301


K87 SPECIFIC CONSTRAINTS

500 MILMCP_MEM_COMP TOP 0.1 MM

MCP_DV_COMP TOP 500 MIL0.1 MM

MEM_40S 5.8 MM0.09 MM*

=1:1_DIFFPAIR* =55_OHM_SESENSE_1TO1_55S =55_OHM_SE=55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR

250 MIL0.25 MM*MCP_DV_COMP

500 MILTOPMCP_MII_COMP 0.1 MM

PWR_P2MMSB_POWERSATA *

GND_P2MMSATA *GND

GND_P2MMCLK_PCIE *GND

SB_POWER PWR_P2MMUSB *

PWR_P2MMSB_POWERCLK_PCIE *

GND GND_P2MMUSB *

MEM_DATA GND_P2MM*GND

10000.20 MM*GND_P2MM

?25 MILS*ENETCONN

MEM_POWER ?* =STANDARD

10000.20 MM*PWR_P2MM

?=2:1_SPACING*AUDIO

=1:1_DIFFPAIR*DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR

MEM_CLK GND_P2MM*GND

GND_P2MMCPU_COMP *GND

PWR_P2MMMEM_POWER *MEM_CMD

CPU_VCCSENSE GND_P2MM*GND

PWR_P2MMMEM_POWER *MEM_CLK

PWR_P2MMMEM_POWER *MEM_CTRL

MEM_DQS GND_P2MM*GND

CPU_GTLREF GND_P2MM*GND

GND_P2MMPCIE *GND

=2:1_SPACING*SENSE ?

=1:1_DIFFPAIR* =55_OHM_SETHERM_1TO1_55S =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR=55_OHM_SE

?=2:1_SPACING*THERM

MEM_CTRL GND_P2MM*GND

*MEM_CMD GND_P2MMGND

MEM_POWER PWR_P2MM*MEM_DATA

GND_P2MMCLK_FSB *GND

GND_P2MMGND *LVDS

*GND ?=STANDARD

TOP 0.1 MMMCP_USB_RBIAS 500 MIL

MEM_POWER *MEM_DQS PWR_P2MM

GND_P2MM*GNDENET_MDI

SATA_HDD_D2R_FILT_PSATA_90D SATASATA_HDD_D2R_FILT_NSATASATA_90D

SATASATA_90D SATA_HDD_D2R_UF_P

SATA_90D SATA SATA_HDD_D2R_UF_N

SATA_90D SATA SATA_HDD_R2D_UF_P

SATA_90D SATA SATA_HDD_R2D_UF_N

ENETCONN_N<3..0>ENETCONNENET_MDI_100D

SATASATA_90D SATA_ODD_D2R_UF_N

SATA_ODD_R2D_UF_NSATASATA_90D

ENETCONN_P<3..0>ENET_MDI_100D ENETCONN

SATA_ODD_R2D_UF_PSATA_90D SATA

USBUSB_90DUSB_BT CONN_USB2_BT_PPCIE_90D PCIE CONN_PCIE_MINI_R2D_NPCIE_90D PCIEPCIE_AP_R2D CONN_PCIE_MINI_R2D_P

PCIEPCIE_90D CONN_PCIE_MINI_D2R_N

DIFFPAIR AUDIO BI_MIC_P

AUDIO SSM2315R_NDIFFPAIR

DP_EXT_DDC_DATADISPLAYPORTDP_90DDP_EXT_DDC_CLKDISPLAYPORTDP_90D

DP_EXT_ML_C_N<3..0>DISPLAYPORTDP_90D

DP_EXT_ML_F_N<3..0>DP_90D DISPLAYPORT

DP_EXT_AUX_CH_C_NDP_90D DISPLAYPORT

DP_EXT_ML_F_P<3..0>DISPLAYPORTDP_90D

DP_EXT_ML_N<3..0>DP_90D DISPLAYPORT

AUDIODIFFPAIR SPKRCONN_S_OUT_PSPK_OUT

AUDIO SPKRCONN_L_OUT_PDIFFPAIRSPK_OUT

DIFFPAIR SPKRCONN_R_OUT_PAUDIOSPK_OUT

DIFFPAIR SPKRCONN_R_OUT_NAUDIO

AUDIO AUD_SPKRAMP_RIN_PDIFFPAIR

AUDIO AUD_SPKRAMP_RIN_NDIFFPAIR

SATA SATA_HDD_D2R_NORDRV_PSATA_90D

SENSE_1TO1_55S SENSE ISNS_1V5_S3_N

THERM_1TO1_55S THERMMCP_THMDIODE MCP_THMDIODE_P

SENSE_1TO1_55SSENSE_DIFFPAIR SENSE ISNS_LCDBKLT_P

SENSE_1TO1_55S SENSE ISNS_HDD_R_P

SENSESENSE_1TO1_55S ISNS_AIRPORT_R_NSENSESENSE_1TO1_55S ISNS_AIRPORT_R_P

SENSE_DIFFPAIR SENSESENSE_1TO1_55S ISNS_HDD_PSENSESENSE_1TO1_55S ISNS_HDD_N

SENSESENSE_1TO1_55S ISNS_HDD_R_N

SENSE_1TO1_55S SENSE ISNS_LCDBKLT_R_P

ISNS_CPUVTT_PSENSESENSE_DIFFPAIR SENSE_1TO1_55S

SENSE ISNS_CPUVTT_NSENSE_1TO1_55SMCPCORES0_VSEN_PSENSE_DIFFPAIR SENSESENSE_1TO1_55SMCPCORES0_VSEN_NSENSE_1TO1_55S SENSEPP1V5R1V35_S3MEM_POWER

PP1V5_S0SB_POWER

PCIE_CLK100M_MINI_CONN_NCLK_PCIECLK_PCIE_100D

USB_90D USB USB_EXTA_MUXED_N

CLK_PCIECLK_PCIE_100D PCIE_CLK100M_AP_CONN_NCLK_PCIECLK_PCIE_100D PCIE_CLK100M_AP_CONN_P

LVDS_100D LVDS LVDS_IG_A_CLK_F_PLVDS_IG_A_CLK

SATASATA_90D SATA_HDD_R2D_RDRV_OUT_P

USBUSB_90D USB_EXTA_MUXED_P

USB_90D USB USB_LT1_P

USB_90D USB USB_LT1_N

USBUSB_90D USB_TPAD_R_P

USB USB_CAMERA_CONN_NUSB_90D

LVDS_100D LVDS LVDS_IG_A_CLK_F_N

AUDIO AUD_SPKRAMP_LIN_NDIFFPAIR

DIFFPAIR AUDIO AUD_SPKRAMP_SUBIN_PAUDIODIFFPAIR AUD_SPKRAMP_SUBIN_N

AUDIO SSM2315L_NDIFFPAIR

AUDIO SSM2315S_PDIFFPAIR

AUDIO SSM2315R_PDIFFPAIR

DIFFPAIR AUDIO SPKRCONN_S_OUT_N

AUDIO BI_MIC_NDIFFPAIR

CPUTHMSNS_D1_PTHERMTHERM_1TO1_55SCPUTHMSNS_D2CPUTHMSNS_D1_NTHERMTHERM_1TO1_55S

CPUTHMSNS_D2_NTHERM_1TO1_55S THERM

THERM CPU_THERMD_NTHERM_1TO1_55S

THERM_1TO1_55S THERM MCP_THMDIODE_N

SENSE ISNS_1V5_S3_R_PSENSE_1TO1_55SISNS_1V5_S3_R_NSENSE_1TO1_55S SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR SENSE ISNS_AIRPORT_PSENSE_1TO1_55S ISNS_AIRPORT_NSENSE

SENSE ISNS_LCDBKLT_NSENSE_1TO1_55S

SENSE_DIFFPAIR SENSE_1TO1_55S ISNS_ODD_PSENSE

SENSE_1TO1_55S SENSE ISNS_LCDBKLT_R_N

ISNS_ODD_R_NSENSESENSE_1TO1_55S

SENSE ISNS_ODD_NSENSE_1TO1_55S

SENSE ISNS_ODD_R_PSENSE_1TO1_55S

AUDIO HS_MIC_PDIFFPAIR

AUDIODIFFPAIR HS_MIC_N

AUDIODIFFPAIR SPKRCONN_L_OUT_N

AUDIO SSM2315S_NDIFFPAIR

DIFFPAIR SSM2315L_PAUDIO

AUDIO AUD_SPKRAMP_LIN_PDIFFPAIR

SENSE_DIFFPAIR SENSE ISNS_1V5_S3_PSENSE_1TO1_55S

THERM_1TO1_55S THERM MCPTHMSNS_D2_NMCPTHMSNS_D2 THERM_1TO1_55S THERM MCPTHMSNS_D2_P

CPU_THERMD THERM_1TO1_55S THERM CPU_THERMD_P

CPUTHMSNS_D2_PCPUTHMSNS_D2 THERM_1TO1_55S THERM

USB_90D USB USB_CAMERA_CONN_PUSB_90D USB USB_TPAD_R_N

DP_90D DP_EXT_ML_C_P<3..0>DISPLAYPORT

DP_EXT_ML_P<3..0>DP_90D DISPLAYPORT

DP_90D DP_EXT_AUX_CH_C_PDISPLAYPORT

CONN_USB_EXTA_PUSB_90DUSB_EXTA USB

USBUSB_90D CONN_USB_EXTA_N

USBUSB_90D CONN_USB_EXTB_NUSB_EXTB USB_90D USB CONN_USB_EXTB_P

USB_LT2_NUSB_90D USB

USB_LT2_PUSB_90D USB

PP3V3_S0SB_POWER

PP3V3_S5SB_POWER

CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_CONN_PMCP_PE1_REFCLK

SATA_90D SATA SATA_HDD_R2D_NORDRV_NSATASATA_90D SATA_HDD_R2D_NORDRV_P

SATA_90D SATA SATA_HDD_R2D_RDRV_OUT_N

SATA_90D SATA SATA_HDD_D2R_RDRV_OUT_P

SATA_90D SATA_HDD_D2R_RDRV_OUT_NSATA

SATA_90D SATA SATA_HDD_D2R_NORDRV_N

USBUSB_90D CONN_USB2_BT_N

PCIEPCIE_90D CONN_PCIE_MINI_D2R_PPCIE_AP_D2R

SATA_90D SATA SATA_HDD_R2D_RDRV_IN_NSATA_90D SATA SATA_HDD_R2D_RDRV_IN_P

SATASATA_90D SATA_ODD_D2R_UF_P

SATA_HDD_D2R_RDRV_IN_NSATA_90D SATA

SATA_HDD_D2R_RDRV_IN_PSATASATA_90D

GNDGND

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33

33

33

33

33

33

33

33

7 30

7 9 30

7 9 30

7 9 30

7 52 53

65

65

66

66

9 66

66

9 66

19 41

46 67

46

46

46

33 46

33 46

46

40

40

22 59

22 59

7 8

7 8 62

7 30

34 72

7 64

34 72

43

7 64

7 64

7 52 53

41

41

41

10 41

19 41

30 46

30 46

46 67

33 46

46

33 46

46

52 53

52 53

10 41

41

7 64

43

66

9 66

9 66

34

34

34

34

7 8 62

7 8 62

7 30

7 30

7 9 30

33




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TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS

















































TABLE_SPACING_RULE_ITEMTABLE_PHYSICAL_RULE_ITEM


















PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM



K87 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS


K87 RULE DEFINITIONS

15.5.1MMNO_TYPE,BGA_P1MMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

Y 12.7 MM =DEFAULT=DEFAULT =DEFAULT=DEFAULTSTANDARD *

?0.15 MM*1.5:1_SPACING

* ?2.5:1_SPACING 0.25 MM

4:1_SPACING 0.4 MM ?*

50_OHM_SE 0.115 MMY 0.115 MMTOP,BOTTOM

0.126 MM =STANDARDY40_OHM_SE * =STANDARD=STANDARD0.100 MM

0.310 MMY27P4_OHM_SE 0.310 MMTOP,BOTTOM

0.112 MM 0.112 MM 0.220 MM0.220 MM90_OHM_DIFF YTOP,BOTTOM

=STANDARDN =STANDARD=STANDARD* =STANDARD100_OHM_DIFF =STANDARD

1:1_DIFFPAIR * =STANDARD 0.1 MM0.1 MM=STANDARD=STANDARDY

Y 0.091 MM 0.230 MM0.091 MMTOP,BOTTOM100_OHM_DIFF 0.230 MM

ISL3,ISL4,ISL9,ISL10 Y 0.244 MM 0.244 MM0.075 MM0.075 MM100_OHM_DIFF

N =STANDARD =STANDARD90_OHM_DIFF =STANDARD =STANDARD* =STANDARD

0.200 MM0.185 MMY70_OHM_DIFF TOP,BOTTOM 0.100 MM 0.200 MM

4X_DIELECTRIC ?* 0.252 MM


?TOP,BOTTOM4X_DIELECTRIC 0.280 MM

TOP,BOTTOM ?0.210 MM3X_DIELECTRIC

BGA_P3MMFSB_DSTBFSB_DSTB BGA_P1MM

BGA_P2MM*CLK_SLOW BGA_P1MM

BGA_P1MMCLK_LPC BGA_P2MM*

CLK_FSB BGA_P1MM BGA_P2MM*

?*2:1_SPACING 0.2 MM

?TOP,BOTTOM 0.140 MM2X_DIELECTRIC

?=DEFAULT*BGA_P3MM

?*BGA_P2MM =DEFAULT

?* =DEFAULTSTANDARD

DEFAULT ?0.1 MM*

=DEFAULT* ?BGA_P1MM

3:1_SPACING ?* 0.3 MM

1.5X_DIELECTRIC 0.095 MM ?*

?0.350 MMTOP,BOTTOM5X_DIELECTRIC


2X_DIELECTRIC ?0.126 MM*

TOP,BOTTOM1.5X_DIELECTRIC 0.105 MM ?0.100 MMY40_OHM_SE TOP,BOTTOM 0.165 MM

0.076 MM 0.076 MM =STANDARDY =STANDARD=STANDARD*50_OHM_SE

0.090 MMTOP,BOTTOM Y55_OHM_SE 0.090 MM

0 MMY* =50_OHM_SEDEFAULT 0.100MM 30 MM 0 MM

=STANDARD =STANDARDN* =STANDARD =STANDARD70_OHM_DIFF =STANDARD

=STANDARD 0.224 MM0.151 MMY70_OHM_DIFF ISL3,ISL4,ISL9,ISL10 0.100 MM 0.224 MM

0.234 MM0.234 MM0.095 MM0.095 MMY90_OHM_DIFF ISL3,ISL4,ISL9,ISL10

0.222 MM0.222 MM =STANDARD=STANDARDY*27P4_OHM_SE =STANDARD

0.076 MMY =STANDARD =STANDARD=STANDARD55_OHM_SE 0.076 MM*

BGA_P1MMBGA_P1MM** MEM_40S STANDARDBGA_P1MM

BGA_P2MMBGA_P1MM*MEM_CLK

CLK_PCIE * BGA_P1MM BGA_P2MM

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