TAPIS PELEWAT RENDAH DENGAN KAPASITOR TERSAKLAR (LOW PASS SWITCHED CAPASITOR FILTER ) TUGAS AKHIR Diajukan untuk memenuhi salah satu Syarat Memperoleh Gelar Sarjana Teknik Program Studi Teknik Elektro Disusun oleh : Maria Rosanti Dadi Ramba NIM : 995114065 JURUSAN TEKNIK ELEKTRONIKA FAKULTAS TEKNIK UNIVERSITAS SANATA DHARMA YOGYAKARTA 2007
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TAPIS PELEWAT RENDAH DENGAN KAPASITOR TERSAKLAR
(LOW PASS SWITCHED CAPASITOR FILTER )
TUGAS AKHIR
Diajukan untuk memenuhi salah satu Syarat
Memperoleh Gelar Sarjana Teknik Program Studi Teknik Elektro
Disusun oleh :
Maria Rosanti Dadi Ramba
NIM : 995114065
JURUSAN TEKNIK ELEKTRONIKA
FAKULTAS TEKNIK
UNIVERSITAS SANATA DHARMA
YOGYAKARTA
2007
TAPIS PELEWAT RENDAH DENGAN KAPASITOR TERSAKLAR
(LOW PASS SWITCHED CAPASITOR FILTER )
TUGAS AKHIR
Diajukan untuk memenuhi salah satu Syarat Memperoleh Gelar Sarjana Teknik
Program Studi Teknik Elektro
Disusun oleh :
Maria Rosanti Dadi Ramba
NIM : 995114065
JURUSAN TEKNIK ELEKTRONIKA
FAKULTAS TEKNIK
UNIVERSITAS SANATA DHARMA
YOGYAKARTA
2007
i
ii
iii
MOTO DAN PERSEMBAHAN
Tuhan tidak berjanji langit akan selalu biru
Bunga di sepanjang jalanmu,
Lautan tanpa gelombang.
Tapi ……
Ia berjanji beserta kita
Mendampingi kita dalam segala keadaan
Bersyukurlah untuk kesalahanmu, karena
Semuanya akan memberikan pelajaran berharga
Bersyukurlah untuk semua kesusahannmu dan itu semua akan menjadi berkatmu.
Bersyukurlah bila kamu tidak mengetahui semuanya, karena
Hal itu memberikan kesempatan padamu untuk belajar.
Skripsi ini kupersembahkan untuk :
Kemuliaan Tuhan di Surga dan untuk
Kedua orang tuaku serta kakak dan adik-
adikku.
iv
PERNYATAAN KEASLIAN KARYA
Saya menyatakan dengan sesungguhnya bahwa skripsi yang saya tulis ini tidak
memuat karya atau bagian karya orang lain, kecuali yang telah disebutkan dalam
kutipan dan daftar pustaka, sebagaimana layaknya karya ilmiah.
Yogyakarta, 29 Januari 2007
Penulis
Maria Rosanti Dadi Ramba
v
TAPIS PELEWAT RENDAH DENGAN KAPASITOR TERSAKLAR
Nama : Maria Rosanti Dadi Ramba
Nim : 995114065
INTISARI
Berawal dari semakin berkembangnya teknologi khususnya teknologi telekomunikasi antara lain telepon , radio dan berbagai alat elektronik, filter digunakan untuk membatasi arus listrik dengan frekuensi tertentu. Penelitian ini membicarakan tentang tapis kapasitor tersaklar di mana nilai dari resistansi akan di ganti dengan sebuah kapasitor dan sakar MOS. Penapis kapasitor tersaklar terdiri atas sebuah amplifier, kapasitor, dan saklar MOS. Nilai frekuensi cuttoff 5 Khz, dan frekuensi penyaklaran 150 Khz. Keluaran dari frekuensi generator digunakan sebagai masukan dari penapis kapasitor dan batasannya dari 10Hz sampai 50Khz. Kata kunci : Penapis aktif, kapasitor tersaklar, penapis pelewat rendah.
vi
LOW PASS SWITCHED CAPASITOR FILTER
Name: Maria Rosanti Dadi Ramba
Nim :995114065
ABSTRACT
Early from progressivelly expand technological on specially telecomunications technology, for example telephone, radio, and various all electronic appliance, filter is used to limit the electrics current with the certain frequency that is required. The objective of this research is about the low pass switched capasitor , where the value of resistansi of the filter would be change by capasitor and Mos switched. The low pass switched capasitor filter consists of amplifier, capacitor,and MOS switched. Cutt off frequency is design about 5khz and the clock frequency is 150 Khz. The output from frequency generator is used as input to capasitor filter and it is about 10 Hz up to 5OKhz. Keyword: Active filter,switched capasitor, low pass filter.
vii
KATA PENGANTAR
Puji dan syukur kepada Allah Bapa di surga, Allah Putera dan Allah Roh
Kudus yang telah memberikan limpahan anugerah, kekuatan,kesabaran, kesehatan dan
penghiburan sehingga penulis dapat menyelesaikan skripsi yang berjudul "TAPIS
PELEWAT RENDAH DENGAN KAPASITOR TERSAKLAR “.
Penulisan skripsi ini dapat diselesaikan bukan atas usaha penulis sendiri
melainkan juga berkat bantuan , dorongan dan bimbingan dari berbagai pihak. Oleh
karena itu penulis ingin mengucapkan banyak terima kasih terutama kepada semua
pihak yang telah membantu penulis hingga terselesaikannya skripsi ini. Ucapan
terima kasih penulis sampaikan kepada :
1. Bapak A. Bayu Primawan, ST,M.Eng, selaku Ketua Jurusan Teknik Elektro
Fakultas Teknik Universitas Sanata Dharma.Bapak Martanto, ST, MT, selaku
dosen pembimbing skripsi yang telah membimbing dan memberikan saran.
2. Seluruh staf pengajar teknik elektro yang telah banyak memberikan
pengetahuan dan bimbingan kepada penulis selaMa kuliah di Universitas
Sanata Dharma.
4. Karyawan laboratorium Teknik Elektro yang telah banyak memberikan bantuan
selama penulis mencari data di lab.
viii
5. Kedua orang tuaku, Bapak Rosi Fransiskus dan lbu Benedikta M yang selalu
memotivasi, mendoakan sepanjang waktu serta memberikan kasih sayangnya
untuk menyelesaikan tugas akhirku.
6. Kakak dan adekku, Yani, Oscar, Helmin, Gundis yang selalu memotivasi diriku
LF353Wide Bandwidth Dual JFET Input Operational AmplifierGeneral DescriptionThese devices are low cost, high speed, dual JFET inputoperational amplifiers with an internally trimmed input offsetvoltage (BI-FET II™ technology). They require low supplycurrent yet maintain a large gain bandwidth product and fastslew rate. In addition, well matched high voltage JFET inputdevices provide very low input bias and offset currents. TheLF353 is pin compatible with the standard LM1558 allowingdesigners to immediately upgrade the overall performance ofexisting LM1558 and LM358 designs.
These amplifiers may be used in applications such as highspeed integrators, fast D/A converters, sample and holdcircuits and many other circuits requiring low input offsetvoltage, low input bias current, high input impedance, highslew rate and wide bandwidth. The devices also exhibit lownoise and offset voltage drift.
Featuresn Internally trimmed offset voltage: 10 mVn Low input bias current: 50pAn Low input noise voltage: 25 nV/√Hzn Low input noise current: 0.01 pA/√Hzn Wide gain bandwidth: 4 MHzn High slew rate: 13 V/µsn Low supply current: 3.6 mAn High input impedance: 1012Ωn Low total harmonic distortion : ≤0.02%n Low 1/f noise corner: 50 Hzn Fast settling time to 0.01%: 2 µs
Typical Connection
00564914
Simplified Schematic1/2 Dual
00564916
Connection DiagramDual-In-Line Package
00564917
Top ViewOrder Number LF353M, LF353MX or LF353N
See NS Package Number M08A or N08E
BI-FET II™ is a trademark of National Semiconductor Corporation.
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage ±18V
Power Dissipation (Note 2)
Operating Temperature Range 0˚C to +70˚C
Tj(MAX) 150˚C
Differential Input Voltage ±30V
Input Voltage Range (Note 3) ±15V
Output Short Circuit Duration Continuous
Storage Temperature Range −65˚C to +150˚C
Lead Temp. (Soldering, 10 sec.) 260˚C
Soldering InformationDual-In-Line Package
Soldering (10 sec.) 260˚C
Small Outline Package
Vapor Phase (60 sec.) 215˚C
Infrared (15 sec.) 220˚C
See AN-450 “Surface Mounting Methods and Their Effecton Product Reliability” for other methods of solderingsurface mount devices.
ESD Tolerance (Note 8) 1000V
θJA M Package TBD
Note 1: Absolute Maximum Ratings indicate limits beyond which damage tothe device may occur. Operating ratings indicate conditions for which thedevice is functional, but do not guarantee specific performance limits. Elec-trical Characteristics state DC and AC electrical specifications under particu-lar test conditions which guarantee specific performance limits. This assumesthat the device is within the Operating Ratings. Specifications are not guar-anteed for parameters where no limit is given, however, the typical value is agood indication of device performance.
DC Electrical Characteristics(Note 5)
Symbol Parameter Conditions LF353 Units
MIn Typ Max
VOS Input Offset Voltage RS=10kΩ, TA=25˚C 5 10 mV
Over Temperature 13 mV
∆VOS/∆T Average TC of Input Offset Voltage RS=10 kΩ 10 µV/˚C
IOS Input Offset Current Tj=25˚C, (Notes 5, 6) 25 100 pA
Tj≤70˚C 4 nA
IB Input Bias Current Tj=25˚C, (Notes 5, 6) 50 200 pA
Tj≤70˚C 8 nA
RIN Input Resistance Tj=25˚C 1012 ΩAVOL Large Signal Voltage Gain VS=±15V, TA=25˚C 25 100 V/mV
VO=±10V, RL=2 kΩOver Temperature 15 V/mV
VO Output Voltage Swing VS=±15V, RL=10kΩ ±12 ±13.5 V
VCM Input Common-Mode Voltage VS=±15V ±11 +15 V
Range −12 V
CMRR Common-Mode Rejection Ratio RS≤ 10kΩ 70 100 dB
PSRR Supply Voltage Rejection Ratio (Note 7) 70 100 dB
IS Supply Current 3.6 6.5 mA
AC Electrical Characteristics(Note 5)
Symbol Parameter Conditions LF353 Units
Min Typ Max
Amplifier to Amplifier Coupling TA=25˚C, f=1 Hz−20 kHz −120 dB
(Input Referred)
SR Slew Rate VS=±15V, TA=25˚C 8.0 13 V/µs
GBW Gain Bandwidth Product VS=±15V, TA=25˚C 2.7 4 MHz
en Equivalent Input Noise Voltage TA=25˚C, RS=100Ω, 16
f=1000 Hz
in Equivalent Input Noise Current Tj=25˚C, f=1000 Hz 0.01
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AC Electrical Characteristics (Continued)(Note 5)
Symbol Parameter Conditions LF353 Units
Min Typ Max
THD Total Harmonic Distortion AV=+10, RL=10k,VO=20Vp−p,BW=20 Hz-20 kHz
<0.02 %
Note 2: For operating at elevated temperatures, the device must be derated based on a thermal resistance of 115˚C/W typ junction to ambient for the N package,and 158˚C/W typ junction to ambient for the H package.
Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 4: The power dissipation limit, however, cannot be exceeded.
Note 5: These specifications apply for VS=±15V and 0˚C≤TA≤+70˚C. VOS, IBand IOS are measured at VCM=0.
Note 6: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, Tj. Due to the limitedproduction test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambienttemperature as a result of internal power dissipation, PD. Tj=TA+θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink isrecommended if input bias current is to be kept to a minimum.
Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS= ±6V to ±15V.
Note 8: Human body model, 1.5 kΩ in series with 100 pF.
Typical Performance CharacteristicsInput Bias Current Input Bias Current
0056491800564919
Supply Current Positive Common-Mode Input Voltage Limit
0056492000564921
LF353
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Typical Performance Characteristics (Continued)
Negative Common-Mode Input Voltage Limit Positive Current Limit
00564922 00564923
Negative Current Limit Voltage Swing
00564924 00564925
Output Voltage Swing Gain Bandwidth
00564926 00564927
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Typical Performance Characteristics (Continued)
Bode Plot Slew Rate
00564928 00564929
Distortion vs. Frequency Undistorted Output Voltage Swing
0056493000564931
Open Loop Frequency Response Common-Mode Rejection Ratio
00564932 00564933
LF353
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Typical Performance Characteristics (Continued)
Power Supply Rejection Ratio Equivalent Input Noise Voltage
0056493400564935
Open Loop Voltage Gain (V/V) Output Impedance
00564936 00564937
Inverter Settling Time
00564938
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Pulse ResponseSmall Signaling Inverting
00564904
Large Signal Inverting
00564906
Small Signal Non-Inverting
00564905
Large Signal Non-Inverting
00564907
Current Limit (RL = 100Ω)
00564908
Application HintsThese devices are op amps with an internally trimmed inputoffset voltage and JFET input devices (BI-FET II). TheseJFETs have large reverse breakdown voltages from gate tosource and drain eliminating the need for clamps across theinputs. Therefore, large differential input voltages can easilybe accommodated without a large increase in input current.The maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltagesshould be allowed to exceed the negative supply as this willcause large currents to flow which can result in a destroyedunit.
Exceeding the negative common-mode limit on either inputwill force the output to a high state, potentially causing areversal of phase to the output. Exceeding the negativecommon-mode limit on both inputs will force the amplifieroutput to a high state. In neither case does a latch occur
LF353
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Application Hints (Continued)
since raising the input back within the common-mode rangeagain puts the input stage and thus the amplifier in a normaloperating mode.
Exceeding the positive common-mode limit on a single inputwill not change the phase of the output; however, if bothinputs exceed the limit, the output of the amplifier will beforced to a high state.
The amplifiers will operate with a common-mode input volt-age equal to the positive supply; however, the gain band-width and slew rate may be decreased in this condition.When the negative common-mode voltage swings to within3V of the negative supply, an increase in input offset voltagemay occur.
Each amplifier is individually biased by a zener referencewhich allows normal circuit operation on ±6V power sup-plies. Supply voltages less than these may result in lowergain bandwidth and slew rate.
The amplifiers will drive a 2 kΩ load resistance to ±10V overthe full temperature range of 0˚C to +70˚C. If the amplifier isforced to drive heavier load currents, however, an increasein input offset voltage may occur on the negative voltageswing and finally reach an active current limit on both posi-tive and negative swings.
Precautions should be taken to ensure that the power supplyfor the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in asocket as an unlimited current surge through the resultingforward diode within the IC could cause fusing of the internalconductors and result in a destroyed unit.
As with most amplifiers, care should be taken with leaddress, component placement and supply decoupling in orderto ensure stability. For example, resistors from the output toan input should be placed with the body close to the input tominimize “pick-up” and maximize the frequency of the feed-back pole by minimizing the capacitance from the input toground.
A feedback pole is created when the feedback around anyamplifier is resistive. The parallel resistance and capacitancefrom the input of the device (usually the inverting input) to ACground set the frequency of the pole. In many instances thefrequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently thereis negligible effect on stability margin. However, if the feed-back pole is less than approximately 6 times the expected 3dB frequency a lead capacitor should be placed from theoutput to the input of the op amp. The value of the addedcapacitor should be such that the RC time constant of thiscapacitor and the resistance it parallels is greater than orequal to the original feedback pole time constant.
Detailed Schematic
00564909
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Typical ApplicationsThree-Band Active Tone Control
Order Number LF353M or LF353MXNS Package Number M08A
Molded Dual-In-Line PackageOrder Number LF353N
NS Package N08E
LF353
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.
2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer ProductsStewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National SemiconductorAmericas CustomerSupport CenterEmail: [email protected]: 1-800-272-9959
National SemiconductorEurope Customer Support Center
National SemiconductorAsia Pacific CustomerSupport CenterEmail: [email protected]
National SemiconductorJapan Customer Support CenterFax: 81-3-5639-7507Email: [email protected]: 81-3-5639-7560
www.national.com
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
• Maximum Input Current of 1 µA at 18V Over Full Pack-age Temperature Range; 100nA at 18V and +25 oC
• Noise Margin (Over Full Package Temperature Range):- 1V at VDD = 5V- 2V at VDD = 10V- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative StandardNo. 13B, “Standard Specifications for Description of‘B’ Series CMOS Devices”
Applications• Registers
• Counters
• Control Circuits
DescriptionCD4013BMS consists of two identical, independent datatype flip-flops. Each flip-flop has independent data, set,reset, and clock inputs and Q and Q outputs. These devicescan be used for shift register applications, and, byconnecting Q output to the data input, for counter and toggleapplications. The logic level present at the D input istransferred to the Q output during the positive goingtransition of the clock pulse. Setting or resetting isindependent of the clock and is accomplished by a high levelon the set or reset line, respectively.
The CD4013BMS is supplied in these 14 lead outline pack-ages:
Braze Seal DIP H4Q
Frit Seal DIP H1B
Ceramic Flatpack H3W
November 1994
File Number 3080
7-63
Specifications CD4013BMS
Absolute Maximum Ratings Reliability InformationDC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5VDC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mAOperating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Maximum Package Power Dissipation (PD) at +125oCFor TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mWFor TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/oC to 200mWDevice Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1)GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 2 µA
2 +125oC - 200 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 2 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >VDD/2
VOL <VDD/2
V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low(Note 2)
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterizedon initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
S E M I C O N D U C T O R CD4016BMSCMOS Quad Bilateral Switch
Applications• Analog Signal Switching/Multiplexing
• Signal Gating
• Squelch Control
• Chopper
• Modulator
• Demodulator
• Commutating Switch
• Digital Signal Switching/Multiplexing
• CMOS Logic Implementation
• Analog to Digital & Digital to Analog Conversion
• Digital Control of Frequency, Impedance, Phase, andAnalog Signal Gain
DescriptionCD4016BMS Series types are quad bilateral switches intendedfor the transmission or multiplexing of analog or digital signals.Each of the four independent bilateral switches has a single con-trol signal input which simultaneously biases both the p and ndevice in a given switch on or off.
The CD4016BMS is supplied in these 14 lead outline packages:
Braze Seal DIP H4Q
Frit Seal DIP H1B
Ceramic Flatpack H3W
Features• Transmission or Multiplexing of Analog or Digital Signals
• High Voltage Type (20V Rating)
• 20V Digital or ±10V Peak-to-Peak Switching
• 280Ω Typical On-State Resistance for 15V Operation
• Switch On-State Resistance Matched to Within 10 ΩTyp. Over 15V Signal Input Range
• High On/Off Output Voltage Ratio: 65dB Typ. at FIS =10kHz, RL = 10k Ω
• High Degree of Linearity: <0.5% Distortion Typ. at FIS= 1kHz, VIS = 5Vp-p, VDD-VSS ≥ 10V, RL = 10kΩ
• Extremely Low Off State Switch Leakage Resulting inVery Low Offset Current and High Effective Off StateResistance: 100pA Typ. at VDD-VSS = 18V, T A = 25oC
• Extremely High Control Input Impedance (Control cir-cuit Isolated from Signal Circuit: 10 12Ω Typ.
• Low Crosstalk Between Switches: -50dB Typ. at FIS =0.9MHz, RL = 1kΩ
• Matched Control Input to Signal OutputCapacitance: Reduces Output Signal Transients
• Frequency Response, Switch On = 40MHz (Typ.)
• 100% Tested for Quiescent Current at 20V
• Maximum Control Input Current of 1 µA at 18V Over FullPackage Temperature Range; 100nA at 18V at +25 oC
• 5V, 10V and 15V Parametric Ratings
November 1994
File Number 3296
PinoutCD4016BMSTOP VIEW
SIG A IN
SIG A OUT
SIG B IN
SIG B OUT
CONTROL B
CONTROL C
VSS
VDD
CONTROL A
CONTROL D
SIG D IN
SIG D OUT
SIG C OUT
SIG C IN
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Functional Diagram
IN/OUT
OUT/IN
OUT/IN
IN/OUT
CONTROL B
CONTROL C
VSS
VDD
CONTROL A
CONTROL D
IN/OUT
OUT/IN
OUT/IN
IN/OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SWASIG A
SWD
SWB
SWC
SIG B
SIG C
SIG D
7-734
Specifications CD4016BMS
Absolute Maximum Ratings Reliability InformationDC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5VDC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mAOperating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Maximum Package Power Dissipation (PD) at +125oCFor TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mWFor TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/oC to 200mWDevice Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1)GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 0.5 µA
2 +125oC - 50 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 0.5 µA
Input Leakage Current IIL VC = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VC = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Input/Output LeakageCurrent (Switch Off)
IOZL VDD = 18V, VC = 0V, VIS = 18V,VOS = 0V
1 +25oC -100 - nA
2 +125oC -1000 - nA
3 -55oC -100 - nA
Input/Output LeakageCurrent (Switch Off)
IOZH VDD = 18V, VIS = 18V, VOS = 0V 1 +25oC - 100 nA
2 +125oC - 1000 nA
3 -55oC - 100 nA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
On-State ResistanceRL = 10K Returned toVDD-VSS/2
RON10 VIS = VDD or VSS, VDD = 10V 1 +25oC - 660 Ω
2 +125oC - 960 Ω
3 -55oC - 600 Ω
RON10 VIS = 4.75V or 5.75V, VDD = 10V 1 +25oC - 2000 Ω
2 +125oC - 2600 Ω
3 -55oC - 1870 Ω
RON15 VIS = VDD or VSS, VDD = 15V 1 +25oC - 400 Ω
2 +125oC - 600 Ω
3 -55oC - 360 Ω
RON15 VIS = 7.25 or 7.75, VDD = 15V 1 +25oC - 850 Ω
2 +125oC - 1230 Ω
3 -55oC - 775 Ω
Functional(Note 3)
F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >VDD/2
VOL <VDD/2
V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Switch ThresholdRL = 100K to VDD
SWTHRH5 VDD = 5V, VC = 1.5V, VIS = GND 1, 2, 3 +25oC, +125oC, -55oC 4.1 - V
SWTHRH15 VDD = 15V, VC = 2V, VIS = GND 1, 2, 3 +25oC, +125oC, -55oC 14.1 - V
7-735
Specifications CD4016BMS
Input Voltage Control,Low (Note 2)
VILC VDD = 5V, VOS = VDD, VIS = VSS,and VDD = 5V, VOS = VSS, VIS =VDD, |IIS| < 10µA
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented.2. Go/No Go test with limits applied to inputs3. VDD = 2.8V/3V, RL = 100K to VDD
VDD = 20V/18V, RL = 10K to VDD
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONSGROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Propagation DelaySignal Input to SignalOutput
TPHLTPLH
VDD = 5V, VIN = VDD or GND(Notes 1, 2)
9 +25oC - 100 ns
10, 11 +125oC, -55oC - 135 ns
Propagation DelayTurn On
TPZHTPZL
VDD = 5V, VIN = VDD or GND(Notes 2, 3)
9 +25oC - 70 ns
10, 11 +125oC, -55oC - 95 ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 1K, TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.25 µA
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterizedon initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K. Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 2.5 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold VoltageDelta
∆VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold VoltageDelta
∆VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >VDD/2
VOL <VDD/2
V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHLTPLH
VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x+25oCLimit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 OC
PARAMETER SYMBOL DELTA LIMIT
Supply Current - SSI IDD ±0.1µA
ON Resistance RONDEL10 ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
• Maximum Input Current of 1 µA at 18V Over Full Pack-age Temperature Range, 100nA at 18V and +25 oC
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative StandardNo. 13B, “Standard Specifications for Description of‘B’ Series CMOS Devices”
Applications• Wave and Pulse Shapers
• High Noise Environment Systems
• Monostable Multivibrators
• Astable Multivibrators
• NAND Logic
DescriptionCD4093BMS consists of four Schmitt trigger circuits. Eachcircuit functions as a two input NAND gate with Schmitt trig-ger action on both inputs. The gate switches at differentpoints for positive and negative going signals. The differencebetween the positive voltage (VP) and the negative voltage(VN) is defined as hysteresis voltage (VH) (see Figure 1).
The CD4093BMS is supplied in these 14 lead outline pack-ages:
Braze Seal DIP H4H
Frit Seal DIP H1B
Ceramic Flatpack H3W
File Number 3330
December 1992
CD4093BMSCMOS Quad 2-Input
NAND Schmitt Triggers
7-1075
Specifications CD4093BMS
Absolute Maximum Ratings Reliability InformationDC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5VDC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mAOperating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Maximum Package Power Dissipation (PD) at +125oCFor TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mWFor TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/oC to 200mWDevice Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1)GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 2 µA
2 +125oC - 200 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 2 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 5) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >VDD/2
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterizedon initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Input on terminals 1, 5, 8, 125. Input on terminals 1 and 2, 5 and 6, 8 and 9, or 12 and 13
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold VoltageDelta
∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold VoltageDelta
∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >VDD/2