June 11, 2014 [email protected] sawyes/courses.html 1 ECSE-6230 Semiconductor Devices and Models I Lecture 14 Prof. Shayla Sawyer Bldg. CII,

April 10, 2023 [email protected] www.rpi.edu/~sawyes/courses.html 1

ECSE-6230Semiconductor Devices and Models I

Lecture 14Prof. Shayla Sawyer

Bldg. CII, Rooms 8225Rensselaer Polytechnic Institute

Troy, NY 12180-3590Tel. (518)276-2164Fax. (518)276-2990

e-mail: [email protected]@rpi.edu www.rpi.edu/~sawyes/c

ourses.html April 10, 2023

mailto:[email protected]


Lecture Outline

• MOS Capacitor – Time Dependent Capacitance

Measurements– Current Voltage Characteristics of MOS Gate

Oxides

• Field Effect Transistor Introduction• Field Effect Transistor Basic Output

Characteristics

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Time Dependent Capacitance Measurements• During CV measurements, if

the gate bias is varied rapidly from accumulation to inversion

– Depletion width momentarily becomes greater than theoretical maximum for gate biases beyond VT

– Called deep depletion– Drops below Cmin for a

transient period– Depletion width, over a

characteristic time, collapses back to Cmin

• C-t called Zerbst technique to measure lifetime


Current-Voltage Characteristics of MOS Gate Oxides

• Ideally, the gate insulator does not conduct any current

• For real insulators there can be some leakage current

– Varies with voltage or electric field across the gate oxide

– Happens when electric field or temperature is sufficiently high

– There is a barrier ΔEC, carrier cannot go through the barrier classically but quantum mechanically they can tunnel through


Tunneling• Tunneling is essentially

independent of temperature, but strong dependence on applied voltage

• Fowler-Nordheim tunneling current IFN can be expressed as a function of the electric field in the gate oxide

– B is a constant depending on mn*

and barrier height• Direct tunneling

– Gate oxide becomes so thin the electrons tunnel through

What are the implications for modern devices?

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FET (Field Effect Transistor) concept• Current through two terminals is controlled by

voltage at the third terminal• Junction FET: control gate voltage varies depletion

width of reversed biased pn junction• Metal Semiconductor FET: junction is replaced by

Schottky barrier• Metal-insulator-semiconductor FET: Metal gate

electrode separated by an insulator• Oxide layer on Silicon is most common (MOSFET)• Unipolar (majority carrier) device rather than bipolar

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FET (Field Effect Transistor) Concept

• FET family tree• Distinguished in the way the gate capacitor is

formed

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MOSFET

MOSFET Basic Operation –A field-induced channel to connect two adjacent source and drain

junctions.Features:• 4th terminal (substrate or backgate terminal)• MOS-induced channel• Pinchoff near the drain end• Parasitic npn


Water Analogy: MOSFET

• When the source and drain are level, there is no flow VDS=0

• Whatever depth in the canal can be varied by the gear and track (VGS)

• When the drain is lower than the source, water flows along the canal

• The flow is limited by the channel capacity, lowering the drain further only increases the height of the waterfall at its edge


MOSFET Behavior: Types• Two types of MOS transistors

– N-channel MOSFETS (conducting carriers are electrons) • Built on p-type substrates so that reverse biased pn junction isolate the

conducting channel of nearby devices• Positive gate voltages create conducting channel

– P-channel MOSFETS (conducting carriers are holes)• Built on n-type substrates• Negative gate voltages create conducting channel

• Two modes– Depletion mode: channel is inverted or on, when the gate to

source voltage is zero– Enhancement mode: channel is not inverted or off, when the

gate to source voltage is zero


MOSFET Types


MOSFET Types

Type of MOSFETs

VT IDS

Enhancement-Mode, N-Channel

> 0 > 0

Depletion-Mode, N-Channel

< 0 > 0

Enhancement-Mode, P-Channel

< 0 < 0

Depletion-Mode, P-Channel

> 0 < 0


MOSFETGate controlled potential

barrier example• Gate voltage to induce

the channel is the threshold voltage

• Fermi level is flat with a potential barrier

• Positive applied to gate and negative charges form at surface

• Channel becomes less p-type, reducing the barrier essentially

• (For enhancement type)


MOSFETGate controlled variable resistor example

• Gate increases, more electrons means more conductive

• Drain current increases linearly with drain bias

• More drain current flows, more ohmic voltage drop along the channel

• Threshold is barely maintained near the drain end called pinch off

• Saturation region (not affect by drain bias)


MOSFET I-V Analysis

• Basic characteristics derived from– Gate structure corresponds to an ideal MOS capacitor

(no interface traps nor mobile charges)– Only drift current will be considered– Doping in the channel is uniform– Reverse leakage current is negligible– Transverse field in the x-direction in the channel is

much larger than the longitudinal field in the y direction (Gradual Channel approximation)


MOSFET I-V AnalysisFeatures of the I-V Characteristics: • Linear Region – VGS large, ID varies linearly with VDS

– Channel connects source and drain regions.– MOSFET acts like a gate-controlled resistor.– Inversion layer is continuous, no pinch-off.

• Triode Region – VDS becomes larger, saturating IDS.

– Channel resistance increases.

• Saturation Region –– VDS gets so large that VDS > VGS

– Leveling of IDS IDS,sat

– Pinch-off region exists at drain.– IDS not dependent on VDS

MOSFET IV Analysis


I-V Characteristics

Linear Region Onset of Saturation

VG>VT, VD=0 VG>VT, VD≤VG-VT

VDsat=VG-VT


I-V Characteristics

Channel Length Reduction

VG>VT, VD>VG-VT

Threshold VoltageWhen the surface potential, s, is at 2 B, the semiconductor

surface is at the onset of strong inversion and the gate voltage is at threshold voltage, VT.

The threshold voltage is the most important device parameter in any MOS system.

Gate voltage required to induce a conducting channel at the surface of the semiconductor

VT 2 BQ s

C ox 2 B

2 s q N A 2 B 1

2

C ox


I-V Characteristics• Inversion charge in the channel• ΔΨi is the channel potential with

respect to the source end• Z is the depth• b) no gate bias no drain bias in

equilibrium• c) equilibrium condition but under a

gate bias causing surface inversion• In nonequilbirum when both drain

and gate biasEFp remains at bulk Fermi level with EFn is lowered toward the drain contact


MOSFET I-V Analysis• Inversion charge is defined by

• Under ideal conditions the channel current at any y-position is given by

• Since current has to be continuous and constant throughout the channel, integration from 0 to L

Q n y( ) VG VFB i y( ) 2 B C ox 2 s qN A i y( ) 2 B

ID y( ) Z Qn y( ) y( )

IDZ

L0

L

yQn y( ) y( )

d

Where υy is the averagecarrier velocity

ID y( ) Z Qn y( ) y( )

IDZ

L0

L

yQn y( ) y( )

d


MOSFET• Under the assumption of constant mobility where

• Linear region equations

• Saturation region, pinch off point

ID ZL n Cox VG VFB 2 BVD

2

VD for Vd<<(VG-VT)

VT VFB 2 B2 s q NA 2 B

Cox

Pinch off pointDrain voltage and drain current

VDsat VG VFB 2 B K2

1 12 VG VFB

K2

K

sq NA

Cox

M 1K

2 B

IDsatZ

2 MLn Cox VG VT 2

I DZ

L n C ox V G V T

V D

2

V D


MOSFET• Non-linear region equations: between two

extremes

• Subthreshold region– Gate bias is below the threshold and semiconductor

surface is in weak inversion or depletion– Tells how sharply the current drops to zero with gate bias

I DZ

L n C ox VG VT

MVD

2

VD

I D

Z n

L2

q s N A

2 s

n i

N A

2

exp s S ln10( )kT

q

C ox C D

C ox


ExampleFor an n-channel MOSFET with a gate oxide thickness

of 10 nm, VT = 0.6V and Z=25μm, L=1μm. Calculate the drain current at VG=5V and VD=0.1V. Repeat for VG = 3V and VD = 5V. Discuss what happens for VD=7V. Assume an electron channel mobility of μn=200 cm2/V-s.

June 11, 2014 [email protected] sawyes/courses.html 1 ECSE-6230 Semiconductor Devices and Models I Lecture 14 Prof. Shayla Sawyer Bldg. CII,

Documents

mosfet gate

gate capacitor

gate insulator

gate biases

gate structure

control gate voltage

channel pchannel mosfets

channel threshold