July 14, 2010 San Francisco, California Marriott Hotel Assembly and Packaging.

July 14, 2010 San Francisco, California Marriott Hotel

Assembly and Assembly and PackagingPackaging


Assembly and PackagingAssembly and Packaging• 82 Members 22 present for Summer workshop• Focus of activities for 2010

– The only change to tables will be AP1: Difficult Challenges – Preparation for 2011 with expanded coverage for:

• Medical electronics, • 3D integration• Interposers • Automotive electronics • Optoelectronics • Printed electronics• Handling of thinned wafers and die• Embedded components• MEMS integration

– Rewrite of the System in Package paper

• Cross TWG coordination– Major collaborations include ERM, ERD, ESH, Interconnect, Design, Test

• Coordination with other Roadmaps– iNEMI– CTR/MPC– JISSO

• Difficult Challenges changing: 3D integration, new materials, more “Moore”


Assembly and Packaging Technical Working Group Assembly and Packaging Technical Working Group Summer Meeting 2010Summer Meeting 2010


Expanded Coverage of Emerging Requirements for 2011:

Medical ElectronicsMedical Electronics• Medical electronics Categories to be addressed:

– Portable medical electronics– Implantable medical electronics (Parkinson’s disease symptom control)

• Selected Issues for Medical electronics – Power requirements: energy scavenging; wireless radiated power; batteries– Safety issues (voltage, biocompatibility, power delivery)– FDA certification– Reliability requirements– Environmental issues– Connectivity (wireless)– Optical components (cameras)– Microfluidics– Implantable micro-robotics – Sensors– MEMS



3D Integration3D Integration

• Selected Issues for 3D Integration– Die stacking methods

• Homogeneous stacking• Heterogeneous stacking

– Test challenges for 3D• Test access• Test cost

– Through silicon Vias– Thermal management for 3D structured– Power integrity– 3D SiP– Bonding methods– Codesign and simulation



InterposersInterposers

• Selected Issues for Interposers:– Systems integration for 2D and 3D– Interposer features

• Redistribution wiring• Passive networks• Thermal management• Stress management

– Materials selection• Si• Ceramic• Glass• Organics

cross section of a fully assembled package with functional devices

IP

package

TSV



Automotive ElectronicsAutomotive Electronics• Automotive electronics Categories to be addressed:

– Internal combustion– Hybrid– All electric

• Selected Issues– Communications (including optical networks)– Thermal management

• In cabin• Hostile environments

– Safety– Sensors– Controls for improved efficiency– Cost

One side air cooling

Cooling on both sides

Liquid immersion cooling



Thin Wafer and Die HandlingThin Wafer and Die Handling

• Selected Issues for Thin Wafer and Die Handling– Testing: contactors with ohmic contact without damage– Holding mechanisms

• Electrostatic chucks • Bernouilli chuck • Temporary bonding (sacrificial layer) • Vacuum chucks (porous ceramic chucks)

– Dicing of thin wafer– Warpage



Embedded ComponentsEmbedded Components• Embedded Component Categories to be addressed:

– Active devices– Passive devices

• Selected Issues for Embedded Components– Performance enhancement due to reduced distance between die and passives– Incorporation of additional functionality (heat pipes; wave guides)– Keep out area around embedded components – Charge source close to the die for current surge– Reduced size by placement of passives under die– Placement accuracy for small thinned die– 3D alignment tolerance for assembly– Improved resistance to shock– Thermal management



MEMS IntegrationMEMS Integration• MEMS Integration Categories to be addressed:

– Sensors– Accelerometers– RF Switches, Oscillators, and filters – Microfluidics– Optical

• Selected Issues for MEMS Integration– Low stress interconnect between MEMS device and package cavities – Low cost, high reliability mechanical mounting– Electrical and environmental connections – low electrical parasitic interconnect– Low cost hermetic cavities – Stress management

Microfluidic pump


Difficult Challenges

Difficult Challenges ≥16 nm Summary of Issues

-Direct wire bond and bump to Cu or improved barrier systems bondable pads

- Dicing for ultra low k dielectric

-Bump and underfill technology to assure ultra low-κ/ air gap dielectric integrity

-Improved fracture toughness of dielectrics

-Interfacial adhesion

-Reliability of first level interconnect (increasing with decreasing contact pitch)

-Mechanisms to measure the critical properties (particularly for thin layers and interfaces)

-Redistribution processing for pad pitch below 50um

-Thermal management (for high power devices used in automotive and other areas)

-Wafer thinning and handling technologies

-TCE mismatch compensation for large die

Impact of BEOL including Cu/low κ on packaging

Wafer level Packaging


Difficult ChallengesDifficult Challenges ≥16 nm Summary of Issues

-Models for Reliability prediction

-Rapid turn around modeling and simulation

-Integrated analysis tools for transient thermal analysis and integrated thermal mechanical analysis

-Electrical (power disturbs, EMI, signal and power integrity associated with higher frequency/current and lower voltage switching)

-System level co-design(cm to nm) is needed now (including mixed signal and simulation).

-EDA for “native” area array is required to meet the Roadmap projections.

-Low cost embedded passives: R, L, C

-Embedded active devices

-Quality levels required not attainable on chip

-Die size for high C, low L integrated circuit matching die size

-Wafer level embedded components

- Wafer/die handling for thin die (must address die warpage)

-Reliability

-stress impact on device performance and assembly yield

-Interconnect thickness and bonding for die stacking

-Testability (ohmic contacts without damage)

Coordinated design tools and simulators to address chip, package, and substrate co-design

Embedded components

Thinned die packaging


Difficult Challenges

Difficult Challenges < 16 nm Summary of Issues

-Increased wireability at low cost

-Improved impedance control and lower dielectric loss to support higher frequency applications

-Improved planarity and low warpage at high process temperatures

-Low-moisture absorption

-Increased via density in substrate core

-Production techniques will require silicon-like production and process technologies

-Electromigration will become a more limiting factor.

-Thermal dissipation

Post CMOS switch devicesThe structures and materials employed will present serious challenges for packaging that will

need to be addressed during this Roadmap period. The specifics of the requirements and challenges are not known at this time.

High current density packages

Close gap between chip and substrate


Thank YouThank You

July 14, 2010 San Francisco, California Marriott Hotel Assembly and Packaging.

Documents

san francisco

d integration selected

packaging slide

thermal management slide

simulation slide

moore slide

handling selected issues

wafer warpage slide