Pimentel 1 P225/MAPLD 2004 Julio C. G. Pimentel ([email protected]) Julio C. G. Pimentel ([email protected]) Hoang Le-Huy ([email protected]) Hoang Le-Huy ([email protected]) Gilbert Sybille ([email protected]) Gilbert Sybille ([email protected]) LEEPCI - Laboratory of Electro-technology, LEEPCI - Laboratory of Electro-technology, Power Electronics and Power Electronics and Industrial Control Industrial Control An FPGA-Based Real Time Power An FPGA-Based Real Time Power System Simulator for Power System Simulator for Power Electronics Electronics
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Julio C. G. Pimentel (pimentel@ieee) Hoang Le-Huy ([email protected])
An FPGA-Based Real Time Power System Simulator for Power Electronics. Julio C. G. Pimentel ([email protected]) Hoang Le-Huy ([email protected]) Gilbert Sybille ([email protected]) LEEPCI - Laboratory of Electro-technology, Power Electronics and Industrial Control. Plan. Introduction - PowerPoint PPT Presentation
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LEEPCI - Laboratory of Electro-technology, Power Electronics and LEEPCI - Laboratory of Electro-technology, Power Electronics and Industrial ControlIndustrial Control
An FPGA-Based Real Time Power An FPGA-Based Real Time Power System Simulator for Power System Simulator for Power
ElectronicsElectronics
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Plan
Introduction Proposed Approach
Implementation Flow
Library of Components
Experimental Results
Conclusion
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Introduction
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Applications Power system stability analysis High frequency switched converters High frequency motion control
applications: Industrial machines Hybrid vehicles
Many more …
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Evolution of Real Time Power System Evolution of Real Time Power System SimulatorsSimulators
Continue Time ModelsContinue Time ModelsAmplifiers and passive Amplifiers and passive devicesdevicesReduced scale modelsReduced scale models
Discrete Time ModelsDiscrete Time ModelsParallel processorsParallel processorsMatrix RepresentationMatrix RepresentationInteractive Numeric Interactive Numeric Methods (algorithm)Methods (algorithm)
Proposed ApproachProposed Approach
Hardware EmulationHardware EmulationFPGAs + VHDLFPGAs + VHDLDSP or DSP or ProcessorProcessor
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Proposed Approach
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General ArchitectureGeneral Architecture
Decouple the electrical network in two parts:Decouple the electrical network in two parts:1.1. Linear part - RLC network is modelled as a Linear part - RLC network is modelled as a
matrix and processed by a microprocessormatrix and processed by a microprocessor2.2. Nonlinear part – nonlinear devices are Nonlinear part – nonlinear devices are
modelled as VHDL sub-circuits and processed modelled as VHDL sub-circuits and processed in the FPGAin the FPGA
Voltage and currents calculated by each part are Voltage and currents calculated by each part are exchanged at the end of each time stepexchanged at the end of each time step
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Data Flow Processing Model The sub-circuits are interconnected through their
input and output ports The inputs of a sub-circuit can only change at the
end of a time step The outputs of a sub-circuit only depends on its
inputs At the end of a time step the sub-circuit transfers
its calculated voltages and currents to the next sub-circuit
The sub-circuits are modelled in VHDL and implemented in a FPGA
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The synchronization ProblemThe synchronization Problem The sub-circuits I/O The sub-circuits I/O
signals can be: signals can be: – Control signals: CLK, Control signals: CLK,
– Voltages and Voltages and currents – fixed currents – fixed point integerpoint integer
– Logical signals: Logical signals: carry On/OFF carry On/OFF information (PWM information (PWM outputs, outputs,
RSTCLK
Voltages
ENSTCEOCReg
LogicalSignals
Sub
CircuitCurrentsVoltages
Currents
LogicalSignals
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The synchronization Problem (cnt’d)The synchronization Problem (cnt’d)
RSTCLK
EOC1
EOC2
EOCn
Master
State
Machine
The control signals are:The control signals are:– Generated by a master state Generated by a master state
machine that synchronizes the machine that synchronizes the whole systemwhole system
– Sent to all VHDL sub-circuitsSent to all VHDL sub-circuits The SM controls:The SM controls:
– Initialization - Stability Initialization - Stability depends a lot on the depends a lot on the initialization strategyinitialization strategy
– SequencingSequencing1.1. Send data to/from DACSend data to/from DAC2.2. Send data to/from uPSend data to/from uP3.3. Process dataProcess data
EN
STC_l
STC_nl
REG_l
REG_nl
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I(t-1)Vb(t-1)
Z-1
Z-1
Decoupling StrategyDecoupling Strategy
Decouple the linear and nonlinear parts by Decouple the linear and nonlinear parts by introducing a Voltage-Current pair introducing a Voltage-Current pair => reduce the size of the problem=> reduce the size of the problem
Problem: the value of I et Vb used in each Problem: the value of I et Vb used in each part are delayed by one time step part are delayed by one time step => system may become => system may become unstableunstable
The simulation of the nonlinear part takes much less than 1 us
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Implementation Flow
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Implementation FlowImplementation Flow
Translate PSBTo
VHDL
Elaboration
Synthesis
PlacementRouting
FPGA Programming
PSB/Matlab Schematic
Library of ComponentsFor DRTPSS
VendorLibrary
FPGA Design Flow
DRTPSSSimulator
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Library of parameter-driven components
Sources: DC, ramp, sinus, etc. 1and 3PWM modulators PI and PID controllers DQ-ABC and ABC-DQ converters Components (diode, MOST, Thyristor,
etc.) Digital filters and CORDIC D/A converters
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Sinusoidal sourceSinusoidal source
n, nc, VMax
Sin_1Ø
clkclock
outn
Freqn
en
0 10 20 30-1
-0.5
0
0.5
1
Résolution: 8 bits x Entrée: b'00001111Fréquence: 78.7 Hz
Time ( ms )
Vsi
n (V
)
0 100 200 300 400 500-80
-60
-40
-20
0
Résolution: 8 bits x Entrée: b'00001111Fréquence: 78.7 Hz
Frequency (Hz)
Vsi
n (d
Bv)
78.7 Hz
The sinusoidal source (example):The sinusoidal source (example):Can generate a sinus with 16-bit resolution (amplitude Can generate a sinus with 16-bit resolution (amplitude and phase)and phase)Approximation: series of Taylor (can also use a lookup Approximation: series of Taylor (can also use a lookup table):table):
Implemented using multiply-accumulate operationsImplemented using multiply-accumulate operationsDistortion < 1%Distortion < 1%
NOTE: 1) implemented on a Xilinx 2VP30 Virtex II PRO FPGA 2) results taken after placement and routing
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Conclusion Proposed a new approach to implement
DRTPSSs based on programmable hardware and HDL languages
The proposed simulator produces results comparable to those obtained with the PSB/Matlab from Mathworks
The initial results show that the technique has the potential to create a breakthrough in DRTPSS and set a new level of performance for these simulation tools