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Joint Meeting of ASP-DAC SC
ASP-DAC 2014 OC
Jan. 23, 2014
Singapore
Agenda1. Opening (Yasuura, SC Chair) 18:30-18:35
2. Introduction 18:35-18:40
3. Bylaws update 18:40-18:45
4. ASP-DAC 2014 report (Ha and Ishiura) 18:45-19:00
5. ASP-DAC 2015 report (Uchiyama and Chang) 19:00-19:10
6. ASP-DAC 2016 report (Martins) 19:10-19:15
7. SC reports (Yasuura) 19:15-19:20
8. Sister conference reports 19:20-19:30
DAC, ICCAD, and DATE
9. Other business issues 19:30-19:35
10. Adjurn 19:35
1
Bylaws updates
• CEDA joins ASP-DAC as a regular sponsor.• Section 2-4. Voting:
– One voting right from IEEE and one voting right from ACM.
• Section 6. Sponsorships:– The conference shall be sponsored by IEEE and ACM.
• IEEE consists of Circuits and Systems Society (IEEE CASS) and Council on Electronic Design Automation (IEEE CEDA).
• ACM consists of Special Interest Group on Design Automation (ACM SIGDA).
• The OC may add other local organizations, if necessary, under the following principle ...
• IEEE (CASS+CEDA) and ACM (SIGDA) always have the equal sponsorship ratio.
2
ASP-DAC 2014Report
Yong Lian and Yajun Ha
General Co-Chairs
Date: January 20-23, 2014
Place: Suntec, Singapore
ASP-DAC 2014
Date: 20 Jan (Monday)- 23 Jan (Thursday)
Venue: Suntec Convention & Exhibition Centre
Banquet: Flower Field Hall, Gardens by the Bay
History: 19th event of the ASP-DAC series ASP-DAC 2013 in Yokohama, Japan
ASP-DAC 2012 in Sydney, Australia
3
Session Organization
Regular Sessions 4 parallel breakouts 26 Sessions
Special Sessions Invited Talks 9 Sessions
University LSI Design Contest Short Talks & Poster Exhibition 1 Session
Tutorials (8 three-hour tutorials) 4 system-level and 4 physical-level tutorials Each participant can choose 1 system-level and 1
physical level tutorial to attend
Attendees in 2014as of 23 Jan, 2014
Total Number: 282
Strong attendance from academiaAcademia: 252 (including 53 students)
Industries: 30
International participation (26 countries/regions)
Singapore: 31
Overseas: 251ASP 156
NA 51
EU 41
Mid-East 3
4
Attendees as of Jan. 23, 2014
* Designers’ Forum Only(16) and Tutorial Only(N/A) are not included.** workshop attendees are just estimate
Attendees – Tutorial(2008~2014)Thanks to student group rate policy and new
change of format, tutorials come back to a reasonable level of attendees
Special rate for student group4 or more students as a group
Change of format3-hour, 4 parallel tutorials each half day
Options to select 2 out of 8 topics
2008 2009 2010 2011 2012 2013 2014
#Registrants 126 113 216 111 42 106 65
5
Delegate Summary
Country Number of Delegates
1 Japan 53
2 USA, Canada 50 (46, 4)
3 Hongkong/China 46
4 Europe 41
5 Singapore 31
6 Taiwan 27
7 Korea 16
8 India 5
9 Australia 6
10 Israel, Jordan, Malaysia, Kuwait, US Minor Islands
5 (1 each)
Total 282 (263 paid)
Tutorial Delegates
Tutorial Instructor
#PD1 Prof. Massoud Pedram 12
#PD2Prof. Tsung-Yi Ho and Prof. Krishnendu Chakrabarty
16
#PD3 Prof. Fadi Kurdahi and Prof. Ahmed Eltawil 12
#PD4 Prof. Sheldon Tan and Prof. Hai Wang 22
#SD1 Prof. Wolfgang Mueller and Prof. Gunar Schirner 10
#SD2 Mr. Alex Goryachev and Mr. Ronny Morad 15
#SD3 Prof. Rolf Drechsler and Dr. Rainer Findenig 8
#SD4 Prof. Zhiru Zhang and Prof. Deming Chen 17
6
Keynote Addresses“Title: All Programmable SOC FPGA for Networking and Computing in Big Data Infrastructure”Ivo Bolsens
Senior VP and CTO, Xilinx, USA
“Designing Analog Functions without Analog Transistors”Georges Gielen
Professor, Katholieke Universiteit Leuven, Belgium
“Beyond Charge-based Computing”Kaushik Roy
Professor, Purdue University, USA
I.
II.
III.
IV.
“The Art of Innovation - How Singapore Will Continue to Drive the Progress in Semiconductor Technologies”Ulf Schneider
Managing Director, Lantiq Asia PacificPresident, SSIA, Singapore
University LSI Design Contest
10 excellent designs are accepted out of 19 submissions from five countries/areas
Best Design Award A Dual-loop Injection-locked PLL with All-digital Background
Calibration System for On-chip Clock Generation
Wei Deng, Ahmed Musa, Teerachot Siriburanon,
Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
(Tokyo Institute of Technology, Japan)
Special Feature Award A Single-Inductor 8-Channel Output DC-DC Boost Converter with
Time-limited Power Distribution Control and Single Shared Hysteresis Comparator
Jungmoon Kim, Chulwoo Kim (Korea Univ., Republic of Korea)
7
University LSI Design Contest - Impression
Accepted papers quality are high with good oral presentation
Wide coverage on different area:5 RF+3 Analog+2 Digital
Submissions to this year’s ASP-DAC are from 5 countries/areas in Asia: Japan, Korea, China, Singapore, India.
UDC at ASP-DAC is established as a high-level design contest for Asian universities.
Financial Support
Singapore Tourist Board to support 10 conference and 11 tutorial registrations for students.
IEEE CEDA to support the lunch boxes for University Design Contest
8
Supporter’s exhibition
2 companies (Silicon Clound and Toshiba) joined
Exhibitors showed interesting exhibitions and demos
Many people visited their booths and exhibitions are successful
9
ASP-DAC 2014 Publication Report
Chong Kwen Siong Singapore
1
Outline
Publication Issues: with IEEE Authors’ Kit
Final Manuscripts and Copyrights
Final Program Proceedings
Prohibited Authors List Check
2
General Information
Advance Program
Materials We Have
10
3
GGeneral Information
The Publication Chair is required to work together with all parties, especially GC, TPC, Prof Taoka, Conference Secretariat and IEEE.
The Publication Chair is required to understand the general conference publication flow and to specify some deadlines (as advised/agreed by GC and TPC)
PPublication Issues: with IEEE No Items Remarks
1 Conference Publication Form (CPF)1 & Letter of Acquisition (LOA)
CPF submitted on 2 Sep CPF approved on 15 Sep LOA received on 20 Sep
Advice: Start earlier; decide the proceedings format
2 PDF eXpress Registration1
Registration submitted on 2 Sep Registration approved on 15 Sep
Advice: Should be available when Final Submission starts until the end of the conference; register earlier
3 E-Copyright Form Registration2,3,4
Registration submitted on 18 Sep Registration approved on 20 Sep
Advice: require IT setup; should be available when Final Submission starts
1 Initial submission guide (templates were largely based on the 2013 templates)
Initial submission guide/templates (in latex, doc and pdf) in May
2 Final submission guide (templates were largely based on the 2013 templates)
Final submission guide/templates (in latex, doc and pdf) available on 6 Sep Website information updated before 6 Sep All website information completed by 15 Oct
Advice: Make Conference Registration website, Paper Submission website, IEEE PDF eXpress check website, and e-Copyright Form website to be available as early as possible
3 Instructions for Authors/Presenters
Available in December (Arranged by Tulika; room arrangement/presentation info required)
5
PProhibited Authors List (PAL) Check
No Items Remarks
1 General Information
Checking completed using the list from the IEEE Intellectual Property Rights (IPR) Office (updated on Aug 2013)
Advice: register with IEEE IPR Office to get the PAL list
6
12
AAdvance Program No Items Remarks
1 General Information
First version available on 15 Oct Many revisions/updates thereafter
Advice: aim to be available before registration starts
2 Preliminary Technical Program
Update of Authors latest by 4 Oct – not critical Keynote information, Special Sessions, Regular papers, UDC papers, Tutorials – from TPC, tutorial chair, UDC chairs & Taoko’s system
Advice: Take special attention on Special Sessions as such information could be delayed by authors
3 Registration Information
Price/Discount/Deadline – from Registration chair/Conference co-chairs
4 Conference and Singapore Information
Hotel booking forms Banquet information Singapore transport/general info
7
FFinal Manuscript and Copyrights No Items Remarks
1 Manuscripts Only 2/3 manuscripts submitted by the first deadline (11 Nov) All draft/final papers (save one paper cancelled by TPC) submitted by the second deadline (18 Nov) Many requests for further update of manuscripts thereafter All manuscripts (no changes allowed) received on 3 Jan UDC/Regular papers: update of title/author list required approval from TPC/UDC chair Invited papers: update of the title/author list was allowed Update of database was strictly done by TPC Edit of the manuscripts was handled by Prof Taoka
Advice: Check inconsistencies between the database and manuscripts
2 Copyright forms
Hard-copy (signed) and e-copy forms were accepted/received Check types of copyright notices (e.g. U.S. Government, Crown Government and General)
Note: Many inconsistencies between the manuscripts/copyright forms (but were acceptable – informed by IEEE Copyright Office) 8
13
PProceedings No Items Remarks
1 General Information
USB format (recommended) Followed requirements mentioned in the IEEE LOA First version completed: 6 Jan USB copies: 330 pieces available on 6 Jan All data transferred into USBs: 9 Jan
2 Further Details
Using Taoka’s system Manuscripts all available (on 3 Jan) Messages/other information available (on 6 Jan)
Advice: The progress will much be depending on the available of the final manuscripts and award lists
3 Liaison with the IEEE
Deadline: 22 Feb 2014 No show papers/no presentation papers– need inputs from TPC
9
FFinal Program No Items Remarks
1 General Information
A4-size booklet; prefect binding; colour – cover; Black & white – other contents First version available: 6 Jan Sample available: 9 Jan Printing production: 10 Jan (printing); 16 Jan (available) Printing company: CMYK Digital Hub Pte Ltd suggested by Conference Secretariat Number of copy: 280
2 Further details
Using Taoka’s system General messages received by early Dec; but all were finalized on 6 Jan PDF version could be uploaded into the web after the conference
Advice: The progress will much depending on the available of the final manuscripts, award lists and exhibitors’ information 10
1 System-Level Modeling and Simulation/Verification 21 242 System-Level Synthesis and Optimization 23 273 System-Level Memory/Communication Design and Networks on Chip 28 364 Embedded and Real-Time Systems 41 365 High-Level/Behavioral/Logic Synthesis and Optimization 21 266 Validation and Verification for Behavioral/Logic Design 15 137a Physical Design (Placement) 7 127b Physical Design (Routing) 13 168 Timing, Power, Thermal Analysis and Optimization 42 279 Signal/Power Integrity, Interconnect/Device/Circuit Modeling and Simulation 10 1610 Design for Manufacturability/Yield and Statistical Design 37 2511 Test and Design for Testability 14 1512 Analog, RF and Mixed Signal Design and CAD 16 1613a EDA and Design Methodologies for Emerging Technologies 44 2613b Emerging Applications 32 28
total 343
after “reshuffling”
19
TPC memberssubcommittee members
1 System-Level Modeling and Simulation/Verification 72 System-Level Synthesis and Optimization 83 System-Level Memory/Communication Design and Networks on Chip 114 Embedded and Real-Time Systems 115 High-Level/Behavioral/Logic Synthesis and Optimization 76 Validation and Verification for Behavioral/Logic Design 47a Physical Design (Placement) 57b Physical Design (Routing) 58 Timing, Power, Thermal Analysis and Optimization 89 Signal/Power Integrity, Interconnect/Device/Circuit Modeling and Simulation 610 Design for Manufacturability/Yield and Statistical Design 711 Test and Design for Testability 612 Analog, RF and Mixed Signal Design and CAD 513a EDA and Design Methodologies for Emerging Technologies 713b Emerging Applications 7
total 104
TPC members
country membersJapan 23U. S. A. 22China 17Taiwan 16Korea 8Germany 5Hong Kong 4Singapore 2Australia, Finland, France, Sweden, Switzerland 1×5
India, Australia 1×2Canada 1
total 104
20
TPC meeting
■Monday, September 2, 2013■Kyoto Research Park, Japan
9:00-9:30 Opening9:30-15:00
(12:00-13:00)
- Paper selection- Session organization- Best Paper Award nominationLunch
15:30-17:30 EDA Workshop19:00- Dinner
TPC meeting
■90/104 members attended physically1 attended via Skype
■Paper selection was very smoothMost of the subcommittees finished their
work by 3:00pm
23 presentations at EDA Workshop
21
TPC meeting dinner
19:00-21:00Sanjaku-Sanzun-Bashi(10F, Isetan, JR Kyoto Station)
Paper selection
Submitted 343↓ paper selection
Accepted 108 (31.5%)
22
Accepted papers
country #accU.S.A. 35 32.4%China 18 16.7%Germany 8 7.4%Japan 8 7.4%Taiwan 8 7.4%Hong Kong 4 3.7%India 4 3.7%Singapore 4 3.7%
■1 paper (TCAD)→ REJECTEDWe should explicitly prohibit journal vs
ASP-DAC double/parallel submission in CFP
24
Notification
■Schedule was carefully planned
Sept 2 TPC MeetingSept 3 List of accepted papers posted
on webSept 11 Notification with commentsSept 13 DATE 2014 submission deadline
Sept 9
Notification was done two days ahead of the schedule
Special sessions
■Proposal basis■Received 11 proposals9 were adopted1 was rejected1 was accepted as a tutorial
25
Program organization
0pening
Keynote
S1A1
UDC B1 C1
lunch
S2 A2 B2 C2
S3 A3 B3 C3
Keynote
S4 A4 B4 C5
lunch
S5 A5 B5 C5
S6 A6 B6 C6
Banquet Keynote
Keynote
S7 A7 B7 C7
lunch
S8 A8 B8 C8
S9 A9 B9 C9
Day 1 (Jan 20) Day 2 (Jan 21) Day 3 (Jan 22)
5 papers
Special sessions
(1S) “Normally-Off Computing: Towards Zero Stand-by Power Management”Hiroshi Nakamura (Univ. of Tokyo, Japan)
(2S) “EDA for Energy”Fadi Kurdahi (UC Irvine, U.S.A.), Sani Nassif (IBM, U.S.A.), Mohammad Al Faruque (UC Irvine, U.S.A.)
(3S) “Neuron Inspired Computing using Nanotechnology”Kevin Cao, Sarma Vrudhula (Arizona State Univ., U.S.A.)
(4S) “Design Automation Methods for Highly-Complex Multimedia Systems”Sri Parameswaran (Univ. of New South Wales, Australia)
(5S) “Billion Chips of Trillion Transistors”Chen-Yong Cher (IBM, U.S.A.)
26
Special sessions (cont’d)
(6S) “Overcoming Major Silicon Bottlenecks: Variability, Reliability, Validation, and Debug”Subhasish Mitra (Stanford Univ., U.S.A.)
(7S) “Brain Like Computing: Modelling, Technology, and Architecture”Ahmed Hemani (KTH, Sweden)
(8S) “Design Flow for Integrated Circuits using Magnetic Tunnel Junction Switched by Spin Orbit Torque”Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)
(9S) “The Role of Photons in Harming or Increasing Security”Francesco Regazzoni (Univ. of Lugano, Switzerland), EdorardoCharbon (Delft Univ. of Tech., Netherlands)
Best Paper Award
13 candidates were nominated at TPC meeting Through 2 rounds of reviews by Award Selection
Committee, one winner has been selectedAward Selection Committee
Yoshi WadanabePaolo IenneChung-Ta KingJian-Jia ChenDeming ChenMiroslav VelevHung-Ming ChenWen-Hao Liu
Masanori HashimotoLuca DanielHai ZhouTomokazu YonedaSheldon TanIk Joon Chang/Yongpan LiuJongsun Park
change afterthe 1st review
27
Best Paper Award
(2B-1) Flexible Packed Stencil Design with Multiple Shaping Apertures for E-Beam Lithography
Chris Chu (Iowa State Univ., U.S.A.)
Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
10-Year Retrospective Most Influential Paper Award Sponsored by IEEE CEDA 4 most cited papers from ASP-DAC 2004 were
nominated as candidates One winner has been selectedAward Selection Committee (same as Best Paper Award)
Yoshi WadanabePaolo IenneChung-Ta KingJian-Jia ChenDeming ChenMiroslav VelevHung-Ming ChenWen-Hao Liu
Masanori HashimotoLuca DanielHai ZhouTomokazu YonedaSheldon TanIk Joon Chang/Yongpan LiuJongsun Park
CoIs
CoIs
28
Candidates(1D-1) “Register Binding and Port Assignment for Multiplexer
Optimization”Deming Chen, Jason Cong
(1E-1) “TranGen: A SAT-Based ATPG for Path-Oriented Transition Faults”
Kai Yang, Kwang-Ting Cheng, Li-C. Wang(2E-2) “Design Diagnosis Using Boolean Satisfiability”
Alexander Smith, Andreas Veneris, Anastasios Viglas(3D-1) “Efficient Translation of Boolean Formulas to CNF in
Formal Verification of Microprocessors”Miroslav N. Velev
10-Year Retrospective Most Influential Paper Award
(2E-2) Design Diagnosis Using Boolean Satisfiability
Alexander Smith, Andreas Veneris, Anastasios Viglas
(Univ. of Toronto, Canada)
10-Year Retrospective Most Influential Paper Award
29
Subcommittee chairs’ meeting
“Topics of ASP-DAC are conservative...”→ Newly held “subcommittee chairs’
meeting” (Jan 22) to discuss: Next year’s CFP Various TPC policies
No show/no author presentation
<1st day and 2nd day>■No show: 0■No author presentation: 1
30
TPC Summary
There were minor troubles, of course, but almost everything has been smooth and efficient this year
Thank you!
31
ASP-DAC 2015 OC Report
Kunio Uchiyama Hitachi Ltd.
ASP-DAC SC-OC meeting 2014/1/23
Chairs • Chairs – General Chair: Kunio Uchiyama(Hitachi Ltd., Japan) – TPC Chair: Naehyuck Chang (Seoul National Univ.,
Korea) – Secretary: M. Yamaoka (Hitachi) , K. Shimamura
(Hitachi), Y. Uematsu (Hitachi), Y. Sakurai (Hitachi), K. Seto (Tokyo City U.), N. Togawa (Waseda U.)
– Secretariat: JESA
http://www.aspdac.com/aspdac2015/
32
Date and Place • Date
– January 19(Mon) – 22(Thu), 2015 • Place
– Makuhari Messe, Chiba, Japan (http://www.m-messe.co.jp/en/index.html)
From Tokyo 23-29 min. (train) From Narita 30min. (bus) From Haneda 40min. (bus)
Conference
Exhibition
Park
Stadium Disney Land
Makuhari Messe
33
Organizing Committee
• Tutorial: – M. Ikeda(U.Tokyo), T. Isshiki(Tokyo I. T.)
• Design Contest: – H. Ito(Tokyo I. T.), N. Miura (Kobe U.)
• Designers’ Forum: – Y. Masubuchi(Toshiba), K. Inoue(Kyushu U.)
• Finance: – T. Matsumoto(U.Tokyo), A. Takahashi(Tokyo I. T.)
• Publication: – S. Nagayama(Hiroshima City U.), M. Imai(Hirosaki U.)
• Publicity: – H. Tomiyama(Ritsumeikan U.), T. Matsunaga (Kyushu S.
U.), N. Kojima(Toshiba) • Web publicity: Y. Hara (Nara IST), T. Ishihara(Kyoto U.) • Promotion: Y. Nakamura(NEC)
1 Normally-Off Computing : Towards Zero Stand-by Power Management Hiroshi Nakamura (Univ. of Tokyo, Japan) 4
2 EDA for Energy Fadi Kurdahi (UC Irvine, USA) 3
3 Neuron Inspired Computing using Nanotechology Kevin Cao, Sarma Vrudhula (Arizona State Univ., USA)4
4 HIGH‐LEVEL SPECIFICATIONS TO COPE WITH DESIGN COMPLEXITY Wolfgang Mueller (Univ.of Paderborn/C‐LAB, Germany) 4
5 A bug's life: prediction, creation, detection and extinction Tali Rabetti (IBM research lab, Israel) 4
6 Design Automation Methods for Highly-Complex Multimedia Systems Sri Parameswaran (Univ. of New South Wales, Australia) 4
7 Design Flow for Integrated Circuits using Magnetic Tunnel Junction Switched by Spin Orbit Torque
Mehdi Tahoori (Karlsruhe Institute of Technology, Germany)4
8 The role of photons in harming or increasing security Francesco Regazzoni, AlaRI (Univ. of Lugano, Switzerland)3
9 Bain Like Computing: Modelling, Technology and Architecture Ahmed Hemani (School of ICT, KTH, Kista, Sweden)4
10 Overcoming Major Silicon Bottlenecks: Variability, Reliability,Validation and Debug
Subhasish Mitra (Stanford Univ., USA)3
11 Billion chips of trillion transistors Chen-Yong Cher (IBM TJ Watson Research Center, USA)3
35
Special Session(Accepted)
Session ID Title Organizer Talks
1SNormally-Off Computing : Towards Zero Stand-by Power Management
Hiroshi Nakamura (Univ. of Tokyo, Japan) 4
2S EDA for Energy Fadi Kurdahi (UC Irvine, USA) 3
3S Neuron Inspired Computing using NanotechologyKevin Cao, Sarma Vrudhula (Arizona State Univ., USA)
3
4SDesign Automation Methods for Highly-Complex Multimedia Systems
Sri Parameswaran (Univ. of New South Wales, Australia)
4
5S Billion chips of trillion transistorsChen-Yong Cher (IBM TJ Watson Research Center, USA)
3
6SOvercoming Major Silicon Bottlenecks: Variability, Reliability,
Validation and DebugSubhasish Mitra (Stanford Univ., USA) 3
7S Bain Like Computing: Modelling, Technology and Architecture Ahmed Hemani (School of ICT, KTH, Kista, Sweden) 4
8SDesign Flow for Integrated Circuits using Magnetic Tunnel Junction Switched by Spin Orbit Torque
Mehdi Tahoori (Karlsruhe Institute of Technology, Germany)
4
9S The role of photons in harming or increasing securityFrancesco Regazzoni, AlaRI (Univ. of Lugano, Switzerland)
3
2015 CFP
•Purpose•Balance the submissions and trend•Match with sister conferences (DAC)•Remove ambiguity to avoid excessive paper migration•Ensure quality review removing diversity in a subcommittee•Promote popular and timely topics
36
2015 CFP
Number of reviewed papers in ASP-DAC 2014 and 2013
2015 CFP
TPC size of the ASP-DAC 2015: 100 TPC size of the ASP-DAC 2015: 104
37
2015 CFP
Topic ID Topic (subcommittee) Name TPC Size
1 System-Level Modeling, Simulation and Verification 7
2 Interconnect/Device/Circuit/Gate Modeling, Simulation and Verification 7
3 System-Level Architecture and Design Methodologies 8
4 Power and Thermal Modeling, Simulation and Optimization/Management 7
5 On-chip and System-level Communication Design, I/O, Networks on Chip, and Memory Systems 7
6 Embedded Systems 10
7 Logic/Behavioral/High-Level Synthesis and Optimization 7
8 Physical Design 8
9 Timing and Signal/Power Integrity Analysis and Verification 8
10 Design for Manufacturability, Yield and Statistical Design 7
11 Test and Design for Testability 4
12 Analog, RF and Mixed Signal Design and CAD 5
13 CAD and Design Methodologies for Emerging Technologies 7
14 CAD for Emerging Applications and Cyber-Physical Systems 8
2015 CFP
• Important deadlines• Deadline for submission: 5 PM JST (UTC+9) July 11 (Friday), 2014• Notification of acceptance: Sep. 15 (Monday), 2014• Deadline for final version: 5 PM JST (UTC+9) Nov. 10 (Monday), 2014
38
Track Chairs’ COI
• Motivation• General understanding on the volunteer positions
• Pure service• No right to abuse the power for their interest
• Getting rid of perception and incidences• Paper assignment• Paper selection• Best paper nomination
• Sister and neighborhood conferences• Track chairs are not allowed to submit the papers in their tracks• Track chairs’ papers are separately handled
• Suggestion on the best paper nomination• Track chairs’ papers are not allowed to be nominated as a best paper
candidate
10-Year Award
• Motivation• Traditional EDA topics have leveraged and positioned the reputation
of major EDA conferences• Higher number of citations• Well formulated problems• Less chances to have harsh reviews• Free from out-of-scope issues
• High-level and new topics are the driving forces of EDA conferences as of today
• Suggestion on the 10-year retrospective best paper nomination• Plan 1: Two awards per year: from-end and back-end• Plan 2: Looking at two-year window horizon, and award front-end
and back-end every other year
39
Other Businesses
• Any other business?
40
Asia and South Pacific Design Automation Conference (ASP-DAC) 2016
hosted by
University of Macau & IEEE Macau Joint-Chapter CAS/COM
inMacao, China
ASP-DAC 2016
• General Chair– Rui Martins (University of
Macau)
• Venue– Macao
• University of Macau Hengqin New Campus (tentative - includes Hotel with 100 rooms),
or alternative
• Hotel nearby - Galaxy, Venetian or Sheraton
• Date – 2016 February 1(Mon) - 4(Thu) (tentative)
41
New Campus of University of Macau
•Covering an area of 1.0926km2, accommodate 10000 students
From Airport 5-10 min. (taxi)From Ferry Terminal 20min. (taxi)Via Hong Kong 1 hour (ferry)
Venetian Macao
Airport
Conference Venue
University of Macau Hengqin Campus
City of Dreams
Taipa Houses-MuseumGalaxy Macau
42
Thank You,Looking forward to seeing you in Macao!!!
43
Reports from SC Chair
Jan. 23, 2014
Hiroto Yasuura
SC Chair of ASP-DAC
Discussion Items
• Assignment of GC of 2017
• TPC chair candidate for 2017
• Call for proposal of 2018
• Schedule
• Member updates
44
ASP-DAC 2017 venue
• Japan – Keep Japan Outside-Japan rule for several years
– Final Decisions are made at SC meeting in ASP-DAC2014 (Singapore)
• ASP-DAC Bylaw (Section 5. Location of the Conference)The location of the conference shall alternate between Japan and other countries or areas in the Asia South Pacific Region. The location shall be decided by the SC. The SC Chair may call for proposals from the hosting country or area, if necessary. The hosting country or area shall be decided at least three years before the conference.
Exhibit Hours: Monday, June 2: 9:00am-6:00pm Tuesday, June 3: 9:00am-6:00pm Wednesday, June 4: 9:00am-6:00pm
Conference Schedule Sunday, June 1 • Workshops Monday, June 2 • New! General Session/Keynote • Tutorials • IP Track Session • Afternoon Keynote • Evening Reception
52
Thursday, June 5 • Morning Keynote • Best Paper Awards • Security Track • Technical Sessions • Panels • Special Sessions • Training Day • Closing Reception
◆ Technical Program Co-Chairs ◆ Charles Alpert, Cadence Design Systems, Inc. ◆ Sharon Hu, Univ. of Notre Dame
◆ Automotive Track Co-Chairs ◆ Tony Cooprider, Ford Motor Company ◆ Samarjit Chakraborty, Technical Univ. of
Munich
53
Confirmed Keynotes
Monday, June 2 • 9:00-10:00am • Sir Hossein Yassaie,
CEO and President - Imagination Technologies
Monday, June 2 • 3:00-4:00pm • Dr. Cliff Hou, Vice President,
Research and Development - TSMC • Talk: Industry Opportunities in
the Sub-10nm Era
Tuesday, June 3 • 9:00-10:00am • Jim Tung, MathWorks Fellow - MathWorks, Inc. • James Buczkowski, Henry Ford Technical Fellow
- Ford Motor Company • Dual Keynote: Automating the Automobile
Creating Verticals at DAC
◆ Motivation: Need to grow design automation in the embedded system and software space ■ Already >35% of the technical program is in embedded ■ Not seeing traction among attendees and on the exhibit
floor
◆ Create Vertical track to emphasize specific market verticals and integration. Focus in 2014 is on: ■ Automotive (2 days) ■ Security (1 day) ■ IP (1 day) ■ Mobile (1 day)
54
Automotive Track
◆ dddThe Automotive Track has been created this year to bring together researchers and practitioners from the automotive domain with their counterparts from the embedded systems & software (ESS) domains. This also includes those from the electronic design automation (EDA) space.
Automotive Track Chair: Samarjit Chakraborty Technical University of Munich Anthony Cooprider Ford Motor Company
Track # of Submissions
AUTO1. Automotive 44
Automotive TPC
◆ dddAutomotive Track Technical Program Committee: Adir Allon IBM Research - Haifa Butts Ken Toyota Motor Corporation Di Natale Marco Scuola Superiore Sant'Anna Dixit Manoj MathWorks, Inc. Ecker Wolfgang Infineon Technologies AG Eles Petru Linköping University Grunler Christian Daimler AG Hamann Arne Robert Bosch GmbH Lukasiewycz Martin TUM CREATE Ltd. Nuckolls Ed Freescale Semiconductor, Inc. Paparo Mario STMicroelectronics Ramesh S. General Motors Company Ravindran Kaushik Natl. Instruments Corporation Samii Soheil General Motors Company Stechele Walter Technical University of Munich Stormer Christoph ETAS Group Zeng Haibo Mcgill University
55
Paper Submission History
YEAR ABSTRACT SUBMISSION APPROVED FOR REVIEW
2011 959 741
2013 913 743
2014 1060 788
2014 Paper Submission By Committee
SUBCOMMITTEE # OF PAPERSEDA1. System-on-chip design and HW/SW codesign 38
EDA2. On-Chip Communication and Networks-on-Chip 34
EDA3. Cross-Layer Power Analysis and Low-Power Design 64
EDA4. Low-Power Devices and Circuits 26
EDA5. Verification 47
EDA6. High-Level Synthesis, Logic Synthesis, and FPGAs 47
EDA7. Analog Design and Simulation 40
EDA8. Physical Design and Design Closure 50
EDA9. Physical Verification, Lithography and DFM 30
EDA10. Analysis of Digital Design 38
EDA11. Testing 16
EDA12. New and Emerging Design Technologies 53
56
2014 Paper Submission By Committee
SUBCOMMITTEE # OF PAPERSESS1. Embedded Software 58
▪ TPC: 17 tracks, 106 members, meeting in Austin, TX ▪ Registration: 348 (375 in 2012, 350 in 2011)
▪ Keynotes ▪ T. Sterling: Future of computing through brain-inspired architectures ▪ L. Liebmann: Escalating design impact of resolution-challenged lithography ▪ L. Scheffer: Networks of NMOS and neurons