S .1 Embedded and Real Time Systems (April-2012, Set-1) JNTU-Kakinada( JNTU-Kakinada ) B.Tech. IV-Year II-Sem. Code No: L0421/R07 IV B.Tech. II Semester Regular/Supplementary Examinations April - 2012 EMBEDDED AND REAL TIME SYSTEMS (Common to Electronics and Communication Engineering & Electronics and Instrumentation Engineering) Time: 3 Hours Max. Marks: 80 Answer any FIVE Questions AllQuestions carry equalmarks - - - 1. (a) Ex pl ain th e compo nents of emb ed de d s ys tem hard wa re . (Unit-I, Topic No. 1.1) (b) Expla in with an exa mple h ow to op timize custo m sing le purp ose pr ocessors. [8+8] (Unit-I, Topic No. 1.2) 2 . (a ) Explai n the dev elo pme nt env ironme nt of genera l purpose processor s u sed in an embedd ed sys tem des ign wit h an example.(Unit-II, Topi c No. 2.2) (b) Explai n the import ance of the following pr ocess ors in embed ded sy stems , ( i ) Di gi tal si gnal pro ce ssor (i i ) ASSP . [8+8](Unit-II, Topic N o. 2.3) 3 . (a) De sc ri be program state ma ch in e mod el wi th re le vant exampl e. (Unit-III, Topic No. 3.1) (b) Dis cus s a bout c onc urre nt proces ses. [8+8] (Unit-III, Topic No. 3.4) 4 . (a ) What i s meant by communicat ion in terf ac e? Explain t he need f or communi cati on i nt er face s. (Unit-IV, Topic No. 4.1) (b) Illus trate with suit able e xample how to uti lize et herne t as a communic ation in terface. [8+8] (Unit-IV, Topic No. 4.3) 5 . (a) Expl ai n t he us e of s emapho re s f or the critica l s ec tions of a Tas k. (Unit-V, Topic No. 5.2) (b ) Wr ite notes on tas k a nd tas k s tates. [8+8] (Unit-V, Topic No. 5.1) 6. (a) Wh at is mea nt b y pr iori ty i nver si on p roblem? Ex pl ain it wit h an exampl e. (Unit-VII, Topic No. 7.1) (b) What i s mean t by pipe ? How do es a pi pe diff er from a queue ? Expla in with a n examp le. [8+8] (Unit-VI, Topic No. 6.4) 7 . (a) Ex pl ain i n b rief t he di ffe ren t Timer Func ti ons . Unit-VII, Topic No. 7.1) (b) Wri tes not es o n Windows C E. [8+8] (Unit-III, Topic No. 3.4) 8 . Explai n t he fol lowing rel ate d t o e mbe dde d s ystem des ign tec hnology , (a) Be ha vi or al Synthesis. (Unit-VIII, Topic No. 8.1) (b ) Har dwa re/ Sof tware co- ver ifi cat ion. [8+8] (Unit-VIII, Topic No. 8.2) Set-1 Solutions
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S.6 Embedded and Real Time Systems (April-2012, Set-1) JNTU-Kakinada
B.Tech. IV-Year II-Sem. ( JNTU-Kakinada )
Need for Communication Interface
The need for communication interface are given as,
1. In order to share the data in a network, a communication interface is required.
2. In order to establish communication between two embedded systems a standard communication interface is necessary.
3. The station receiving the data will study and present it through a GUI (Graphical User Interface) with the help of a
communication interface.
4. For weather forecast, the system can be enabled by internet by using TCP/IP protocol and HTTP server.
5. If two mobiles want to share information bluetooth can be used, which is a popular communication interface. Even
for mobile to laptop communication blue tooth can be used.
6. Communication interfaces even support software upgradation.
(b) Illustrate with suitable example how to utilize ethernet as a communication interface.
Answer : April-12, Set-1, Q4(b) M[8]
Ethernet is a standard communication interface used to connect devices on a LAN. It is also known as IEEE 802.3
standard. A wired ethernet LAN connecting multiple embedded systems on one end and a computer on other end can be a
suitable example to show how an ethernet could be used as communication interface.
Computer
Ethernet
EM4EM3EM2EM1
Embedded systems
Computer
Ethernet
EM4EM3EM2EM1
Embedded systems
Figure (i) : Ethernet as a Communication Interface
The above figure contains multiple embedded systems which are monitored using a computer. Ethernet is a standard
protocol to connect a computer network on a LAN, printers, faxes and etc.
For remaining answer refer Unit-IV, Q10 (From 2nd para till end of the answer).
Q5. (a) Explain the use of semaphores for the critical sections of a Task.
Answer : April-12, Set-1, Q5(a) M[8]
The condition or a situation in RTOS when a single or multiple tasks try to access a system resource which is alreadyheld by a task, is called critical section. In such scenarios, binary semaphores- a type of semaphore, is used to share system
resources among multiple tasks. The binary semaphores acts like locks over critical sections. When a binary semaphore is
locked, it indicates that a task is in critical section and is currently running the resource. Similarly, when a binary semaphore
is unlocked it indicates that a resource is currently idle and can be accessed by a task.
When a binary semaphore is locked, no task can enter the system resource untill the task exits the corresponding
critical section and unlocks the binary semaphore. Thus, execution and synchronization of multiple tasks in critical section
S.8 Embedded and Real Time Systems (April-2012, Set-1) JNTU-Kakinada
B.Tech. IV-Year II-Sem. ( JNTU-Kakinada )
Q7. (a) Explain in brief the different Timer Functions.
Answer : April-12, Set-1, Q7(a) M[8]
For answer refer Unit-VII, Q2.
(b) Writes notes on Windows CE.
Answer : April-12, Set-1, Q7(b) M[8]
For answer refer Unit-III, Q12.
Q8. Explain the following related to embedded system design technology.
(a) Behavioral Synthesis.
Answer : April-12, Set-1, Q8(a) M[8]
Behavioral Synthesis
Behavioral synthesis is a high-level synthesis technique which optimizes a sequential program and converts it into
a single-purpose processor. Behavioral synthesis, apart from performing allocation and binding for a certain sequential
program it also needs to operate in scheduling the program. Scheduling is a process of designing states for every function
in a sequential program.
As far as allocation and binding are concerned, every variable has a storage unit, for every operation there is a
functional unit and for every data transfer there is a connection unit. To carry out these techniques advanced methods are
used in order to optimize a circuit.
(b) Hardware/Software co-verification.
Answer : April-12, Set-1, Q8(b) M[8]
Design verification is a process of ensuring whether a formulated design is correct/complete or not. A design is said
to be correct when all the design specifications are implemented accurately. While, a design is said to be complete when it
describes all the outputs in advance for all the relevant inputs.
There are two methods of hardware/software verification. They are ‘formal verification’ and ‘simulation’. In formal
verification, a design is verified on the basis that it approves or disapproves certain properties correctly or not. It is a very
complex process and is used only in verifying small designs or some specific design properties. On the other hand,
simulation is a very simple, easy and widely used verification process. In this method a software model is created and is runon the computer against the potential test cases. If the outputs of the test cases match the expected outputs, then the
corresponding design model is said to be verified else it is not. Simulation has a disadvantage, that it cannot verify design
model against all the possible inputs. Thus, designers using simulation method test the design model against a small set of
inputs, which typically include all kinds of real-time input along with known boundary conditions.
Physically implementing a design and then testing it is not feasible due to the grave consequences that may arise.
Hence, simulation of a design is done before implementing it in real-time. Simulation provides several advantages which
makes it worth, like facilitating a designer to debug and test a design through providing controllability and observeability.
A designer can start and stop simulation of a design at any desired time and further more design can be tested over any
values or even though small intervals.
IC
FPGA
HE
Throughput model
ISS
CAS
RT-level HDC simulation
GT-level HDC simulation× 10,000,000
× 10,00,000
× 1,00,000
× 10,000
× 1,000
× 100
× 10
1 1 hour
1 day
4 days
1.4 months
1.2 years
12 years
> 1 life time
1 millenium
IC
FPGA
HE
Throughput model
ISS
CAS
RT-level HDC simulation
GT-level HDC simulation× 10,000,000
× 10,00,000
× 1,00,000
× 10,000
× 1,000
× 100
× 10
1 1 hour
1 day
4 days
1.4 months
1.2 years
12 years
> 1 life time
1 millenium
Figure (1): Comparison of Relative Speeds of Different Types of Simulation/Emulation and Real-time Execution