JIT FPGA Ideas Contributing Ph.D. Students Roman Lysecky (Ph.D. 2005, now Asst. Prof. at Univ. of Arizona Greg Stitt (Ph.D. 2007, now Asst. Prof. at Univ. of Florida, Gainesville Scotty Sirowy (current) David Sheldon (current) Chen Huang (current) This research was supported in part by the National Science Foundation, the Semiconductor Research Corporation, Intel, Freescale, IBM, and Xilinx Frank Vahid Dept. of CS&E University of California, Riverside Associate Director, Center for Embedded Computer Systems, UC Irvine
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JIT FPGA Ideas Contributing Ph.D. Students Roman Lysecky (Ph.D. 2005, now Asst. Prof. at Univ. of Arizona Greg Stitt (Ph.D. 2007, now Asst. Prof. at Univ.
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JIT FPGA Ideas
Contributing Ph.D. StudentsRoman Lysecky (Ph.D. 2005, now Asst. Prof. at
Univ. of ArizonaGreg Stitt (Ph.D. 2007, now Asst. Prof. at Univ. of
Florida, GainesvilleScotty Sirowy (current)
David Sheldon (current)Chen Huang (current)
This research was supported in part by the National Science Foundation, the Semiconductor Research
Corporation, Intel, Freescale, IBM, and Xilinx
Frank VahidDept. of CS&E
University of California, Riverside
Associate Director, Center for Embedded Computer Systems, UC Irvine
2Frank Vahid, UC Riverside
SystemC Bytecode for FPGAs
Demo
3Frank Vahid, UC Riverside
FPGA Common Presence
Caches, FPUs, GPUs, FPGAs
App developers may expect FPGA presence
How create/distribute apps that make good use of FPGA if present?
µP
Binary
Cache FPU
FPGAµP
GPU
4Frank Vahid, UC Riverside
“Spatial” Algorithms for FPGAs Example – Count patterns
Sequential algorithm Hash table 10s cycles per pattern
int patterns[1,000]; int counts[1,000];while (1) { WaitForPattern(); CurrPattern = X; hash = HashFct(CurrPattern); item = Find(patterns, CurrPattern, hash); if (item) { counts[item]++; } }
count
Level 1logic pattern
logicLevel 2
Level mlogic
CurrPattern
countpattern
countpattern
.
.
.
bus
Spatial algorithm Pipelined stages Essence is the connectivity
of components, not the sequencing of instructions
5Frank Vahid, UC Riverside
Bytecode Modern portability approach
Java, C#
PentiumAtomOpteron
bytecode
Compiler
VM VM VM
Virtual Machine (VM): Program that executes bytecode
May JIT compile to native architecture
6Frank Vahid, UC Riverside
SystemC Bytecode?
PentiumFPGA
SystemC bytecode
Compiler
VM VM
SystemC
Opteron+
FPGA
VM
7Frank Vahid, UC Riverside
UCR SystemC Bytecode and Compiler
class EDGE_DETECTOR : public sc_module {//signal declarations…EDGE_DETECTOR() { SC_method(mainComp); sensitive << dataReady;
SC_method(getPixel); sensitive << clock.pos();
void getPixel(){ … dataReady.write(1);}
void mainComp(){ int i, j; for(i = 0; i < 3; i++){ for(j = 0; j < 3; j++){ sumX = sumX + mem.read()*GX[i][j] } } … edge.write(sumX + sumY)}