JAZiO Incorporated 1 Change No-Change Concept. JAZiO Incorporated 2 Change /No Change Concept Comp A Data In VTR Data In Comp A No Change This band is.

JAZiO™ Incorporated1

Change No-Change

Concept


Change /No Change ConceptComp A

Data In

VTR VTR

Data In Comp A

No Change

This band is based on process mismatch (device W, L, etc.), reflection or overshoot (discontinuity, termination, inductance, etc.).

3

• Case 3: Comp A remains High (weakly) while the Data Output retains the previous data

• Case 1: Comp A amplifies the change and the data passes through the Steering Logic

Change

1

Change

• The time gap is used by the steering logic to pass the change or block the no-change from reaching the data output

1

THE GAP1


• JAZiO bus is usually a terminated uniform transmission line (resistive characteristic)

• Differential amplifiers in the JAZiO receiver after the input protection resistance receive exponential signals (low pass filter characteristic)

• Tune the receiver load capacitance and input protection resistance to get desired signal and VTR slew characteristics and the change/no-change gap

JAZiO’s Transition Detection

JAZiO receiver rejects undesired high frequency noise by doing transition detection instead of conventional peak detection!


Note: Red area is insufficient differential for either change or no change detection; Green indicates GAP region.

VTR

VTR

S0

S1S3

VTR and Signal Relationship(same levels and similar rise/fall times on VTRs versus signals)

Change

• Early in time• Quick amplification (after

signal and VTR crossing)• 2X the conventional signal

Steering Logic

• Later in time (delayed from VTR/VTR crossing)

• Time 85 to 95% of the same bit-time

• Xor low crossing

No Change

• Much later in time (after VTR and signal become equal)

• Slow amplification (noise and device mismatch)


Note: Red area is insufficient differential for either change or no change detection; Green indicates GAP region (no change can never occur).

VTR

VTR

S0

S1

S3

VTR and Signal Relationship(same levels and different rise/fall times on VTRs versus signals)

Change

• Earlier in time• Quick amplification (after


Steering Logic



• Xor low crossing

No Change

• Much later in time (cannot be in the same bit-time)

• Requires large noise and/or device mismatch


Note: Red area is insufficient differential for either change or no change detection; Green indicates GAP region (no change can never occur).

VTR

VTR

S0

S1

S3

VTR to Signal Techniques

VTR and Signal Relationship(same rise/fall times but different levels on VTRs versus signals)

Change

• Earlier in time• Quick amplification (after


Steering Logic



• Xor mid-point crossing

No Change

• Will not occur (100mV noise margin between signal and VTR)

• Requires large noise and/or device mismatch


Bit to Bit Static De-SkewD

ata

Inp

ut

0

Bit

s 1-

7

VT

RS

L

SL

VT

R

Dat

a O

utp

ut

0

SIG

NA

LS

FR

OM

P

AD

S

Dat

a In

pu

t 8

Dat

a In

pu

t 9

Dat

a In

pu

t 17

Dat

a O

utp

ut

8

Dat

a O

utp

ut

9

Dat

a O

utp

ut

17

Bit

s 10

-16

XO

RSt

atic

De-

skew X

OR

Static De-skew X

OR

Stat

ic D

e-sk

ew XO

RStatic D

e-skew XO

RSt

atic

De-

skew X

OR

Static De-skew

XO

RSt

atic

De-

skew X

OR

Static De-skew


Current Switching Technologies

• Change determines voltage and timing margins

– Higher voltage swings increase power and noise

– Slower rise/fall times reduce the set-up and hold time margins or frequency

Receiver Change Margin

JAZiO Switching

• Change is made much easier

– Self timed (increased timing margins)

– Larger signal (~2x)

– Less noise (lower slew rate and common mode)

– Low power (smaller swings, edge current, and lower termination voltage)

– No set-up and hold time requirement at the pin


1. Diff-Amp biasing

2. Diff-Amp gain

3. Slew rate of signals and VTR at the receiver

4. Timing skew : VTRs to signals

5. Voltage skew : VTRs to signals

JAZiO No-Change Margin

Optimize the change/no-change gap based on highest operating frequency!


DRAM Single Channel Example


ClockSource

UpperAddress &

Control Lines

LowerData Lines

VTR0VTR0

VTR1

VTR1

LowerAddress &

Control Lines

5 Bit Addr & Ctrl

5 Bit Addr & Ctrl

VTR0 & VTR0

Data

VTR1 & VTR1

Data

UpperData Lines

VTT

VTT

VTT

VTT

VTT VTT

VTT

C O N T R O L L E R

DRAMDRAMDRAM

Clock


Read Cycle 8-Bit Burst2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns

TRCD

2-Pins

2-Pins

1-Pin

1-Pin

8-Pins

18 Pins

VTR0

VTR1

CS/RAS

CAS/WE

ADR 0:7/ADR 8:15

I/O 0:17

CS

RAS

CS RAS

CAS WE

Rows0:7

Cols0:7

Cols8:15

TCAC

Rows8:15

TRCD ~20ns or 10 cyclesTCAC ~20ns or 10 cycles

CLK2-Pins


Write Cycle 8-Bit Burst2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns

TRCD

2-Pins

2-Pins

1-Pin

1-Pin

8-Pins

18 Pins

VTR0

VTR1

CS/RAS

CAS/WE

ADR 0:7/ADR 8:15

I/O 0:17

CS

RAS

CS RAS

CAS

WE

Rows0:7

Cols0:7

Cols8:15

Rows8:15

TRCD ~20ns or 10 cyclesTCWD ~20ns or 10 cycles

CLK

TCWD

2-Pins


Read, Read,Write, Read Burst

VTR0

VTR1

CS/RAS

CAS/WE

ADR 0:7/ADR 8:15

I/O 0:17

10 Cycles 10 Cycles 10 Cycles 10 Cycles

CLK


Data Latch Timing (4-bit burst)

SL

SL

1 2 3 4 5 6 7 8 9

SLL0

SLL1

SLL2

SLL3

SLD2

SLD2

SL

SL

SLD2

SLD2

Receiver Enable

Reset

FF

Divide By 2

SLSLL1

SLD2

SLSLL2

SLD2

SLSLL3

SLD2

SLSLL0

SLD2


D0

SLL0

SLL1

SLL2

SLL3

SLL2

SLL3

1.5 to 2.0ns delay

1.0 to 1.5ns delay

0.5 to 1.0ns delay

D17

1 to 4 Serial to Parallel Data Latch

D3

D71

D0

D1

D2


DRAM Dual Channel Example(skew between different DRAMs)


Data0:8

LowerAddress &

Control LinesData9:17

VTR0VTR0

ClockSource

VTT

VTT

VTR1

VTR1

VTT

VTT VTT

VTT

C O N T R O L L E R

DRAM

DRAMDRAM

VTR2

VTR2

Data

VTR2 & VTR2

Data

VTT

VTT VTT

VTT

5 Bit Addr & Ctrl

VTR0 & VTR0

Data

VTR1 & VTR1

Data

DRAMData18:26

Data27:35

VTT

5 Bit Addr & Ctrl

Clock

VTT

Clock

UpperAddress &

Control Lines


Data Flow From DRAM To Controller

VTT

VTT

CLK

VTT

VTT

Data & VTR2’sReceiver & Termination

Lat

ch

Lev

el C

onve

rter

Ver

nier

JAZ

iODRAM

Level Converter

Vernier

JAZ

iO

Lat

ch

CO

RE

DRAM

Level Converter

Vernier

JAZ

iO

Lat

ch

CO

RE

DRAM

Level Converter

Vernier

JAZ

iO

Lat

ch

CO

RE

DRAM

Level Converter

Vernier

JAZ

iO

Lat

ch

CO

RE

DRAM

Level Converter

Vernier

JAZ

iO

Lat

ch

CO

RE

DRAM

Level Converter

Vernier

JAZ

iO

Lat

ch

CO

RE

JAZ

iO

1 to

4 P

aral

lel

Lat

ch

1 to

4 P

aral

lel

CO

NT

RO

LL

ER

Data & VTR1’s


DRAM to DRAM Skew Dual Channel1 2 3 4 5 6 7 8 9

Data LatchingWindow

SL

SLVTR2VTR2

SLL0

SLL1

SLL2

SLL3

CLK

SL

SLVTR1VTR1

SLL0

SLL1

SLL2

SLL3

TOP

BOTTOM


Design Optimization


Design Optimization

Step 1Design DC bias point of the differential amplifier to be approximately (Voh+Vol)/2 (with typical conditions) with a gain of 3 to 4

Step 2Line up SL and SL to cross at the mid-point and look symmetrical to one other (with typical conditions)

Step 3Design the XORs to have no glitches and to cross low with 200pS skew in the external Data Input (with typical conditions).

Step 4Design the output driver for slow turn-on and turn-off, to get symmetric rise and fall times and a transition time equal to 80% of the data rate (with typical conditions) up to a max of 2nS.


Diff-Amp Optimization

VTR DataInput

Output

Under Typical Conditions

VTR = Data Input = (Vih+Vil)/2

Data Output = ½ Vcc

VTR = Data Input = Vih

Data Output < (½Vcc-200mV)

VTR = Data Input = Vil

Data Output > (½Vcc+200mV)


Data Output

XOR-ASL

SL

XOR-BSL

SL

The XORs should act like a low-pass filter (slow path)

First stage nand gates bias point should be approximately mid-point

Second stage nand gate bias point should be 1/3 to 1/4 VCC

Data Output

Data Output


JAZiO Scalability

1. Voltage Works with lower voltage as the technology shrinks

2. Frequency Works at higher frequency as the logic speeds up

3. Power Reduces speed-power-product at higher frequency and lower power supply

4. Bus Size Works from point-to-point to large DRAM buses

5. Bus Width Uses multiple VTRs for wider buses (x32, x64, etc.)

6. Timing Margins Transition time / cycle time ratio does not reduce

JAZiO Incorporated 1 Change No-Change Concept. JAZiO Incorporated 2 Change /No Change Concept Comp A Data In VTR Data In Comp A No Change This band is.

Documents

jazio incorporated

change concept slide

vtr sl vtr data output

steering logic change

change detection green

time gap

jazio bus

static deskew data input