SOLAR @ 2003 1 Janusz Starzyk and Yongtao Guo Janusz Starzyk and Yongtao Guo School of Electrical Engineering and Computer Science School of Electrical Engineering and Computer Science Ohio University, Athens, OH 45701, U.S.A. Ohio University, Athens, OH 45701, U.S.A. September, 2003 September, 2003
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Janusz Starzyk and Yongtao Guo School of Electrical Engineering and Computer Science
A SELF-ORGANIZING LEARNING ARRAY AND ITS HARDWARE-SOFTWARE CO-SIMULATION. Janusz Starzyk and Yongtao Guo School of Electrical Engineering and Computer Science Ohio University, Athens, OH 45701, U.S.A. September, 2003. ONTLINE. 1.Introduction SOLAR Principle Simulation Results - PowerPoint PPT Presentation
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SOLAR @ 2003 1
Janusz Starzyk and Yongtao GuoJanusz Starzyk and Yongtao Guo
School of Electrical Engineering and Computer ScienceSchool of Electrical Engineering and Computer ScienceOhio University, Athens, OH 45701, U.S.A.Ohio University, Athens, OH 45701, U.S.A.
Cosimulation - What and Why?Cosimulation - What and Why?
• Cosimulation– Simulation of heterogeneous systems whose
hardware and software components are interacting
• Benefits of cosimulation– Verifying correct functionality of the target even
before hardware is built
– Profiling the dynamic behavior
– Identifying the performance bottleneck
– Preventing problems such as over-design or under-design related to system integration
– Saving the system development cost and cycle
SOLAR @ 2003 13
Traditional Cosimulation Traditional Cosimulation EnvironmentEnvironment
– A software process• Written in high-level language,
such as C/C++
– A simulation process of hardware model
• Hardware description language, such as VHDL
– Inter-process communication (IPC) routine
• Connect the hardware process and software process
Software Model
(C-program)
Hardware Model(VHDL)
IPCroutines
Foreign IPC
proceduresIPC
Two simulators
SOLAR @ 2003 14
Traditional CosimulationTraditional Cosimulation
To perform cosimulation, two simulators should be combined and complex IPC should be developed. These IPCs are error-prone routines requiring to handle various formats of data and processed signals
Especially, when focusing on hardware part, we hope that the software part is minimized and the HW/SW communication is simple and reliable
SOLAR @ 2003 15
SOLAR CosimulationSOLAR Cosimulation
– A software process• Written in behavioral VHDL
which is not synthesizable
– A hardware process• Written in RTL VHDL which
is synthesizable
– HW/SW communication• FSM and FIFOs
SoftwareModel
(BehavioralVHDL)
Hardware Model
(RTL VHDL)
One simulator
FSM and FIFOs
SOLAR @ 2003 16
SOLAR CosimulationSOLAR Cosimulation To perform SOLAR cosimulation, one single
VHDL simulator is applied. So complex error-prone IPC is avoided. Data formats and other problems can be easily handled.
The interface between HW/SW is implemented by several FIFOs controlled by a FSM, which is simple, reliable and easily modified.
File I/O functions are used to simplify software part design when focusing on hardware part implementation.
SOLAR @ 2003 17
Co-simulation System Co-simulation System DecompositionDecomposition
SW Organization VHDL ModelSW Organization VHDL ModelAll functions and signal variables in the packages are shared, and program execution is functionally interleaved.
•lower level package is the description for system input and output, initialization and update of the memory element in the network.
•The higher level packages encapsulate new system functions based on the functions described by the lower level packages.
•The highest design level function representing the software part in the overall system implements the system organization and management.
SOLAR @ 2003 19
Single Neuron’s Hardware Single Neuron’s Hardware ArchitectureArchitecture
Figure 4: Single neuron’s learning architecture
DREG CTRL
R
R
R
R
FIFO/DMA CTRL
MAIN CONTROLLEROP
1024X32 FIFO
INTERFACE INTERFACE M
AL
U
M
SOLAR @ 2003 20
Interface ProcessInterface Process
SW
HW
time
conf
igur
atio
n
send
dat
a
Rec
eive
dat
a
conf
don
e
star
t
wai
t co
mm
and
send
com
man
d
over
read
reg
iste
rs
dma
requ
est
…
…
time
SOLAR @ 2003 21
Interface ModelingInterface Modeling
clas
sot
her
1
2
3
4
5
6
Sof
twar
e (b
ehav
iora
l V
HD
L)
Interface
FIFOs
memorymodule
Ctr
l
Others
Figure 5: Interface modeling using FSM&FIFO
Har
dw
are
(str
uct
ura
l V
HD
L)
trai
ning
SOLAR @ 2003 22
Interface SimulationInterface Simulation
Small Training Data Set
SOLAR @ 2003 23
System Synchronized WorkSystem Synchronized Work
Software Work
Hardware Work
Interface Work
Time
SOLAR @ 2003 24
Incremental PrototypingIncremental Prototyping
Overall system design can be accelerated by replacing HW subcomponent with real hardware once successfully simulated.
HW function is completely defined and
prototyped
t
HW
function
VHDL- simulated
(incremental part)
SOLAR @ 2003 25
EBE SimulationEBE Simulation Main Procedures contain:
Sending data from software to Chip Memory
Trigger start signal ALU calculation for all data Moving calculated results to
intermediate memory Threshold scanning & ID
calculation Updating the intermediate values Data Movement if the current ID
is optimal Repeating from 3 to 6 untill all
functions are scanned Sending data from Chip to
softwareIn this simulation waveform, the signal “Opt_Threshold” and “ID” represent the optimal threshold and the corresponding information index deficiency for this particular training neuron in its learning subspace.