January 2006 1 Verilog Digital System Desi gn Copyright Z. Navabi, 2006 Verilog Digital System Design Verilog Digital System Design Z. Navabi, McGraw-Hill, 2005 Z. Navabi, McGraw-Hill, 2005 Chapter 2 Chapter 2 Register Transfer Level Register Transfer Level Design with Verilog Design with Verilog Prepared by: Prepared by: Homa Alemzadeh Homa Alemzadeh
77
Embed
January 2006 1 Verilog Digital System Design Copyright Z. Navabi, 2006 Verilog Digital System Design Z. Navabi, McGraw-Hill, 2005 Chapter 2 Register Transfer.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
January 2006 1Verilog Digital System Design Copyright Z. Navabi, 2006
Verilog Digital System Design Verilog Digital System Design Z. Navabi, McGraw-Hill, 2005Z. Navabi, McGraw-Hill, 2005
Chapter 2Chapter 2Register Transfer LevelRegister Transfer Level
Taking a high level description of a designTaking a high level description of a design Partitioning Partitioning Coming up with an architectureComing up with an architecture Designing the bussing structureDesigning the bussing structure Describing and implementing various components Describing and implementing various components
of the architectureof the architecture Steps in RT level design:Steps in RT level design:
Control/Data PartitioningControl/Data Partitioning Data Part DesignData Part Design Control Part DesignControl Part Design
January 2006 5Verilog Digital System Design Copyright Z. Navabi, 2006
inputinput Flags, ...; Flags, ...;inputinput Opcodes, ...; Opcodes, ...;inputinput ExternalControls, ...; ExternalControls, ...;outputoutput ControlSignals; ControlSignals;// Based on inputs decide :// Based on inputs decide :// What control signals to issue,// What control signals to issue,// and what next state to take// and what next state to take
endmoduleendmodule
Outline of a ControllerOutline of a Controller
Takes Takes control control
inputs from inputs from thethe
Data PartData Part
January 2006 15Verilog Digital System Design Copyright Z. Navabi, 2006
Elements of VerilogElements of Verilog
We discuss basic constructs of Verilog language for We discuss basic constructs of Verilog language for describing a hardware module.describing a hardware module.
January 2006 16Verilog Digital System Design Copyright Z. Navabi, 2006
Elements of VerilogElements of VerilogHardware Hardware Modules Modules
Primitive Primitive InstantiationsInstantiations
Assign Assign Statements Statements
Condition Condition ExpressionExpression
Procedural Procedural BlocksBlocks
Module Module InstantiationsInstantiations
January 2006 17Verilog Digital System Design Copyright Z. Navabi, 2006
January 2006 18Verilog Digital System Design Copyright Z. Navabi, 2006
Hardware ModulesHardware Modules
modulemodule module-name module-name List of ports;List of ports;DeclarationsDeclarations......Functional specification of moduleFunctional specification of module......
endmoduleendmodule
Module SpecificationsModule Specifications
KeyworKeyword d
modulemodule
module :module :The Main The Main ComponeCompone
nt of nt of VerilogVerilog
Keyword Keyword endmodendmod
uleule
Variables, Variables, wires, and wires, and
module module parametersparameters
are declared.are declared.
January 2006 19Verilog Digital System Design Copyright Z. Navabi, 2006
Hardware ModulesHardware Modules
There is more than one way to describe a Module in Verilog.There is more than one way to describe a Module in Verilog. May correspond to descriptions at various levels of abstraction May correspond to descriptions at various levels of abstraction
or to various levels of detail of the functionality of a module. or to various levels of detail of the functionality of a module. Descriptions of the same module need not behave in exactly Descriptions of the same module need not behave in exactly
the same way nor is it required that all descriptions describe a the same way nor is it required that all descriptions describe a behavior correctly.behavior correctly.
We discuss basic constructs of Verilog language for a hardware We discuss basic constructs of Verilog language for a hardware module description.module description.
We show a small example and several alternative ways to We show a small example and several alternative ways to describe it in Verilog.describe it in Verilog.
January 2006 20Verilog Digital System Design Copyright Z. Navabi, 2006
January 2006 54Verilog Digital System Design Copyright Z. Navabi, 2006
ControllersControllers
Controller OutlineController Outline
Decisions Based on : Inputs ,
Outputs , State
Issue Control Signal
Set Next State
Go to Next State
January 2006 55Verilog Digital System Design Copyright Z. Navabi, 2006
ControllersControllers
Controller:Controller: Is wired into data part to control its flow of data.Is wired into data part to control its flow of data. The inputs to it controller determine its next states and The inputs to it controller determine its next states and
outputs.outputs. Monitors its inputs and makes decisions as to when and what Monitors its inputs and makes decisions as to when and what
output signals to assert.output signals to assert. Keeps the history of circuit data by switching to appropriate Keeps the history of circuit data by switching to appropriate
states.states. Two examples to illustrate the features of Verilog for describing Two examples to illustrate the features of Verilog for describing
state machines:state machines: SynchronizerSynchronizer Sequence DetectorSequence Detector
January 2006 56Verilog Digital System Design Copyright Z. Navabi, 2006
ifif (reset) current = s0; (reset) current = s0; elseelse
casecase (current) (current) s0: s0: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; s1: s1: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s0; current <= s0; s2: s2: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s3; current <= s3; s3: s3: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; endcaseendcase
endend
assignassign w = (current == s3) ? 1 : 0; w = (current == s3) ? 1 : 0;
endmoduleendmodule
Verilog Code for Verilog Code for 110110 Detector Detector
January 2006 64Verilog Digital System Design Copyright Z. Navabi, 2006
Sequence DetectorSequence Detector
modulemodule Detector110 ( Detector110 (inputinput a, clk, reset, a, clk, reset, outputoutput w); w);
ifif (reset) current = s0; (reset) current = s0; elseelse
casecase (current) (current) s0: s0: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; s1: s1: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s0; current <= s0; s2: s2: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s3; current <= s3; s3: s3: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; endcaseendcase
endend
Verilog Code for Verilog Code for 110110 Detector Detector
if-elseif-else statementstatementchecks for checks for
resetresetAt the At the Absence Absence of aof a 1 1 on on
resetreset
The 4 Case-The 4 Case-alternativesalternatives
each correspond each correspond to a state of state to a state of state
machinemachine
January 2006 66Verilog Digital System Design Copyright Z. Navabi, 2006
Sequence DetectorSequence Detector
State Transitions on Corresponding Verilog CodeState Transitions on Corresponding Verilog Code
s10
s20
s00
a=0
a=1
s1:
if (a)
current <= s2;
else
current <= s0;
January 2006 67Verilog Digital System Design Copyright Z. Navabi, 2006
Sequence DetectorSequence Detector
endend................................................................................................................assignassign w = (current == s3) ? 1 : 0; w = (current == s3) ? 1 : 0;
endmoduleendmodule
Verilog Code for Verilog Code for 110110 Detector Detector
Assigns a Assigns a 11 to to w ow output when utput when
Machine Machine Reaches to Reaches to s3s3
StateState
Outside of Outside of the the alwaysalways
Block:Block:A A
combinationcombinational circuital circuit
January 2006 68Verilog Digital System Design Copyright Z. Navabi, 2006
TestbenchesTestbenches
TestbenchesTestbenches
A SimpleA SimpleTesterTester
Tasks Tasks And And
FunctionsFunctions
January 2006 69Verilog Digital System Design Copyright Z. Navabi, 2006
A Simple TesterA Simple Tester
TestbenchesTestbenches
A SimpleA SimpleTesterTester
Tasks Tasks And And
FunctionsFunctions
A SimpleTester
January 2006 70Verilog Digital System Design Copyright Z. Navabi, 2006
A Simple TesterA Simple Tester`timescale`timescale 1ns/100ps 1ns/100ps
$display$display ("A 1 was detected on w at time = ("A 1 was detected on w at time = %t", %t", $time$time););
endmoduleendmodule
Testbench for Testbench for Detector110Detector110
Reports the Reports the Times at Times at
whichwhichthe the wwww
Variable Variable becomes becomes 11
always always Block Block Wakes up Wakes up when when wwww ChangesChanges
This Note Will This Note Will Appear in the Appear in the
Simulation Simulation Environment’s Environment’s
Window: Window: “Console” or “Console” or “Transcript”“Transcript”
A Verilog A Verilog System System TaskTask
January 2006 75Verilog Digital System Design Copyright Z. Navabi, 2006
Tasks And FunctionsTasks And Functions
TestbenchesTestbenches
A SimpleA SimpleTesterTester
Tasks Tasks And And
FunctionsFunctions
Tasks And
Functions
January 2006 76Verilog Digital System Design Copyright Z. Navabi, 2006
Tasks And FunctionsTasks And Functions Verilog Tasks and Functions:Verilog Tasks and Functions:
System tasks for Input, Output, Display, and Timing System tasks for Input, Output, Display, and Timing ChecksChecks
User defined tasks and functionsUser defined tasks and functions Tasks:Tasks:
Can represent a sub module within a Verilog moduleCan represent a sub module within a Verilog module Begins with a Begins with a task task keywordkeyword Its body can only consist of sequential statements like Its body can only consist of sequential statements like
if-elseif-else and and casecase Functions:Functions:
Can be used for corresponding to hardware entities Can be used for corresponding to hardware entities May be used for writing structured codesMay be used for writing structured codes Applications: Representation of Boolean functions, data Applications: Representation of Boolean functions, data
and code conversion, and input and output formattingand code conversion, and input and output formatting
January 2006 77Verilog Digital System Design Copyright Z. Navabi, 2006
SummarySummary
This chapter presented:This chapter presented: An overview of Verilog and how this language is An overview of Verilog and how this language is
used for design and test of RT level description used for design and test of RT level description Components of an RT level design Components of an RT level design Small examples to illustrate such components and Small examples to illustrate such components and
at the same time Verilog coding of hardware at the same time Verilog coding of hardware modulesmodules
The descriptions in this part were all synthesizable The descriptions in this part were all synthesizable and had a one-to-one hardware correspondence. and had a one-to-one hardware correspondence.
How testbenches could be developed in Verilog and How testbenches could be developed in Verilog and new constructs of it in this partnew constructs of it in this part