J - K & MASTERSLAVE FLIPFLOPS

JK & MASTER SLAVE FLIP-FLOP

MADE BY- Krishma Parekh Enrollment NO.-140210107039 Computer branch- 3rd SEMESTER

INTRODUCTION After getting problems SR-Flip flops , D-Flip

flops , T-Flip flops…which gives invalid state in the execution of the circuit

To solve up that Problem we got a new Flip-Flop which is called J-K Flip Flop

This Flip Flop removes invalid state but instead of invalid state the output of JK Flip Flop will toggle between 1 &0….

Now we will look upon this construction and working of this circuit and the solution of Toggle Condition…

What is a JK Flip-flop ? A flip-flop is a circuit that has two

stable states and can be used to store state information.

The flip-flop can be made to change state by signals applied to one or more control inputs and will have one or two outputs.

JK Terminology/Structure

Has 5 inputs named: J(set),K(reset), PR, CLR, and CLK

Has 2 outputs: Q and Q’

Set: when it stores a binary 1Cleared (reset): when it stores a binary 0

PR = PresetCLR = ClearCLK = Clock

Outputs

The Q output is the primary output. This means that the binary bit stored in the flip-flop, 1 or 0, is the same as Q.

The Q’ output is the opposite binary bit value that is stored in Q.

The PR and CLR inputs always override the J,K inputs.

Inputs: J and K

The logic states applied to the J and K inputs cause the flip-flop to operate 4 different ways.

The way the logic state is applied to J and K is called Mode of Operation.

The mode of operation refers to the condition of the flip-flop as it prepares for the positive clock pulse.

Four Modes Of Operation

J K Q Q’ Mode0 0 Q Q’ Memor

y1 0 1 0 Sets0 1 0 1 Resets1 1 Q’ Q Toggle

The 4 modes of operation are: hold, set, reset, toggle

JK contains an internal Active Low SR latch.

Active Low SR Latch

S’ – “set” R’ – “reset”

Q Q’

0 0 Invalid Invalid0 1 1 01 0 0 11 1 Q Q’

Point to remember:

A ‘0’ at the set or the reset will either

set or reset the value of Q.

Truth Table for NAND

A B X

0 0 1

0 1 1

1 0 1

1 1 0

A B C X0 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1 0

2 Inputs: 3 Inputs:

Mode of Operation: Hold

J K Q Q’ Orig. Q Orig. Q’0 0 0 1 0 1

Hold: no change in Q.

Mode of Operation: Set

J K Q Q’ Orig. Q

Orig. Q’

1 0 1 0 0 1

Set: Q = 1.

Mode of Operation: Reset

J K Q Q’ Orig. Q

Orig. Q’

0 1 0 1 1 0

Reset: Q = 0.

Mode of Operation: Toggle

J K Q Q’ Orig. Q Orig. Q’

1 1 1 0 0 1

Toggle: Q = Q’.

Mode of Operation: Toggle again

J K Q Q’ Orig. Q

Orig. Q’

1 1 0 1 1 0

Toggle: Q = Q’.

During a Time Period

Characteristic Equation

Q J K Q(t + 1)0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 0

Characteristic Equation:

Q(t+1) = J.Q’+ K’.Q

J K Q Q’ Mode0 0 Q Q’ Hold1 0 1 0 Sets0 1 0 1 Reset

s1 1 Q’ Q Toggl

e

Q(t+1) = J.Q’+ K’.QQ is the primary output.

Characteristic Equation

Master Slave D Flip-flop

A negative edge triggered flip-flop:

On the negative edge of the clock, the master captures the D input and the slave outputs it.

DC

Y DC

QQ

Master Slave

Master-Slave J-K Flip-FlopA master-slave flip-flop contains two flip-flops/latches:

Master S-C latch (S-C Flip-Flop) - receives data while the input trigger clock is HIGH.

Slave S-C latch (S-C Flip-Flop) - receives data from the master and output it when the clock goes LOW.

Two RS flip-flops are combined together using an inverter to construct a master-slave JK flip-flop.

When the clock input Cp is 0, the output of the inverter is 1. The slave latch is then enabled, and its output Q is equal to the master latch output. The master latch is disabled, because Cp is 0.

When a logic-1 clock pulse is applied, the values on S and R control the value stored in the master latch. The slave is disabled as long as the pulse remains at the 1 level, because its Cp input is equal to 0. Any changes in the external S and R inputs change the master output, but cannot affect the slave output.

When the pulse returns to 0, the master is disabled and is isolated from the S and R inputs. At the same time, the slave is enabled, and the current value of master output is transferred to the output of the flip-flop (slave output).

It solves up the problem occur in JK Flip Flop and solves up race around condition which occurs in other flip flops.

Master-Slave J-K Flip-Flop – Operation of the Circuit…

Master-Slave J-K Flip-Flop – Timing Diagram

Note: Here NC means no change.

THANKYOU FOR WATCHING !!!