ITRS may in the future provide Research Guidance by defining better Innovation Questions for R&D ITRS Maastricht 04/07/06.

ITRS may in the future provide Research Guidance by defining

better “Innovation” Questions” for R&D

ITRS Maastricht04/07/06

2

Source: Siemens

The engine of our industry : The exceptional shrinking price of microelectronics products

The engine of our industry : The exceptional shrinking price of microelectronics products

Price of 1 Megabit of Si Memory

75 000 euros

5 000 euros

400 euros

120 euros

30 euros

5 euros0,5 euro

0,05 euro1973

1977

19811984

19871990

19952000

0,01 euro

2003

‘Post-it’

Thanks to « classical scaling »

No need for economics : the smaller, the better

3

Gordon Moore, 1965Gordon Moore, 1965““Reduced cost is one of the big Reduced cost is one of the big attractions of integrated attractions of integrated electronics, and the cost electronics, and the cost advantage continues to increase advantage continues to increase as the technology evolves as the technology evolves toward the production of larger toward the production of larger and larger circuit functions on a and larger circuit functions on a single semiconductor substrate.”single semiconductor substrate.”Electronics, Volume 38, Electronics, Volume 38, Number 8, April 19, 1965Number 8, April 19, 1965

4

“Simplified” Transistor Roadmap

65nm 45nm 32nm 22nm2007 2009 2012

PDSOI FDSOI

2015

bulk

stressors + substrateengineering

+ high µmaterials

MuGFETMuCFET

elec

tro

stat

ic c

on

tro

lSiON

poly

high k

metal

gate stack

planar 3D

Source: European Nanoelectronics Initiative Advisory Council (ENIAC)

5

Food for thought

“Moore’s Law and its continuance is an economic rather than a technical statement” (Bernard Meyerson, chief technologist for IBM’s Systems & Technology Group). “Clock frequency is not the driver of system performance. You can get a better result by making tradeoffs to balance numerous aspects of performance” (Bernard Meyerson) Classical Scaling -- the glue that connected Moore’s Law to performance – replaced by “equivalent scaling”.

6

Pursuing the race for added value for the end customerCombining on chip ULSI and out of the chip integration

More than Moore: DiversificationM

ore

Mo

ore

: M

inia

turi

zati

on

Combining SoC and SiP: Higher Value SystemsBas

elin

e C

MO

S:

CP

U, M

emo

ry, L

og

icBiochips

SensorsActuators

HVPower

Analog/RF Passives

130nm

90nm

65nm

45nm

32nm

22nm...V

Information Processing

Digital contentSystem-on-chip

(SoC)

Interacting with people and environment

Non-digital contentSystem-in-package

(SiP)

Beyond CMOS

2005 edition

7

The blurring nature of products

What is it ?A phone ?A camera ?A PDA ?

What makes its value ?

8

From R&D to R-I-D (Hatchuel & Weil)

R&DR : Answering the questions asked

Good if able to solve the issues it was requested to solveD : Fine tuning the process / product

Who asks the right questions ?In a stable environment, no need to look for new questions

R-I-DIn a changing environment : need for ”I” function

“I” for InnovationDefining the questions to be solved by the “R”

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What does it mean for ITRS ?

ITRS goalProvide research guidance for the industry

In the pastSmaller was better, and cheaper We didn’t need an explicit economic model to tell us which research was useful No need for “I”ITRS role : identify the red brick walls

TodaySystem performance no longer purely commanded by device performanceMore Moore and More than MooreWhat will bring more value to the end user ?

Need for “I”Natural role of ITRS : Defining the questions to be solved by the “R”

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How to achieve that ?Proposed Approach: assessment of the potential value return from research topicsPossible paths

Characterizing new non-scaling dimensions (More than Moore) by parameters that could be used for value assessment

e.g. Inductors, MEMS/NEMS, …

Seek feedback from pre-competitive consortia like SMT, IMEC, SELETE, etc.Possible TWG involvement preparation/proposals for July ITRS

Assy & Packaging : System integration white paperExtension of Design TWG roadmap / system drivers (example Automotive HV power, Sensors) Link PIDS / Design (extending MASTAR to system level)Optical InterconnectRF Wireless … Additional ideas are welcome.

11

Backup

12

IRC Plenary (Misc. 1)Other IRC Plenary Communication ITEMS:

Publication Arrangements CD and Book by RegionLinda Wilson only handling the “free” hardcopies by Region – need quantity by Region (limited number – 60 copies USA (trade for CDs)) Order Hard copies - $160? plus shipping and handling all directly with JEITA Office (limited quantity!)Order Copies ship from Japan (coordinated by JEITACD (plus Exec Summary – available when?) - $25 nominal cost (still too high?) plus shipping and handlingLinda produce Master copy to each region and make their own copies only for internal to Region to ITRS supporters

Domestic Regional TWG Composition/Membership Guidelines (Patrick Cogez foil)

Old Recommendation for domestic TWG guidance presently from Linda Wilson, (USA-based 1990’s -based) guideline of 7 recognized members Managed by Domestic TWG Chairman - Voting by consensus based on equitable distributionNeed Revised Region-variable guidelines (USA, Japan, Korea, Taiwan, and Europe)

Not mandatory “official” guidelines, but recommendations to balance consensus influence

Need to also discuss at next IRC telecon to update distribution list guidelinesHow to include emerging regions, such as membership in Worldwide Semiconductor Council (WSC); and identify approval process for actual members for invitation-only communication email by Linda Wilson

iNEMI Semiconductor Roadmap Chapter Draft (2005 ITRS Exec Summary Re-edit) due May 18th Final Draft Sept’06, publish APEX Feb’07

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IRC Plenary (Misc. 2)IEEE & iNEMI Roadmaps

IEEE Nano-electronics Standards Roadmap in 5/18 New York – Contact Nathan Tinker/IEEE (Paolo follow up)

Reed Semiconductor International - Online Conference - doneApr 18-20

4bits/Flash cellSaifun / Spansion EE Times publication “45nm” 4bits/cell production 2008PIDS Table 43a 4bits/cell after 2010Alan add to ORTC Tables and Flash Model beginning 2008 as a proposal

Timing 2007 ITRS Meetings (Europe SEMICON move out Jun’07, Oct’08?)

ITRS will be held April 23, 24 in FranceAEC/APC during preceding week 4/18-20 Dresden; other potential meetings in preceding week: INC3 Europe or IMEC review week)]

USA – SEMICON USA July 9th or 16th Japan – SEMICON Japan end of November, beginning December

Wireless not present in Vaalsbroek – need earlier communication - AR Wireless/Huang

Important cross-iTWG issues – iTWGs should communicate with Wireless TWG via Telecon in 2Q06?Need to confirm attendance ahead of USA SEMICON ITRS meeting time to inform all iTWGs.