ITRS 2010 Test and Test Equipment – San Francisco, USA Test and Test Equipment July 2010 San Francisco, USA Roger Barth - Micron ITRS Test TWG.

ITRS 2010 Test and Test Equipment – San Francisco, USA

Test and Test Equipment July 2010San Francisco, USA

Roger Barth - Micron

ITRS Test TWG

ITRS 2010 Test and Test Equipment – San Francisco, USA2

2010 Test TeamAkitoshi NishimuraAmit MajumdarAnne GattikerAtul GoelBill PriceBurnie WestCalvin CheungChris Portelli-HaleDave ArmstrongDavide AppelloDennis ContiErik VolkerinkFrancois-Fabien FerhaniFrank PoehlGibum KooHirofumi TsuboshitaHiroki IkedaHisao HoribeJeong Ho ChoJerry Mcbride

Sanjiv TanejaSatoru TakedaSejang OhShawn FetterolfShoji IwasakiStefan EichenbergerSteve ComenSteve TildenSteven SlupskyTakairo NagataTakuya KobayashiTetsuo TadaTom WilliamsUlrich SchoettmerWendy ChenYasuo SatoYervant ZorianYi Cai

Jody Van HornJohn YS KimKazumi HatayamaKen LanierKen TaokaKen-ichi AnzouKhushru ChhorMasaaki NambaMasahiro KanaseMichio MaekawaMike BienekMike Peng LiMike RodgersPaul RoddyPeter MaxwellPhil NighPrasad MantriRene SegersRob AitkenRoger Barth


2009 Changes

• DFT– Test data compression and test time potential solutions identified– Major rewrite completed of the Design Chapter DFT section

• Test Cost– Test cost survey completed that quantifies industry view– Test parallelism dependency by device type modified based on I/O count

• Adaptive Test– New chapter section shows necessity for adaptive test to lower cost

• Prober– Complete redo of prober table to address parallelism and power

• Probecard– LCD display driver probe added as driver

• Handler– Added 10-50 Watt handler category

• Test Sockets– Socket BW limitations on current sockets– New future contacting solutions are required


2010 Drivers Unchanged

Revised

New

Drop

• Device trends– Increasing device interface bandwidth and data rates

– Increasing device integration (SoC, SiP, MCP, 3D packaging)

– Integration of emerging and non-digital CMOS technologies

– Device characteristics beyond the deterministic stimulus/response model

– Fault Tolerant architectures and protocols

– 3 Dimensional silicon - multi-die and Multi-layer

– Multiple Power modes and Multiple time domains

– Complex package electrical and mechanical characteristics

• Test process complexity– Adaptive test and Feedback data

– Concurrent test within a DUT

– Maintaining unit level test traceability

– Device customization / configuration during the test process

– “Distributed test” to maintain cost scaling


Drivers

• Economic Scaling of Test– Physical limits of packaged test parallelism

– Test data volume

– Managing interface hardware and (test) socket costs

– Multiple Insertions and System test

– Effective limit for speed difference of HVM ATE versus DUT

– Trade-off between the cost of test and the cost of quality

Unchanged

Revised

New

Drop


2010 Difficult Challenges

• Test for yield learning – Critically essential for fab process and device learning below optical device

dimensions

• Detecting Systemic Defects – Testing for local non-uniformities, not just hard defects– Detecting symptoms and effects of line width variations, finite dopant

distributions, systemic process defects

• Screening for reliability– Effectiveness and Implementation of burn-in, IDDQ, and Vstress testing– Detection of erratic, non deterministic, and intermittent device behavior

Unchanged

Revised

New

Drop


2010 Difficult Challenges

• Potential yield losses– Tester inaccuracies (timing, voltage, current, temperature control,

etc)

– Over testing (e.g., delay faults on non-functional paths)

– Mechanical damage during the testing process

– Defects in test-only circuitry or spec failures in a test mode e.g., BIST, power, noise

– Some IDDQ-only failures

– Faulty repairs of normally repairable circuits

– Decisions made on overly aggressive statistical post-processing

Unchanged

Revised

New

Drop


Test Cost Components


Adaptive Test

• Modify testing based on analysis of previous results

– Real-time

– Near-time

– Off-line

• Benefits– Higher Quality

– Fast Test Time Reduction

– Lower cost

– Fast yield learning

• Requires data infrastructure– Database

– Analysis tools Confidence

• Implementation is evolving– Multiple learning steps

– Delaying won’t ease task


Test Parallelism Changes

• Soc, Low Performance Logic, commodity DRAM and Commodity Flash unchanged


SoC Changes

• Fault models pulled in Bridging faults to 2011• Full ATE standardized interface delayed from 2013 to 2015• DFT based defect analysis has slightly extended life


Memory Changes

• Data rates pulled in thru 2016


RF Changes

• Increase in short term Carrier Frequency for 2010• Limited need for 12 GHz requirements…• 20GHz appears to be small volume as compared to other devices…

may be lack of developed instrumentation• Target is now 60+ GHz (personal networks and SR radar)


Probing Technology Changes

• 2011 memory roadmap will separate DRAM and Flash in table

• Low contact force probing process requirement added to roadmap


Prober Characteristics

• Many changes / additions from 2008 tables

– Probe card dimensions– Test head weight– Temperature accuracy– 450mm wafer support– Chuck leakage– Planarity– Etc.

• Solutions exist until 2014

2009

2008DRIVERS

Full wafer test

Device Power


3D Devices

• Multiple die system– Sub-systems designed to operate and be

assembled together– Process optimized for contents of each die

• Logic, DRAM, NVM, Analog– Connection by potentially 1000’s of TSVs

(Thru Silicon Via’s)

• Design, Interconnect, Assembly and Test, PIDS and FEP problem

• DFT Requirements– Testability of each die– Vias cannot be probed due to ESD issues– N+ die test methodology a possibility as

die added, not recommended– Final 3D Packaged test

void


TSV Test Strategy

• Strong Recommendations– Can’t (and don’t) touch the TSVs.

• Alternative test pads with ESD protection are ok (analog, power, digital)

• Use Boundary scan test for access

– Design independently testable die• Cannot require resources from other die for test

• Need not operate in mission mode

– Design low resistance TSVs – TSV geometry and parametrics are not be the critical technology limiter

• Needs– Thermal considerations needed for scan after stack – Optimal functional / performance / system test– Possible benefit to self Speed Test (SST) thru TSV loop (post stack)

• Trends– System test / validation much more important in the future with TSVs. The

die stack is a system.


Test Time Reduction Potential Solutions

• Required test time reduction is driven by SoC• Assumes increasing design complexity and transistor count will

not increase test time


DFT Compression Potential Solutions

• Development is necessary to get very high levels of data compression

• Demonstrated techniques are just approaching 1000x

• 100k data compression necessary out in time…no clear path yet!


High Speed Interfaces

• Bit bandwidth increasing…• Physical limit? • Test limit?

Test Sockets are not able to support

controlled impedance contacts at >15 GT/s

Limit?

Jitter Test Critical for HS Interfaces


Summary of 2010 table (trend) Changes

• Device Trends and Challenges significantly updated

• Minor adjustments to tables– Test parallelism

– SoC

– Memory

– Probing Technology

• Refinement of TSV testing strategy

ITRS 2010 Test and Test Equipment – San Francisco, USA Test and Test Equipment July 2010 San Francisco, USA Roger Barth - Micron ITRS Test TWG.

Documents

usa test

cost of test

test process distributed

test mode

test equipment san francisco

test cost components

difficult challenges

test parallelism changes