ITRS-2001 Design ITWG Summary (work in progress) July 18, 2001.

ITRS-2001 Design ITWG Summary(work in progress)

July 18, 2001

New SYSTEM DRIVERS Chapter in ITRSNew SYSTEM DRIVERS Chapter in ITRS

• Defines segments of silicon market that drive process and design technology

• Replaces the 1999 SOC Chapter• Along with ORTCs, serves as “glue” for ITRS• 4 Drivers: SOC (Japan), MPU (USA), DRAM (Korea), M/S

(Europe)– SOC: driven by cost, power, integration– SOC: drives device requirements, packaging, I/O counts, …– SOC: same as “ASIC-LP”

• Each section• Nature, evolution, formal definition of this driver• What market forces apply to this driver ?• What technology elements (process, device, design) does this

drive?• Key figures of merit, and futures

• Driven by Design TWG (ABK = chair)

Mixed-Signal System Driver RoadmapMixed-Signal System Driver Roadmap• Mixed-signal circuits increasingly critical to system performance, cost

– Define “AMS boundary conditions” for Design technology roadmap by choosing critical and important analog/RF circuits, then identifying circuit performance needs and related device parameter needs

• Based on figures of merit for four basic analog building blocks, can estimate future device parameter needs

Roadmap for basic Roadmap for basic analog / RF analog / RF circuitscircuits

Roadmap for Roadmap for device parameters device parameters (needs)(needs)

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LLminmin 2001 … 20152001 … 2015

…………

analog transistor ganalog transistor gmm/g/gdsds

…………

Mixed-Signal System DriversMixed-Signal System Drivers

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System drivers for mass markets can be identified from the FoM approach

““System Driver” Models Are Changing System Driver” Models Are Changing Example – MPUExample – MPU

• Old MPU model – 3 flavors• Cost-performance at introduction (CP-Intro)

– 340+ mm2 die, small L1 cache (32KB in 180nm)

• Cost-performance at production (CP-Prod)– 170+ mm2 die, shrink of previous generation’s CP-Intro chip

• High-performance (HP)– 310+ mm2 die, same as CP-Prod but with large L2 cache (512KB in 180nm)

• SRAM and logic transistor counts double every generation

• New MPU model - 2 flavors• Cost-performance at production (CP)

– 140 mm2 die, “Pentium 4” / “desktop”

• High-performance at production (HP) – 310 mm2 die, “Itanium” / “server”

• Both CP, HP have multiple cores (“helper engines”), on-board L3 cache, …– Multi-cores == more dedicated, less general-purpose logic; driven by power and reuse

considerations; reflect convergence of MPU and SOC

• “Moore’s Law” still applies to tx counts, but NOT to frequency– doubling is each generation, NOT each 18 months

Example Supporting Analyses Example Supporting Analyses (MPU Diminishing Returns)(MPU Diminishing Returns)

• Pollack’s Rule– In a given process technology, new uArch takes 2-3x area of old (last

generation) uArch, and provides only 40% more performance– Backup Slide: process generations (x-axis) versus (1) ratio of Area of New/Old

uArch, (2) ratio of Performance of New/Old (approaching 1) – Other Backup: SPECint, SPECfp per MHz, SPECint per Watt all decreasing

• Power knob running out– Speed == Power– 10W/cm2 limit for convection cooling, 50W/cm2 limit for forced-air cooling– Large currents, large power surges on wakeup– Cf. 140A supply current, 150W total power at 1.2V Vdd for EV8 (Compaq)

• Speed knob running out– Historically, 2x clock frequency every process generation (see Backup Slides)

• 1.4x from device scaling (but running into t_ox, other limits – see Device discussion)• 1.4x from fewer logic stages (from 40-100 down to around 14 FO4 INV delays)

– Clocks cannot be generated with period < 6-8 FO4 INV delays– Pipelining overhead (1-1.5 FO4 INV delay for pulse-mode latch, 2-3 for FF)– Around 14-16 FO4 INV delays is limit for clock period (L1 $ access, 64b add)

• Cannot continue 2x freq per generation trend in ITRS

New On-Chip Max Clock Frequency ModelNew On-Chip Max Clock Frequency Model

• Flat at 16 FO4 INV delays– FO4 INV delay = delay of inverter driving load equal to 4x its input cap =

roughly 14x CV/I device delay metric in ITRS PIDS Chapter

• No local interconnect in the model– negligible, and scales with device performance

• No (buffered) global interconnect in the model, either – was unrealistically fast in ITRS99 model

– global interconnects are pipelined (clock frequency is set by time needed to complete local computation loops, not time for global communication - cf. Pentium-4 and Alpha-21264)

– Note: interconnect delay per se is not a problem (!)

• Clock period decreases from 26 FO4 delays in 2001 (Pentium-4) at historical rates, then flattens at 16 FO4 delays– See discussion of MPU “System Driver” …

New Layout Density ModelsNew Layout Density Models• Semi-custom Logic: Avg size of 4t gate = 32MP2 = 320F2

– MP = lower-level contacted metal pitch– F = min feature size (technology node)– 32 = 8 tracks standard-cell height times 4 tracks width (average NAND2)– Additional whitespace factor = 2x (i.e., 100% overhead)

• Custom Logic: 1.25x ASIC density• SRAM: (used in MPU)

– bitcell area (units of F^2) is near flat: 223.19*F (um) + 97.748 – peripheral overhead = 60% – memory content is increasing (driver: power) and increasingly fragmented– will see paradigm shifts in architecture/stacking; eDRAM, 1-T SRAM, …

• Significant SRAM density increase, slight Logic density decrease, compared to 1999 ITRS– 130nm node: old ASIC logic density = 13M tx/cm2, new = 11.6M tx/cm2

– 130nm node: old SRAM density = 70M tx/cm2, new = 140M tx/cm2– Chief impact: power densities, logic-memory balance on chip

• Very well-calibrated to design data, multiple sectors

SRAM “A-Factors” for Simple 6T SRAM Cell using SRAM “A-Factors” for Simple 6T SRAM Cell using Microprocessor Logic CMOS Process TechnologyMicroprocessor Logic CMOS Process Technology

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0.13micron (Intel, IEDM

2000.p.567))

0.13micron (M

otorola, IEDM2000,p.571))

0.18micron (Intel, IEDM

1998,p.197)

0.25micron (Intel, IEDM

1996,p.847)

0.35micron (Intel, IEDM

1994)

0.3micron (M

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DRAM half-pitch (F) A-Factor (A*F2)0.13micron (Intel, IEDM2000.p.567)) 143.70.13micron (Motorola, IEDM2000,p.571)) 146.740.18micron (Intel, IEDM1998,p.197) 172.530.25micron (Intel, IEDM1996,p.847) 164.160.35micron (Intel, IEDM1994) 167.30.3micron (Motorola, IEDM1994) 175.6

Constrained Power: Logic-Memory Constrained Power: Logic-Memory Balance Analyses (see Backup Slides)Balance Analyses (see Backup Slides)

• Constant power or power density decreasing logic content•#Tr Logic, SRAM cannot scale together as in current ITRS?

•Can “derive” same result from new/reuse logic design productivity gap (!)

•How will Design Technology ensure continued flow of high-value designs?

Anomaly going from 45nm to 32nm due to constant Vdd

Outline of ITRS DESIGN ChapterOutline of ITRS DESIGN Chapter

• Context– Scope of Design Technology– High-level summary of complexities (at level of “issues”) – Cost, productivity, quality, and other metrics of Design Technology

• Overview of Needs– Driver classes and associated emphases– SOC, MPU, DRAM, MS– Resulting needs (e.g., power, …, cost-driven design)

• Summary of Difficult Challenges• Detailed Statements of Needs, Potential Solutions

– System-Level, Circuit, Logic/Physical, Verification, Test

(Dataquest, 2001) Cost Metrics Forecast

$10,000,000

$100,000,000

$1,000,000,000

$10,000,000,000

$100,000,000,000

1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005

Design Cost for Largest Possible ASIC

Same Cost RTL Methodology Only

Design Cost and Quality RequirementDesign Cost and Quality Requirement

• Design cost of “largest ASIC” rises despite major DT innovations• Other Dataquest numbers confirm memory content rising• Currently seeking metric, data, requirements for design quality

Design Cost RequirementDesign Cost Requirement• “Largest possible ASIC” design cost model

• engineer cost per year increases 5% per year ($181,568 in 1990)• EDA tool cost per year increases 3.9% per year ($99,301 in 1990)• #Gates in largest ASIC design per ORTCs (.25M in 1990, 250M in 2005)• %Logic Gates constant at 70% (see next slide)• #Engineers / Million Logic Gates decreasing from 250 in 1990 to 5 in 2005• Productivity due to 8 Design Technology innovations (3.5 of which are still

unavailable) : RTL methodology; In-house P&R; Tall-thin engineer; Small-block reuse; Large-block reuse; IC implementation suite; Intelligent testbench; ES-level methodology

• Small refinements: (1) whether 30% memory content is fixed; (2) modeling increased amount of large-block reuse (not just the ability to do large-block reuse). No discussion of other design NRE (mask cost, etc.).

• #Engineers per ASIC design still rising (44 in 1990 to 875 in 2005), despite assumed 50x improvement in designer productivity

• New Design Technology -- beyond anything currently contemplated -- is required to keep costs manageable

Design Quality RequirementDesign Quality Requirement

• “Normalized transistor” quality model• speed, power, density in a given technology• analog vs. digital• custom vs. semi-custom vs. generated• first-silicon success• other: simple / complex clocking, …• developing quality normalization model within MARCO

GSRC; VSIA, Numetrics, others pursuing similar goals

• Design quality: gathering data

Backup:MPU Analyses

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Performance Efficiency of Microarchitectures (Pollack’s Rule)

Area(Lead / Compaction)

Performance(Lead / Compaction)

1.5 1 0.7 0.5 0.35 0.18Technology Generation

Growth (X)

Note: Performance measured using SpecINT and SpecFP

In the same technology: • New microarchitecture has 2-3X die area of the last microarchitecture• Provides 1.4-1.7X performance of the last microarchitecture

“We are on the Wrong Side of a Square Law”Intel: P. Gelsinger talk ISSCC-2001

SPECint95

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Dec-83 Dec-86 Dec-89 Dec-92 Dec-95 Dec-98

8038680486PentiumPentium II

Expon.

MPU Clock Freq Doubles Each Generation…MPU Clock Freq Doubles Each Generation…

Intel: Borkar/Parkhurst

10.00

100.00

Dec-83 Dec-86 Dec-89 Dec-92 Dec-95 Dec-98

8038680486PentiumPentium II

Expon.

……But 1.4x of This is From Shorter PipelinesBut 1.4x of This is From Shorter Pipelines

Intel: Borkar/Parkhurst

……which can’t get shorter foreverwhich can’t get shorter forever

MPU Futures (1)• Drivers: power, I/O bandwidth, yield, ...• Multiple small cores per die, more memory hierarchy on board

– core can be reused across multiple apps/configs– replication redundancy, power savings (lower freq, Vdd while maintaining

throughput); better use of area than memory; avoid overhead of time-mplexing– IBM Power4 (2 CPU + L2); IBM S390 (14 MPU, 16MB L2 (8 chips) on 1 MCM

(31 chips, 1000W, 1.4B xtors, 4224 pins))– Processor-in-Memory (PIM): O(10M) xtors logic per core– 0.5Gb eDRAM L3 by 2005– high memory content gives better control of leakage, total chip power

• I/O bandwidth becomes a major differentiator– double-clocking, phase-pipelining in parallel-serial data conversion is hitting the

6-8 FO4 limit (i.e., cannot even make a clock pulse in < 6-8 FO4 delays)– I/O count may stay same or decrease due to integration– roughly constant die size (200-350 mm2) also limits I/O count

• Evolutionary microarchitecture changes– superpipelining (for freq), superscalar (beyond 4-way) both run out of steam– more multithreading support for parallel processing– more complex hardwired functions (networking, graphics, comm, security, ...)

(megatrend: shift of flexibility-efficiency tradeoff point away from GPP)

MPU Futures (2)• Circuit design

– ECC for single-event upset (soft errors)– pass gates are on the way out due to low Vt– more redundancy to compensate for yield loss– density models are impacted

• Clocking and power– Reasonable “need”: 1V supplies, 10-50W total power both flat– Power savings from SOI (5% or 25%), multi-Vth (10%), multi-Vdd (30-50%),

min-energy sizing under throughput constraints (25%), parallelism … • Note: combined use of multi-Vth, multi-Vdd potentially saves 2-4x power !

– multiple clock domains, grids; more gating/scheduling– adaptive voltage and frequency scaling– frequency: +1 GHz/year ... but product focus shifts to system throughput

• Bifurcation of MPU requirements– smart interface remedial processing (SIRP): basic computing and power

efficiency, SOC integration of RF, M/S, digital (wireless mobile multimedia)– centralized computing server: high-performance computing (traditional MPU)

Backup:Power-Constrained Logic-Memory

Balance Analyses

Memory/Logic Power Study SetupMemory/Logic Power Study Setup

• Motivation: Is current ITRS MPU model consistent with power realities? Does it drive the right set of needs?

• Ptotal = Plogic + Pmemory = constant (say, 50W or 100W)• Plogic composed of dynamic and static power, calculated as densities• Pmemory = 0.1*Pdensity_dynamic

– power density in memories is around 1/10 th that of logic

• Logic power density (dynamic) determined using active capacitance density (Borkar, Micro99)– dynamic power density Pdensity_dynamic = Cactive * Vdd

2 * fclock

– fclock uses new fixed-FO4 INV delay model (linear, not superlinear, with scale factor)

– Cactive = 0.25nF/mm2 at 180nm– increases with scale factor (~1.43X in theory; 1.30X historically)

Memory/Logic Power Study SetupMemory/Logic Power Study Setup

• Static power model considers dual Vth values– 90% of logic gates use high-Vth with Ioff from PIDS Table 28a/b

– 10% of logic gates use low-Vth with Ioff = 10X Ioff from PIDS Table 28a/b (90/10 split is from IBM and other existing dual-Vth MPUs)

– Operating temp (80-100C) Ioff is 10X of Table 28a/b (room temp)

• Width of each gate determined from IBM SA-27E library– 150nm technology; 2-input NAND = basic cell– performance level E: smallest footprint, next to fastest

implementation W of each device ~ 4um

– Weff (effective leakage width) for each gate = 4um

– 0.8*Weff*Ioff (per um) = Ileak / gate (0.8 comes from avg leakage over input patterns)

Memory/Logic Study SetupMemory/Logic Study Setup

• Calculate densities, then find allowable logic component (percent of total area) to achieve constant power (or power density)– Amemory + Alogic = Achip

– recall that Achip is now flat

• Constant power and constant power density scenarios same until 65nm node (because chip area flat until then)

Power as a Constraint: ImplicationsPower as a Constraint: Implications

Using same constraints, calculate #MPU cores (12Mt/core) and Mbytes SRAM allowable (again, anomaly at 32nm due to constant Vdd)

Backup:Design DOF’s for Power Reduction

Example Analysis: Contributing Example Analysis: Contributing Factors to “ITRS Power Contradiction”Factors to “ITRS Power Contradiction”

• Factors defined by manufacturing technology capabilities• Technology Node, MPU Gate Length, Cap_Gate, Tox, Gate Dielectric

Constant, …

• Factors that can be tuned by designers, design tools• Chip area, % of chip area dedicated to logic, Vdd, Ion, Vth, Weff/xtor,

% of gates with high Vth, …

• Sensitivities (effect that each factor has on total power)• Greatest effects are from tuning % of chip area dedicated to logic, %

of gates with high Vth• Some factors have more effect today, less in the future (e.g., Total

Capacitance Density, Ion)• Some factors have less impact today, more in the future (e.g., high-

Vth gate ratio, Weff/xtor)

Backup:Interactions with Key Other TWGs

Device Roadmap ChangesDevice Roadmap Changes

• Cf. Process Integration, Devices and Structures (PIDS) Chapter• CV/I device delay metric: historically decreases by 17%/year

– Since frequency improvement from shorter pipelines no longer available, perhaps we do need to keep scaling CV/I …

– Bottom line: PIDS is running up against limits of planar CMOS, and is shifting at least some of the pain to “design/architecture improvements”

• Continuing CV/I trend necessitates huge growth in Ioff

• Subthreshold Ioff at room temperature increases from 0.01 uA/um in 2001 to 10 uA/um at end of ITRS (22nm node)

• Ioff increases by at least order of magnitude at ~100 deg C operating temps • Static power becomes a huge problem: multi-Vt, multi-Vdd, substrate biasing, constant-throughput

power minimization, etc. must be coherently and simultaneously applied/optimized by automatic tools

• Also necessitates aggressive reduction in tox

• Physical tox thickness hovers at < 1.4nm (down to 1.0nm) starting in 2001, even assuming arrival of high-k gate dielectrics starting in 2004

• Implies huge variability mitigation challenges for Design Technology

Assembly/Packaging Roadmap ChangesAssembly/Packaging Roadmap Changes• MPU pad counts (Tables 3a/3b of 2000 ITRS ORTC Chap.) flat from 2001-

2005, while chip current draw increases 64%• Effective bump pitch roughly constant at 350mm throughout roadmap

– Bump/pad counts scale with chip area only, do not increase with technology demands (IR drop, L*di/dt)

metal resources needed to control <10% IR drop skyrocket since Ichip and wiring resistance increase challenge for Design Technology

– Later technologies (30-40nm) also have too few bumps to carry maximum current draw (e.g., 1250 V dd pads at 30nm with bump pitch of 250mm can each carry 150mA 187.5A max capability but Ichip/Vdd > 300A

• A&P Rationale: cost control (puts pain onto Design)• Design Rationalization: must introduce power constraints

– ITRS2001 will have strong power-constrained focus• Cost of liquid cooling, refrigeration, etc. impractical anyway• 30-50 W/cm2 limit for forced-air cooling with fins• MPU power dissipation capped at 150W for entire ITRS; MPU chip area held constant (more area

can’t be used well within 150W power budget)• Design DOFs for Power Reduction: see Backup Slides

Backup:Roadmap Acceleration Context

About This PresentationAbout This Presentation

• ITRS = International Technology Roadmap for Semiconductors (“The Roadmap”)– website: http://www.itrs.net (all ITRS-2001 work in progress)– login: 2001 itrs password: Timing

• Goal = highlight issues that can affect EDA– Where possible, infer necessary areas for R&D attention– Not all news in the ITRS will be covered

• Provide reusable “technical collateral” and “backstops”– Correct roadmap dates, technology nodes, etc.– Correct interpretation of models underlying roadmap evolution– Identification of drivers for EDA

Roadmap Acceleration Since 2000Roadmap Acceleration Since 2000

• Cf. Overall Roadmap Technology Characteristics (ORTCs)• Major accelerations continue

– Next slide shows “pull-in” of red and blue lines– E.g., 90nm node is in 2004, with physical gate length at 45nm

• MPU/ASIC half-pitch were separate, now unified – ASIC is at the same process node as MPU

• 2-year cycles b/w MPU/ASIC generations through 2004– New Generation = 0.7x multiplier of half-pitch or minimum feature

size, which generally allows 2x the transistors on the same size die– “Normal” pace = 3-year cycle

• MPU/ASIC half-pitch converges w/DRAM half-pitch in 2004– Previous ITRS: convergence predicted for 2015– Extremely aggressive scaling for density, cost improvement and

competitive positioning

I TRS 2001 Renewal - Work in Progress - Do Not Publish

6

ITRS Roadmap Acceleration Continues...

1998/1999 DRAM Half-Pitch

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MPU/ASIC Gate “In Resist” 1999 ITRS

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Scenario 2.0/DRAM 3.7/MPU

(2-yr cycle M/ A HP & G.L. <2005; 3yr >2005)

Sc 3.7 MPU/ASIC Half- Pitch (1- year Lag Thru 2002, then equal to DRAM after 2004)

“Most Aggressive” Sc 3.7 = 2- yr<’05; 3- yr >’05: MPU Printed (PrGL) & Physical (PhGL) Gate Length cycle; (ASIC/Lo Power Pr/PhGL 2- year delay from MPU Pr/PhGL)

DRAM Sc 2.0 = 3- yr cycle after 2001

2- Year Node Cycle 1995- 2001

Slide courtesy of A. Allan (Intel Corp.)

Backup:(Private) Design ITWG Themes

Big PictureBig Picture• ITRS takes Moore’s Law as a constraint

• Problem: We signed up for the “wrong” Moore’s Law– 2x frequency, 2x xtors,bits every node power, utility contradictions

– Each increment of performance is more and more costly

• Compounding problems– no architecture awareness (2x memory, 2x logic xtors in lock-step)

– no application awareness (e.g., low-power networked-embedded SOC)

– planar CMOS-centric (no DGFET, FinFET in requirements)

– uneven acknowledgment of cost (mask NRE, design cost, cost of technology development, manufacturing cost, …)

• New in 2001: Can Design solve it? Can Designers help?– PIDS : 17%/year improvement in CV/I metric punt Ioff, Rds, …

– A&P : bump pitch improves < chip area punt IR drop, power

– Interconnect : what total variability can Designers tolerate?

2001: Design Technology Better Integrated 2001: Design Technology Better Integrated With Other Supporting TechnologiesWith Other Supporting Technologies

• Problem: Design has always been “metric-free”– Metric “red brick wall” requirement for R&D investment

• Goal 1: show red bricks in Design Technology• Goal 2: shift red bricks from other supporting technologies

– e.g., lithography CD variability requirement solved by new Design techniques that can better handle variability

– e.g., mask data volume requirement solved by Design/Mfg interfaces and flows that pass functional requirements, verification knowledge to mask writing and inspection

– e.g., Simplex “X initiative” as much impact as copper ?

• But..– Need metrics of design cost, design quality– Need serious validation/participation from EDA, system, ASIC

companies

Need to Beef Up…Need to Beef Up…

• Test roadmap discussion is missing• Cost of test will soon exceed cost of manufacturing

• At-speed test stresses tester technology

• How solid is treatment of BIST, analog test, SOC test, etc.?

• Cost (big hole in ITRS)• Manufacturing cost, NRE cost (design, mask, …), technology development

cost (who should solve a given red brick wall?)

• Key challenges for EDA (with respect to ITRS)• Circuit/layout optimizations in the face of manufacturing variability

• System cost-driven design technology

• Holistic analysis, management of power (both dynamic and static)

• Circuit- and methodology-level IP: global signaling and synchronization, off-chip IO; power delivery and management

• Metrics, needs roadmap for quality/cost of design and design process

• Verification and test

• Software