iTOP readout firmware developmentidlab/taskAndSchedule/local_DAQ/PN… · Task Code Status Testing Status Comments Back-End Data-Link Partially Complete In Process Tested stand-alone,

iTOP readout firmwarefirmware development

Not shown: Joshua Sopher (firmware)Lili Zhang (DSP coding)Lili Zhang (DSP coding)

PNNL: David AsnerDavid Asner, Mitchell Myjak, Scott Morris, L W d

1K. Nishimura and G. Varner 25-MAR-2011 l-DAQ meetingLynn Wood

Overview• Status of various components• Status of various components

• Immediate deadline cosmic test in JapanE ti l t i t CERN b t t• Essential gate prior to CERN beam test

T d ’ f• Today’s focus:• ASICs: BLAB3A or IRS2+amps

P th 128 h l d t d l• Progress on the 128-channel readout module

Fi d l t i• Firmware development issues

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iTOP Readout Overview64 DAQ fiber

transceivers

8k channels

32 FINESSE8 COPPER

1k 8-channel waveform ASICs

64 SRM64 SRM

Precision timing requires 64 channels high-precision clock distribution (<~ 10ps)

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distribution (<~ 10ps) Approximately 30m runs

Major milestone:1/16 system test

Third generation waveform

sampling ASIC p g

Clock jitter cleaners

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Current incarnation of Subdetector Readout Module (iTOP)Subdetector Readout Module (iTOP)

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A very crowded location!8k vs. 14k (CDC channels) << 10% of space!

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BLAB3 Specifications32768 samples/chan (>5us trig latency)32768 samples/chan (>5us trig latency)

8 channels/BLAB3 ASIC8 Trigger channels9 bits resolution (12[10] bits logging)~9 bits resolution (12[10]-bits logging)

64 samples convert window (~16ns)4 GSa/s1 word (RAM) chan, sample readout

1+n*0.02 us to read n samples (of same 64)30 kHz sustained readout (multibuffer)( )

• Time alignment critical– Synchronize sampling to accelerator RF clockSy c o e sa p g to acce e ato c oc

– >5us a must for trigger, since single photon rates high

• Needs Gain!

BLAB3/IRS (amp/no-amp)( p p)

5.82mm

7 62mm7.62mm

8x RF inputs(die upside down)

32k storage cells per channel(512 f 64)(512 groups of 64)

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BLAB3/IRS Single Channel 9

• Sampling: 128 (2x 64 separate transfer lanesp

Recording in one set 64, transferring other (“ping-pong”)

• Storage: 64 x 512 (512 = 8 * 64)

Wilkinson (32x2): • Wilkinson (32x2): 64 conv/channel

Sampling speed

Sampling Simulation with full parasitic Extraction

4.000

4.500

5.000

Extracted

2.000

2.500

3.000

3.500

Sam

plin

g R

ate

[GSa

/s]

0.000

0.500

1.000

1.500

0 0.5 1 1.5 2 2.5

RCObias [V]

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IRS2 DC Linearity Calibration

ARA Digitizer - 12-MAR-2011 11

IRS2 Noise Measurement

<1mV<1mV

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Measurement via RF sine

Analog BW~1GHz

BLAB3A testing (carrier board)

23mm x 50mm

Plan to submit soon BLAB3A

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Should work mechanically, if can really fit components…

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mechanical mockup

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SCROD block diagram

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SCROD Fabricated

Rest of board stack needed: Firmware!!

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Beam test: a 1/16 system test

Third generation waveform

sampling ASIC p g

Clock jitter cleaners

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Beamtest back-end (cPCI_DSP)

For freference

when di idiscussing issues b lbelow

cPCI Interface

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(PCI bus)

Front-End Board Stack Hardware Status21

Board Name Design* Fab & Assembly

Testing** Comments

SCROD Complete ~Complete Not started 2x SCROD assembled, in-hand.Si l f ti lit t t b i t kSimple functionality tests begin next week.Full testing requires complete board stack (except HV).

InterConnect ~Complete Not started Not started Fabrication waiting on ASIC carrier card design (in case any changes).

ASIC Carrier Not started Not started Not started Design waiting on ASIC daughter cards

BLAB3A In Process Not started Not started Focusing on design now.Daughter

IRS2 Daughter Not started Not started Not started Only necessary if problems w/ BLAB3A.

HV Not started Not started Not started Waiting on someone with time to design.

Personnel: • Design: primarily Louis Ridley

• Supported by Gary Varner, Matt Andrew, Kurtis NishimuraF b & A bl i il M tt A d

*Designs are NOT the same as final Belle II system.

• Fab & Assembly: primarily Matt Andrew• Testing: primarily Kurtis Nishimura

• Supported by Matt Andrew, Gary Varner

**”Testing” here means checking board connectivity / power / etc.

Front-End FirmwareFront End Firmware DevelopmentTask Code Status Testing

StatusComments

General ASIC Control

Partially Complete

Partially Complete

BLAB3A/IRS interface, timing.Currently in debugging/testing using IRS_eval.Will need to be adapted to new board stack.

Feedback loops Rewrite? Restart? Feeds back to maintain sampling rate / ADCFeedback loops Rewrite? Restart? Feeds back to maintain sampling rate / ADC conversion rate, etc.Old version available, but needs rework.Must be adapted to new DACs.Pending front-end design completion

DAC control Not started Not started

Pending front end design completion.

Front-end data link Not started Not started Data links available from other projects / Belle2Link, need to be adapted to board stack.(Trigger not strictly necessary for beam test.)Front-end trigger

linkNot started Not started

Trigger time encoding

Not started Not started (Trigger not strictly necessary for beam test.)

Personnel: P i K ti Ni hi J h S h ( til• Primary: Kurtis Nishimura, Joshua Sopher (until now)

• Support: Gary Varner 22

Back-end / Auxiliary Boards23

• Not many changes to back-end hard arehardware.

• Sufficient quantities already in h dhand. Primarily testing / firmware / DSP / software work remains.

Back-End / Auxiliary Hardware Statusy

Board Name Design Fab & Testing* CommentsAssembly

DSP_cPCI Complete Complete Partially Complete

DSP programming still needs testing (coupled with firmware).

TRIG FIN C l C l C lTRIG_FIN Complete Complete Complete

FIN_cPCI Complete Complete Complete Simple board for powering FINESSEmodules without COPPER.

CLK FIN C l t C l t P ti ll Cl k di t ib ti f lCLK_FIN Complete Complete Partially Complete

Clock distribution successful.FTSW module could fill in here.

*”Testing” here means checking board connectivity /

Personnel: • Testing: Matt Andrew, Kurtis Nishimura

board connectivity / power / etc.

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Back-End / Auxiliary Firmware/DSP/Software StatusTask Code Status Testing Status Comments

Back-End Data-Link Partially Complete In Process Tested stand-alone, not integrated w/ other firmware.

Back-End Fiber / PCI Bridge

Not Started Not Started Interface between fiber link FPGA and PCI FPGA.g

DSP Interface Partially Complete In Process (Not strictly necessary for beam test.)

DSP Algorithms Partially Complete In Process (Not strictly necessary for beam test.)

PCI Interface (Firmware) Partially Complete In Process Stable version available @ 3 MB/s WorkingPCI Interface (Firmware) Partially Complete In Process Stable version available @ 3 MB/s. Working toward DMA version (60+MB/s).

PCI Kernel Driver Partially Complete In Process

PCI Software ~Not Started ~Not Started Only test software exists to check driver/firmware statusdriver/firmware status.

Trigger Data-Link Complete Complete Fairly mature.

Trigger Combiner / Logic ~Complete ~Complete Fairly mature, may need small changes for beam test.

CAMAC Interface ~Not Started Not Started No code yet… can adapt from other projects.

Personnel: • DSP code: Lili Zhang• DSP interface: Matt Andrew, Serge Negrashov• PCI interface / driver: Xin Gao, Serge Negrashov, Andrew Wong• PCI software : Serge Negrashov, Andrew Wong• Trigger: Xin Gao

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Necessary Hardware (Beam Test)Hardware Needed In-Hand Comment

Front-end board stack 4 <1 8 SL10 / stackFront end board stack 4 1 8 SL10 / stack1 data fiber / stack1 trig fiber / stack

CLK_FIN 1 2 Or FTSWFIN_cPCI 1 1TRIG FIN 1 2_DSP_cPCI 2 4 1 for data

1 for triggercPCI Crate 1 1cPCI Crate 1 1CAMAC Crate Controller

1(?) 1

CAMAC Crate 1 0 Assuming NagoyaCAMAC Crate 1 0 Assuming Nagoya brings crate & modules. 26

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Summary/Open issuesM h fi k d d• Much firmware work needed• Help from PNNL; write system documentation

• Hardware – confirm items previous slideC l A 3A i i b d• Complete BLAB3A carrier, routing boards

• Interface board done, submit 3x designs soon

• Confirm performance of integrated module, i l di i h MCP PMTincluding with MCP-PMTs

28• Development manpower resource limited (where PNNL can help)

Back-up slides

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Photo-detector: Hamamatsu SL-10• Micro channel Plate:• Micro-channel Plate:

– Operates in 1.5T B-field– <50ps single photon timing

• Multi-pixel (4x4 anode pads)• Enhanced Lifetime (Al protection layer)

Interesting mechanical challenges• Interesting mechanical challenges (PMT case at HV)

30Approximately 1” x 1”

BLAB3 status and scheduleSpecification BLAB3 BLAB3A BLAB3B FINAL

A l 175 MH 400MH 500MH ? 400AnalogBandwidth

175 MHz 400MHz 500MHz? 400-600MHz

Gain [50 ref] 34-36x 60x 100x ? SNR>=50

Sampling speed [Giga-sample/s]

3.6 3.8 4.0 4.0

Usable li d

~1.4 3.8 4.0 >= 3sampling speedInternal DACs no no yes yes

Design Sept. Sept. January Autumncompletion 2009 2010 2011 2011Delivery Jan. 2010 Nov. 2010 May 2011 Winter 2011

quantity 120 240* 120? 1000q y

* = not for Belle2, but will learn from design

SL-10 Timing PerformanceNagoya Hawai’iNagoya Hawai i

σ ~ 38.37

N f i di i i CAMAC• Nagoya = constant fraction discriminator + CAMAC ADC/TDC H i’i f li + f t t ti

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• Hawai’i = waveform sampling + feature extraction

High speed Waveform sampling“oscilloscope on a chip”osc oscope o a c p

• Comparable performance to best

CH1

CFD + HPTDC• MUCH lower power, no

d f h bl CH2need for huge cable plant!

• Using full samples

CH2

Using full samples reduces the impact of noise

6 4 RMS• Photodetector limited 6.4 psRMS

NIM A602 (2009) 43833

Advanced Detector Research award

NIM A602 (2009) 438

Belle2 barrel PID upgrade: iTOP

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references and further inforeferences and further info

references: references: http://b2comp.kek.jp/~twiki/pub/Organization/B2

TDR/B2TDR pdfTDR/B2TDR.pdf http://www.phys.hawaii.edu/~idlab/taskAndSched

ule/ICBMS.pdfule/ICBMS.pdf latest info:

http://idlab phys hawaii edu/pcb designs/scrod http://idlab.phys.hawaii.edu/pcb-designs/scrod

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brainstorming SCRODbrainstorming SCROD

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