Issues in design_of_code_generator

Presented by,

M.Selva Vinitha

B.E/CSE

M.Kumarasamy college of engineering

Karur.

Code generator

Final phase of compiler design

Optimized intermediate code is provided as input

It generates target code

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Code generation and Instruction Selection

4

Symboltable

input output

Frontend

IntermediateCode

generatorCode

generator

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Contd…

output code must be correct

output code must be of high quality

code generator should run efficiently

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Pre-requisites Instruction set of target machine.

Instruction addressing modes.

No. of registers.

Configuration of ALU

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Issues in the design of a code

generator

Input to the code generator

Memory management

Target programs

Instruction selection

Register allocation

Evaluation order

Approaches to code generation

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Input to the code generator The intermediate representation of the source program

produced by the front end

Several choices for the intermediate language

Linear - postfix nottion

3 address - quadruples

Virtual machie - stack machine code

Graphical - syntax tree &dags

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Memory management

Mapping names in the source program to addresses of data

objects in run-time memory

Done by the front end and the code generator.

A name in a three- address statement refers to a symbol-

table entry for the name.

A relative address can be determined

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Target programs

Absolute machine language

Relocatable machine language

Assembly language

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Contd..

Absolute machine language:

Produce an absolute machine language program

can be placed in a fixed location in memory and

immediately executed.

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Contd..Relocatable machine language:

Producing a relocatable machine language program

subprograms to be compiled separately.

relocatable object modules can be linked together and loaded for execution by a linking loader.

must provide explicit relocation information to the loader, to link the separately compiled program segments.

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Contd…Assembly language:

Producing an assembly language program

makes the process of code generation easier

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Instruction selection

The factors to be considered during instruction selection are:

The uniformity and completeness of the instruction set.

Instruction speed and machine idioms.

Size of the instruction set.

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Contd…Eg., for the following address code is:

a := b + cd := a + e

inefficient assembly code is:

MOV b, R0 R0 ← b

ADD c, R0 R0 ← c + R0

MOV R0, a a ← R0

MOV a, R0 R0 ← a

ADD e, R0 R0 ← e + R0

MOV R0 , d d ← R0

Here the fourth statement is redundant, and so is the third statement if ,

'a' is not subsequently used.

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Register allocation

• Instructions with register operands are usually shorter and

faster

• Efficient utilization of registers is important in

generating good code.

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Contd..Register allocation phase:

• Select the set of variables that will reside in registers

Register assignment phase:

• Pick the specific register that a variable will reside in.

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Evaluation order The order in which computations are performed

Affect the efficiency of the target code.

Some computation orders require fewer registers to hold

intermediate results

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Approaches to code generation Most important criteria for code generator is that it

produces correct code

Correctness takes on special signification

It contains a straightforward code generation algorithm

The output of such code generator can be improved by

peephole optimization technique

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Conclusion

Output of code generator phase is dependent on:

Target language

Operating system

Memory management system

Instruction selection

Register allocation

Evaluation order

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