380 • 2010 IEEE International Solid-State Circuits Conference ISSCC 2010 / SESSION 21 / SUCCESSIVE-APPROXIMATION ADCs / 21.2 21.2 A 12b 22.5/45MS/s 3.0mW 0.059mm 2 CMOS SAR ADC Achieving Over 90dB SFDR Wenbo Liu, Pingli Huang, Yun Chiu University of Illinois at Urbana-Champaign, Urbana, IL CMOS technology scaling has opened a pathway to high-performance analog- to-digital conversion in the nanometer regime, where switching is preferred over amplifying. Successive-approximation-register (SAR) is one of the conversion architectures that rely on the high switching speed of process technology, and is thus distinctively known for its superior energy efficiency, small chip area, and good digital compatibility. When properly implemented, a SAR ADC also bene- fits from a potential rail-to-rail input swing, 100% capacitance utilization during input sampling (thus low kT/C noise), and insensitivity to comparator offsets during the conversion process. The linearity-limiting factors for SAR ADC are capacitor mismatch, sampling switch non-idealities, as well as the reference voltage settling issue due to the high internal switching speed of the DAC. In this work, a sub-radix-2 SAR ADC is presented, which employs a perturbation-based digital background calibration scheme and a dynamic-threshold-comparison (DTC) technique to overcome some of these performance-limiting factors. The perturbation-based calibration scheme and the timing diagram of the ADC utilizing a radix-1.86 conversion architecture [1] are depicted in Fig. 21.2.1, wherein 14 raw bits are resolved with a net 12bit resolution. One complete con- version process consists of a 6-clock-cycle sampling phase and two 14-clock- cycle conversion phases, in which a single SAR quantizer performs the same digitization twice, perturbed by two added offsets, +Δ a and –Δ a , and resolves to two 14bit non-binary codes, D + and D – , respectively. These codes are subse- quently converted to binary ones, shown as d + and d – in Fig. 21.2.1, by a weight- ed sum of the individual bits. If the conversion process is ideal, the difference e between d + and d – less 2Δ d (the digital version of Δ a ) must be zero. In other words, a nonzero e will provide information to infer the unknown weighting vec- tor W and Δ d ; and this idea leads to the adaptive learning algorithm shown in Fig. 21.2.1 to calibrate the SAR ADC in which e is gradually forced to zero. After the learning procedure converges, the mean of d + and d – will yield the correct digi- tal output with the effect of Δ a cancelled. A side benefit of the double conversion is that the quantization noise and comparator noise both get reduced by 3dB, resulting in an improved SNR. If capacitor mismatch is the dominant error source, this scheme also offers an opportunity to double the conversion speed by disabling the calibration after the bit weights are properly learned. An extra 6- clock-cycle sampling phase is reserved between the two conversion phases to allow for this option in the prototype. The perturbation-based calibration shares a similar spirit with the “split-ADC” calibration reported in [2] and [3], in that two digital representations of a single analog sample obtained through two distinctive decision trajectories are equal if and only if the bit weights, or radixes, are precisely known, which implies a suc- cessful calibration. However, the perturbation-based method, involving a single ADC, requires half the number of comparators and much reduced circuit/layout complexity. In addition, the single front-end sampling also circumvents the clock skew and bandwidth mismatch problems between the two parallel conversion paths of the “split-ADC” architecture. The diagram of the SAR ADC is shown in Fig. 21.2.2. The main sub-radix-2 capacitive DAC is implemented by a compact MOM capacitor array, and the total sampling capacitance is scaled down to exactly the kT/C limit for 12bit. Thus, the chip area, reference voltage bouncing, and DAC dynamic power consumption are all minimized. The bottom- and top-plate sampling switches are both boot- strapped in order to achieve 12bit linearity and high tracking bandwidth for a rail- to-rail input swing. The perturbation signal Δ a is injected by an additional small capacitor C Δ shown in Fig. 21.2.2. Exploiting the built-in redundancy of the sub-radix-2 architecture, a DTC tech- nique is applied to tolerate any conversion errors due to DAC incomplete settling and/or coupled noise [1]. Meanwhile, it significantly relaxes the settling time requirement for the reference voltages, especially during the first few conversion steps when the MSB capacitors are switching between +V R and –V R (which are actually VDDA and GNDA in this work, respectively). The DTC technique can the- oretically allow a reference settling error of 154, 83, …, 2, … LSBs for the MSB, MSB-1, …, MSB-7, … conversion steps, respectively. As the switching distur- bance on the reference lines decreases progressively toward the LSB step, the technique was only applied to the first 8 conversion steps. The prototype SAR ADC also utilizes an asynchronous clocking scheme illustrat- ed in Fig. 21.2.2. In each conversion step, when CLK is low, the DAC outputs a new analog value according to the previous bit decision; meanwhile, the differ- ential outputs of the comparator are both reset to ground. The comparator starts to regenerate at the CLK rising edge, and once one of the comparator outputs reaches high, the NOR gate signals the SAR logic to latch the valid comparator output. Although efficient, asynchronous timing is known to be vulnerable to comparator metastability errors. In this work, the CLK falling edge will force the SAR logic to latch 0 when a metastability error occurs and the NOR gate fails to signal. The following conversion steps then continue on the lower side of the (redundant) transfer curve, as if the metastability error never occurred. This technique is applied to all conversion steps except that for the LSB. The comparator shown in Fig. 21.2.3 consists of a two-stage preamp and a latch. Since the input-referred noise of the comparator is an essential part of the over- all ADC noise budget, the preamp is designed to provide 30dB gain to attenuate the latch noise; Also, PMOS input transistors are used in the first-stage preamp to minimize 1/f noise and limit the noise bandwidth. The latch design is similar to that of [4]. The prototype SAR ADC was fabricated in a 0.13μm CMOS technology. The die photo is shown in Fig. 21.2.7. The core area is 0.059mm 2 , which is, to our best knowledge, the smallest 12bit ADC reported. With the background calibration enabled, the ADC consumes 2.8mW from a 1.2V power supply at 22.5MS/s. The digital calibration logic was implemented in software, with estimated power and area of 0.2mW and 0.01mm 2 , respectively, by SPICE simulation. Fig. 21.2.4 shows the ADC output spectra before and after calibration for a full-scale 1.0281MHz input. When Δ a is set to 25LSB, the LMS loop learns the optimal bit weights in 21000 iterations and completes the calibration. In steady state, the SNDR, SFDR, THD are improved from 60.15, 66.43, -61.68dB to 70.72, 94.63, -89.10dB, respectively. The left plot in Fig. 21.2.5 illustrates the dynamic performance of the ADC at 22.5MS/s with background calibration enabled. The peak SNDR is 71.12dB. The SFDR roll-off after 10MHz is due to the limited band- width of the sample-and-hold circuit. The right plot in Fig. 21.2.5 presents the dynamic performance of the ADC at 45MS/s with frozen bit weights learned in the background mode. The peak SNDR is 68.36dB. The approximate 2.5dB high- er SNDR obtained in the background mode is attributed to the noise averaging effect of the double conversion. The effectiveness of the DTC technique was also experimentally verified with the background calibration enabled. Fig. 21.2.6 indi- cates that the DTC technique effectively eliminates the ADC linearity degradation beyond 19MS/s due to reference bouncing. The measurement results are sum- marized in Fig. 21.2.6. Note that the reported analog power consumption includes the dynamic power dissipation of the reference voltages. The FoM of this SAR ADC is 45.6 and 31.4fJ/conversion-step at 22.5 and 45MS/s, respec- tively. Acknowledgements: We thank SMIC for chip fabrication and ITRI for testing support. References: [1] W. Liu et al., “A 600MS/s 30mW 0.13μm CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital Equalization,” ISSCC Dig. Tech. Papers, pp. 82–83, Feb. 2009. [2] J. McNeill, M. Coln, and B. Larivee, “A Split-ADC Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC,” ISSCC Dig. Tech. Papers, pp. 276–278, Feb. 2005. [3] J. Li and U.-K. Moon, “Background Calibration Techniques for Multistage Pipelined ADC’s with Digital Redundancy,” IEEE TCAS-II, vol. 50, pp. 531–538, Sep. 2003. [4] B. Goll and H. Zimmermann, “A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz,” ISSCC Dig. Tech. Papers, pp. 316–317, Feb. 2007. 978-1-4244-6034-2/10/$26.00 ©2010 IEEE