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S-A. Yu
ISSCC 2007 / SESSION 17 / ANALOG TECHNIQUES AND PLLs / 17.2
Offset frequency [MHz]
Phas
e no
ise
[dB
c/H
z]
Loop Filter(off-chip)
TCXO(off-chip)
VCO
50Driver
DataClock
LE
16MHz
0.5V
1V
0V
VGD can be close to 2VDD
2VDD
VDD
Circuit node voltages exceed VDD
0V
2VDD
~0V time
Thick oxide VDD
Thin oxide VDD
Thin oxide VT
Technology node [nm]
[ITRS'04]
– – High Perf.– –Low Standby– –Low Power
0.5V
0V
VDD
½ VDD
0V
All circuit node voltages between VSS & VDD
0.25V
time
See Digest page 304
17.2 A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS
Columbia University, New York, NY
A 2.5GHz fractional-N synthesizer is realized in a digital 90nm CMOS technology. The RF dividers operate at 0.65V while the remainder ofthe PLL operates at 0.5V; no special devices or voltage boosting is used to achieve the 0.5V operation. The synthesizable range covers 2.4to 2.6GHz with a phase noise of -55dBc/Hz in band and -120dBc/Hz at a 3MHz offset. The synthesizer dissipates 7mW and occupies0.14mm2.