ISA context and x86 history Translation tools: C ...cs240/s16/slides/x86-basics.pdf · ISA First Year 8086 Intel 8086 1978 First 16-bit processor. Basis for IBM PC & DOS 1MB address

x86basicsISAcontextandx86historyTranslationtools:C-->assembly<-->machinecode

x86Basics:RegistersDatamovement instructionsMemoryaddressingmodesArithmetic instructions

1

Devices(transistors,etc.)

Solid-StatePhysics

Hardware

DigitalLogic

Microarchitecture

InstructionSetArchitecture

OperatingSystem

ProgrammingLanguage

Compiler/Interpreter

Program,ApplicationSoftware

pastfewweeks

nextfewweeks

Microarchitecture(Implementation ofISA)

ALURegisters MemoryInstructionFetch andDecode

Computer

Computer

InstructionSetArchitecture(HW/SWInterface)memory

InstructionLogic

Registers

processor

EncodedInstructions

Data

Instructions• Names,Encodings• Effects• Arguments,Results

Localstorage• Names,Size• Howmany Largestorage

• Addresses, Locations

abriefhistoryofx86

6

ISA First Year8086 Intel8086 1978

First16-bitprocessor. BasisforIBMPC&DOS1MBaddress space

IA32 Intel386 1985First32-bitISA.Flataddressing, improved OSsupport

x86-64 AMDOpteron 2003*SlowAMD/Intel conversion, slowadoption.*Notactuallyx86-64untilfewyearslater.Mainstream onlyafter~10years.

16

32

64

WordSize

240now:

240soon:

2015:mostlaptops,desktops, servers.

CISC(vs.RISC)

TurningCintoMachineCode

8

CCodeint sum(int x, int y) {int t = x+y;return t;

}

GeneratedIA32AssemblyCode

sum:pushl %ebpmovl %esp,%ebpmovl 12(%ebp),%eaxaddl 8(%ebp),%eaxmovl %ebp,%esppopl %ebpret

code.s

code.c

gcc -O1 -S code.c

Human-readablelanguageclosetomachinecode.

compiler

01010101100010011110010110001011010001010000110000000011010001010000100010001001111011000101110111000011

code.o

assembler

ObjectCode

Linker:createfullexecutableResolvereferencesbetween objectfiles,libraries, (re)locatedata

Disassembledbyobjdump00401040 <_sum>:

0: 55 push %ebp1: 89 e5 mov %esp,%ebp3: 8b 45 0c mov 0xc(%ebp),%eax6: 03 45 08 add 0x8(%ebp),%eax9: 89 ec mov %ebp,%espb: 5d pop %ebpc: c3 ret

DisassemblingObjectCode(objdump)

12

01010101100010011110010110001011010001010000110000000011010001010000100010001001111011000101110111000011

objdump -d p

Disassembler

code.o

DisassembledbyGDB0x401040 <sum>: push %ebp0x401041 <sum+1>: mov %esp,%ebp0x401043 <sum+3>: mov 0xc(%ebp),%eax0x401046 <sum+6>: add 0x8(%ebp),%eax0x401049 <sum+9>: mov %ebp,%esp0x40104b <sum+11>: pop %ebp0x40104c <sum+12>: ret

DisassemblingObjectCode(gdb)

13

> gdb p(gdb) disassemble sum

(disassemblefunction)(gdb) x/13b sum

(examinethe13bytesstartingatsum)

Object0x401040:

0x550x890xe50x8b0x450x0c0x030x450x080x890xec0x5d0xc3

IntegerRegisters(IA32)

14

%eax

%ecx

%edx

%ebx

%esi

%edi

%esp special purpose

%ebp special purpose

generalp

urpo

se

accumulate

counter

data

base

source indexdestinationindexstack pointer

basepointer

Origin(mostlyobsolete)

32-bitswideSomehavespecial usesforparticular instructions

IntegerRegisters(historicalartifacts)

15

%eax

%ecx

%edx

%ebx

%esi

%edi

%esp

%ebp

%ax

%cx

%dx

%bx

%si

%di

%sp

%bp

%ah

%ch

%dh

%bh

%al

%cl

%dl

%bl

16-bitvirtualregisters(backwardscompatible)

generalp

urpo

se

accumulate

counter

data

base

source index

destinationindex

stack pointer

basepointer

high/lowbytesofold16-bitregisters

IA32:ThreeBasicKindsofInstructions1.Datamovement betweenmemoryandregister

Load datafrommemoryintoregister%reg =Mem[address]

Store register dataintomemoryMem[address] =%reg

2.Arithmetic/logic onregisterormemorydatac=a+b; z=x<<y; i =h&g;

3.ComparisonsandControlflow tochoosenextinstructionUnconditional jumpsto/fromproceduresConditionalbranches

18

Memoryisanarray[]ofbytes!

Datamovement instructionsmovx Source,Dest

x isoneof{b, w, l}givessizeofdata

movl Source,Dest:Move4-byte“longword”

movw Source,Dest:Move2-byte“word”

movb Source,Dest:Move1-byte“byte”

19

%eax

%ecx

%edx

%ebx

%esi

%edi

%esp

%ebp

historicalterms fromthe16-bitdaysnot thecurrentmachinewordsize

Datamovement instructionsmovl Source,Dest:

OperandTypes:Immediate: Literalinteger data

Examples:$0x400,$-533

Register:Oneof8integer registersExamples:%eax, %edx

Memory: 4consecutive bytesinmemory,ataddressheldbyregisterSimplestexample:(%eax)Variousother“addressmodes”

20

%eax

%ecx

%edx

%ebx

%esi

%edi

%esp

%ebp

movl OperandCombinations

21

movl

Imm

Reg

Mem

RegMem

RegMem

Reg

Source Dest CAnalog

movl $0x4,%eax

movl $-147,(%eax)

movl %eax,%edx

movl %eax,(%edx)

movl (%eax),%edx

var_a = 0x4;

*p_a = -147;

var_d = var_a;

*p_d = var_a;

var_d = *p_a;

Src,Dest

Cannotdomemory-memorytransferwithasingleinstruction.Howwouldyoudoit?

BasicMemoryAddressingModesIndirect (R) Mem[Reg[R]]

RegisterRspecifiesthememoryaddress

movl (%ecx),%eax

Displacement D(R) Mem[Reg[R]+D]RegisterRspecifiesamemoryaddress

(e.g. thestartofanobject)

ConstantdisplacementDspecifiestheoffsetfromthataddress(e.g.afieldintheobject)

movl 8(%ebp),%edx

22

UsingBasicAddressingModes

23

void swap(int *xp, int *yp){int t0 = *xp;int t1 = *yp;*xp = t1;*yp = t0;

}

swap:pushl %ebpmovl %esp,%ebppushl %ebx

movl 12(%ebp),%ecxmovl 8(%ebp),%edxmovl (%ecx),%eaxmovl (%edx),%ebxmovl %eax,(%edx)movl %ebx,(%ecx)

movl -4(%ebp),%ebxmovl %ebp,%esppopl %ebpret

Body

SetUp

Finish

Understanding Swap

24

void swap(int *xp, int *yp) {int t0 = *xp;int t1 = *yp;*xp = t1;*yp = t0;

}

movl 12(%ebp),%ecx # ecx = yp

movl 8(%ebp),%edx # edx = xp

movl (%ecx),%eax # eax = *yp (t1)

movl (%edx),%ebx # ebx = *xp (t0)movl %eax,(%edx) # *xp = eax

movl %ebx,(%ecx) # *yp = ebx

Stack(inmemory)

Register Value%ecx yp

%edx xp

%eax t1

%ebx t0

yp

xp

Returnaddr

Old%ebp %ebp0

4

8

12

Offset

•••

Old%ebx-4

register<->variablemapping

loweradd

resses

higheradd

resses

Understanding Swap

25

movl 12(%ebp),%ecx # ecx = yp

movl 8(%ebp),%edx # edx = xp

movl (%ecx),%eax # eax = *yp (t1)

movl (%edx),%ebx # ebx = *xp (t0)movl %eax,(%edx) # *xp = eax

movl %ebx,(%ecx) # *yp = ebx

0x120

0x124

Returnaddr

%ebp 0

4

8

12

Offset

-4

123

456

Address0x124

0x120

0x11c

0x118

0x114

0x110

0x10c

0x108

0x104

0x100

yp

xp

%eax

%edx

%ecx

%ebx

%esi

%edi

%esp

%ebp 0x104

loweradd

resses

higheradd

resses

ex

movl 12(%ebp),%ecx # ecx = ypmovl 8(%ebp),%edx # edx = xp

movl (%ecx),%eax # eax = *yp (t1)

movl (%edx),%ebx # ebx = *xp (t0)movl %eax,(%edx) # *xp = eax

movl %ebx,(%ecx) # *yp = ebx

Understanding Swap

26

0x120

0x124

Returnaddr

%ebp 0

4

8

12

Offset

-4

123

456

Address0x124

0x120

0x11c

0x118

0x114

0x110

0x10c

0x108

0x104

0x100

yp

xp

%eax

%edx

%ecx

%ebx

%esi

%edi

%esp

%ebp 0x104

0x1200x120

Understanding Swap

27

0x120

0x124

Returnaddr

%ebp 0

4

8

12

Offset

-4

123

456

Address0x124

0x120

0x11c

0x118

0x114

0x110

0x10c

0x108

0x104

0x100

yp

xp

%eax

%edx

%ecx

%ebx

%esi

%edi

%esp

%ebp

0x120

0x104movl 12(%ebp),%ecx # ecx = yp

movl 8(%ebp),%edx # edx = xpmovl (%ecx),%eax # eax = *yp (t1)

movl (%edx),%ebx # ebx = *xp (t0)movl %eax,(%edx) # *xp = eax

movl %ebx,(%ecx) # *yp = ebx

0x124

0x124

Understanding Swap

28

0x120

0x124

Returnaddr

%ebp 0

4

8

12

Offset

-4

123

456

Address0x124

0x120

0x11c

0x118

0x114

0x110

0x10c

0x108

0x104

0x100

yp

xp

%eax

%edx

%ecx

%ebx

%esi

%edi

%esp

%ebp

0x124

0x120

0x104movl 12(%ebp),%ecx # ecx = yp

movl 8(%ebp),%edx # edx = xp

movl (%ecx),%eax # eax = *yp (t1)movl (%edx),%ebx # ebx = *xp (t0)movl %eax,(%edx) # *xp = eax

movl %ebx,(%ecx) # *yp = ebx

456

456

Understanding Swap

29

0x120

0x124

Returnaddr

%ebp 0

4

8

12

Offset

-4

123

456

Address0x124

0x120

0x11c

0x118

0x114

0x110

0x10c

0x108

0x104

0x100

yp

xp

%eax

%edx

%ecx

%ebx

%esi

%edi

%esp

%ebp

456

0x124

0x120

0x104movl 12(%ebp),%ecx # ecx = yp

movl 8(%ebp),%edx # edx = xp

movl (%ecx),%eax # eax = *yp (t1)

movl (%edx),%ebx # ebx = *xp (t0)movl %eax,(%edx) # *xp = eax

movl %ebx,(%ecx) # *yp = ebx

123

123

456

Understanding Swap

30

0x120

0x124

Returnaddr

%ebp 0

4

8

12

Offset

-4

Address0x124

0x120

0x11c

0x118

0x114

0x110

0x10c

0x108

0x104

0x100

yp

xp

%eax

%edx

%ecx

%ebx

%esi

%edi

%esp

%ebp

456456

0x124

0x120

123

0x104movl 12(%ebp),%ecx # ecx = yp

movl 8(%ebp),%edx # edx = xp

movl (%ecx),%eax # eax = *yp (t1)

movl (%edx),%ebx # ebx = *xp (t0)movl %eax,(%edx) # *xp = eaxmovl %ebx,(%ecx) # *yp = ebx

456

123

Understanding Swap

31

0x120

0x124

Returnaddr

%ebp 0

4

8

12

Offset

-4

456Address0x124

0x120

0x11c

0x118

0x114

0x110

0x10c

0x108

0x104

0x100

yp

xp

%eax

%edx

%ecx

%ebx

%esi

%edi

%esp

%ebp

456

0x124

0x120

0x104movl 12(%ebp),%ecx # ecx = yp

movl 8(%ebp),%edx # edx = xp

movl (%ecx),%eax # eax = *yp (t1)

movl (%edx),%ebx # ebx = *xp (t0)movl %eax,(%edx) # *xp = eax

movl %ebx,(%ecx) # *yp = ebx

123

123

123

CompleteMemoryAddressingModesGeneralForm:

D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+D]D: Literal“displacement” value represented in1,2,or4bytesRb: Base register:AnyregisterRi: Index register:Anyexcept%esp; %ebp unlikelyS: Scale:1,2,4,or8(whythesenumbers?)

SpecialCases: canuseanycombinationofD,Rb,RiandS(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]] (S=1,D=0)D(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]+D] (S=1)(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]] (D=0)

37

AddressComputationExamples

%edx

%ecx

0xf000

0x100

AddressExpression AddressComputation Address

0x8(%edx)

(%edx,%ecx)

(%edx,%ecx,4)

0x80(,%edx,2)

38

(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]]D(,Ri,S) Mem[S*Reg[Ri]+D](Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]]D(Rb) Mem[Reg[Rb] +D]

Registercontents Addressingmodes

ex

leal Src,Dest loadeffectiveaddressSrc isaddressmodeexpressionSetDest toaddresscomputedbyexpressionExample: leal (%edx,%ecx,4), %eax

DOESNOTACCESSMEMORY

UsesComputingaddresses,e.g.,: translationofp = &x[i];Computingarithmeticexpressionsoftheformx+k*i

k=1,2,4,or8

39

!!!

ArithmeticOperationsTwo-operandinstructions:

Format Computationaddl Src,Dest Dest = Dest + Srcsubl Src,Dest Dest = Dest – Src argumentorder

imull Src,Dest Dest =Dest *Srcshll Src,Dest Dest =Dest <<Src a.k.a sallsarl Src,Dest Dest =Dest >>Src Arithmetic

shrl Src,Dest Dest =Dest >>Src Logicalxorl Src,Dest Dest =Dest ^Srcandl Src,Dest Dest =Dest &Src

orl Src,Dest Dest =Dest |Src

Nodistinctionbetweensignedandunsignedint (why?)exceptarithmeticvs.logicalshiftright

40

ArithmeticOperationsOne-operand(unary)instructions

incl Dest Dest = Dest + 1 incrementdecl Dest Dest = Dest – 1 decrement

negl Dest Dest = -Dest negatenotl Dest Dest = ~Dest bitwisecomplement

SeeCSAPP3.5.5formore:mull,cltd,idivl,divl

41

leal forarithmetic(IA32)arith:

pushl %ebpmovl %esp,%ebp

movl 8(%ebp),%eaxmovl 12(%ebp),%edxleal (%edx,%eax),%ecxleal (%edx,%edx,2),%edxsall $4,%edxaddl 16(%ebp),%ecxleal 4(%edx,%eax),%eaximull %ecx,%eax

movl %ebp,%esppopl %ebpret

Body

SetUp

Finish

42

int arith(int x,int y,int z){int t1 = x+y;int t2 = z+t1;int t3 = x+4;int t4 = y * 48; int t5 = t3 + t4;int rval = t2 * t5;return rval;

}

Understandingarith (IA32)

movl 8(%ebp),%eax # eax = xmovl 12(%ebp),%edx # edx = yleal (%edx,%eax),%ecx # ecx = x+y (t1)leal (%edx,%edx,2),%edx #sall $4,%edx #addl 16(%ebp),%ecx #leal 4(%edx,%eax),%eax #imull %ecx,%eax #

y

x

Rtn adr

Old%ebp %ebp0

4

8

12

OffsetStack

•••

z16

43

int arith(int x, int y, int z){int t1 = x+y;int t2 = z+t1;int t3 = x+4;int t4 = y * 48; int t5 = t3 + t4;int rval = t2 * t5;return rval;

}

ex

Understandingarith (IA32)

movl 8(%ebp),%eax # eax = xmovl 12(%ebp),%edx # edx = yleal (%edx,%eax),%ecx # ecx = x+y (t1)leal (%edx,%edx,2),%edx # edx = y + 2*y = 3*ysall $4,%edx # edx = 48*y (t4)addl 16(%ebp),%ecx # ecx = z+t1 (t2)leal 4(%edx,%eax),%eax # eax = 4+t4+x (t5)imull %ecx,%eax # eax = t5*t2 (rval)

y

x

Rtn adr

Old%ebp %ebp0

4

8

12

OffsetStack

•••

z16

44

int arith(int x, int y, int z){int t1 = x+y;int t2 = z+t1;int t3 = x+4;int t4 = y * 48; int t5 = t3 + t4;int rval = t2 * t5;return rval;

}

Understandingarith (IA32)

movl 8(%ebp),%eax # eax = xmovl 12(%ebp),%edx # edx = yleal (%edx,%eax),%ecx # ecx = x+y (t1)leal (%edx,%edx,2),%edx # edx = y + 2*y = 3*ysall $4,%edx # edx = 48*y (t4)addl 16(%ebp),%ecx # ecx = z+t1 (t2)leal 4(%edx,%eax),%eax # eax = 4+t4+x (t5)imull %ecx,%eax # eax = t5*t2 (rval)

y

x

Rtn adr

Old%ebp %ebp0

4

8

12

OffsetStack

•••

z16

45

int arith(int x, int y, int z){int t1 = x+y;int t2 = z+t1;int t3 = x+4;int t4 = y * 48; int t5 = t3 + t4;int rval = t2 * t5;return rval;

}

Understandingarith (IA32)

movl 8(%ebp),%eax # eax = xmovl 12(%ebp),%edx # edx = yleal (%edx,%eax),%ecx # ecx = x+y (t1)leal (%edx,%edx,2),%edx # edx = y + 2*y = 3*ysall $4,%edx # edx = 48*y (t4)addl 16(%ebp),%ecx # ecx = z+t1 (t2)leal 4(%edx,%eax),%eax # eax = 4+t4+x (t5)imull %ecx,%eax # eax = t5*t2 (rval)

y

x

Rtn adr

Old%ebp %ebp0

4

8

12

OffsetStack

•••

z16

46

int arith(int x, int y, int z){int t1 = x+y;int t2 = z+t1;int t3 = x+4;int t4 = y * 48; int t5 = t3 + t4;int rval = t2 * t5;return rval;

}

Observationsaboutarith

movl 8(%ebp),%eax # eax = xmovl 12(%ebp),%edx # edx = yleal (%edx,%eax),%ecx # ecx = x+y (t1)leal (%edx,%edx,2),%edx # edx = y + 2*y = 3*ysall $4,%edx # edx = 48*y (t4)addl 16(%ebp),%ecx # ecx = z+t1 (t2)leal 4(%edx,%eax),%eax # eax = 4+t4+x (t5)imull %ecx,%eax # eax = t5*t2 (rval)

47

§ Instructions indifferentorder fromCcode

§ Someexpressions requiremultipleinstructions

§ Someinstructionscovermultipleexpressions

§ Same x86codebycompiling:(x+y+z)*(x+4+48*y)

int arith(int x, int y, int z){int t1 = x+y;int t2 = z+t1;int t3 = x+4;int t4 = y * 48; int t5 = t3 + t4;int rval = t2 * t5;return rval;

}

AnotherExample(IA32)

48

int logical(int x, int y){int t1 = x^y;int t2 = t1 >> 17;int mask = (1<<13) - 7;int rval = t2 & mask;return rval;

}

logical:pushl %ebpmovl %esp,%ebp

movl 8(%ebp),%eaxxorl 12(%ebp),%eaxsarl $17,%eaxandl $8185,%eax

movl %ebp,%esppopl %ebpret

SetUp

Finish

y

x

Rtn adr

Old%ebp %ebp0

4

8

12

Offset

Stack•••

Body

ex

AnotherExample(IA32)

49

int logical(int x, int y){int t1 = x^y;int t2 = t1 >> 17;int mask = (1<<13) - 7;int rval = t2 & mask;return rval;

}

logical:pushl %ebpmovl %esp,%ebp

movl 8(%ebp),%eaxxorl 12(%ebp),%eaxsarl $17,%eaxandl $8185,%eax

movl %ebp,%esppopl %ebpret

SetUp

Finish

movl 8(%ebp),%eax eax = xxorl 12(%ebp),%eax eax = x^y (t1)sarl $17,%eax eax = t1>>17 (t2)andl $8185,%eax eax = t2 & 8185

Body

AnotherExample(IA32)

50

int logical(int x, int y){int t1 = x^y;int t2 = t1 >> 17;int mask = (1<<13) - 7;int rval = t2 & mask;return rval;

}

logical:pushl %ebpmovl %esp,%ebp

movl 8(%ebp),%eaxxorl 12(%ebp),%eaxsarl $17,%eaxandl $8185,%eax

movl %ebp,%esppopl %ebpret

SetUp

Finish

movl 8(%ebp),%eax eax = xxorl 12(%ebp),%eax eax = x^y (t1)sarl $17,%eax eax = t1>>17 (t2)andl $8185,%eax eax = t2 & 8185

Body

AnotherExample(IA32)

51

int logical(int x, int y){int t1 = x^y;int t2 = t1 >> 17;int mask = (1<<13) - 7;int rval = t2 & mask;return rval;

}

logical:pushl %ebpmovl %esp,%ebp

movl 8(%ebp),%eaxxorl 12(%ebp),%eaxsarl $17,%eaxandl $8185,%eax

movl %ebp,%esppopl %ebpret

Body

SetUp

Finish

movl 8(%ebp),%eax eax = xxorl 12(%ebp),%eax eax = x^y (t1)sarl $17,%eax eax = t1>>17 (t2)andl $8185,%eax eax = t2 & 8185

213 =8192, 213 – 7=8185…0010000000000000,…0001111111111001

compileroptimization