IR Drop using Voltage Strom.pdf

Comprehensive SoC Power Grid verification using VoltageStorm

Navneet Mohindru, VoltageStorm Product Validation Lead

Lalit Garg, VAVO Product Engineer

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Agenda

•Introduction

•Static and Dynamic IR drop analysis using VoltageStorm

•SoC Hierarchical Analysis Methodology

•Results and Observations

•Conclusions

•Q&A

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Introduction

• Low power supply voltage causing IR drop problems in SoC designs

• Increasing demand to handle analog blocks in SoC

– Have their own dedicated supplies

– Must account for block boundary voltages

– IR drop/ground bounce from top-level power routing

– Some analog blocks share digital power supplies

• Integration with VoltageStorm

– Base SoC power integrity product

– Hierarchical, cell-based approach

– Utilizes abstracted power grid views

– Mix & match power grid views for complete solution

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Static and Dynamic IR drop analysis using VoltageStorm

•VoltageStorm supports both static and dynamic IR drop analysis

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Static IR drop analysis using VoltageStorm

•Static IR drop analysis verifies robustness of power rail by showing static IR drop, open circuits, missing vias and high current densities

•Static IR drop analysis is based upon average power calculated by powermeter

•Average power calculation is based upon three methods

– Full-chip VCD

– Accura based switching probability propagation method

– Mixture of Accura and VCD

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Dynamic IR drop analysis using VoltageStorm

• Dynamic IR drop analysis is used for analyzing the effect of transient IR drop

• Helps in optimizing number of decoupling capacitors to reduce leakage in 90nm and sub-90nm designs

• Based upon instance based dynamic current consumption calculated by powermeter

• Powermeter uses two methods to calculate dynamic current consumption– Vector-based

– Uses gate or transistor level simulation to generate dynamic power/current waveform

– Most accurate solution if “right” vectors are provided by user

– Vectorless– Uses timing window information to generate dynamic power/current

waveform

– Best approach to obtain full-chip transient information

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SoC Hierarchical Analysis Methodology

• VoltageStorm uses power grid views for enabling hierarchical solution

• A power grid is used to model power rail and power distribution information of each instance in design.

• For SoC design, different type of power grids will include

– standard cell views

– digital blocks

– IP/Memory blocks

– Analog/Mixed Signal Blocks

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Types of Power Grid Views

• VoltageStorm uses four types of power grid views for hierarchical static analysis

– Detailed

– Reduced

– Abstract

– Port

• For hierarchical dynamic analysis, three additional types of power grid views are used

– Detailed Dynamic

– Reduced Dynamic

– Port

Static Power Grid ViewsDetailed Reduced Abstract Port

Dynamic Power Grid ViewsDetailed Dynamic Reduced Dynamic Port

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Power Grid Views for Standard Cells

• For standard cells port views are sufficient. However for dynamic analysis detailed views are created for CRC modeling of standardcell.

• CRC modeling– R on

– Device C

– Load C (Pin capacitance)

outdevice C

device Ron

Pin-cap

x out

VDD

Cell

xdevice C

Loading C from

SPEF/DSPF

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Power Grid Views for Memory/Hard IP• For Memory and hard IP, detailed views are created for verifying that these blocks do not suffer from IR drop within the instance

• Two methods are used– Libgen detailed view creation.

– Most common method

– Transistor level VoltageStorm Flow

– Used for detailed dynamic PGV creation

– Device recognition and spice netlistgeneration

– RC extraction

– Spice-like simulation on spice netlist for current tap generation

– Analysis on power grid

– Generate detailed/reduced power grid view from analysis results

VST

LibGen

Vectors

LEF

GDS

Detailed Dynamic PGV

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Power Grid Views for Digital Blocks

•For creating power grid views of digital blocks, static or dynamic IR drop analysis is run at block level first. Here are the steps

– Calculate instance based average static/dynamic current.

– Run R or RC extraction on block level power grid.

– Merge the static or dynamic current with the extracted power grid.

– Run static/dynamic analysis.

– Generate detailed/reduced power grid view for the block from the analysis results.

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Power Grid Views for Analog/ Mixed-Signal Blocks (VAVO)

•Analog VoltageStorm (VAVO) accurately characterize power consumption and power distribution inside analog and mixed signal blocks

– Power integrity verification

– IR drop (power and ground rails)

– Power rail Electromigration

– Integrated with Virtuoso ADE environment

– Flow supported by existing Cadence products

– Assura LVS

– Assura RCX

– Spectre or UltraSim for simulation

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VAVO FLOW DIAGRAM

Schematic Layout

Assura LVS

Assura RCX (RC extraction)

Create simulation netlistfrom config view includingAssura extracted cellview

Testbench schematic

Assura extracted cellview

Create Simulation files

Run Spectre or UltraSim

Run VAVO/VAEO

Display results inAssura extracted cellview

Create Power Grid View

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Simulation Details in VAVO

VDD

Top-levels of interconnect

M1

M6

M5

M4

AnalogCircuit

Voltage measures are automatically added to

extracted netlist

V

V V V

V V

V V

VVVVVV

V

V V

V

V V V V

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VAVO Plot and Report Examples

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VoltageStormComprehensive SoC Power Grid Verification

Small Digital Design

Mixed-Signal & Analog Design

Power Grid Views(static & dynamic)

VoltageStorm PE(activity propagation,

static, cell-based)

VoltageStorm VST(dynamic, transistor)

UltraSim

VoltageStorm PE

VoltageStorm VAVO(dynamic, transistor)

SpectreUltraSim

VoltageStorm DG(vectorless & VCD,

dynamic, cell-based)

CeltICNDC

Full ChipStatic & Dynamic

CeltICNDC

Large Digital Design

Large Digital Design

Virtuoso PlatformEncounter Platform

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Results and Observations

Static IR Drop top level run with VAVO detailed view of PLL

Static IR Drop top level run with libgen detailed view of PLL

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Results and Observations

•The power grid views generated by VAVO for the analog block are more accurate because of the following reasons:

– Device recognition is more accurate because Assura LVS is used to extract analog devices.

– RCX is more accurate in extracting parasitics for non-manhattan geometry.

– Tap current in VAVO is calculated from actual Spice-like simulation.

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Conclusions

•Here are conclusions from this methodology

– VoltageStorm can analyze and characterize all types of blocks such as digital blocks, memories, hard IPs and analog/mixed signal blocks accurately at SoC level.

– The hierarchical flow of VoltageStorm gives it infinite capacity since designer can create as many power grid views as required and feed them into top level run.