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VDAT 2002 Power aware Charaterization of IPPS 1
Power Aware Characterization ofInput Vectors Sequence for Std.
Cell Based Circuits
Pramod K. Jain D. Boolchandani V. Sahula
Department of ECE
Malaviya National Institute of Technology, Jaipur
Deemed university)
[email protected], [email protected], [email protected]
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VDAT 2002 Power aware Charaterization of IPPS 2
Index
Motivation
Sources of power dissipation
Power estimation from layout (full adder)
Power minimization technique
Characterizing the IPPs sequence
Integer linear programming
Greedy heuristic
Results
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VDAT 2002 Power aware Charaterization of IPPS 3
Motivation
Cell selection for low power
technology mapping
Low power sequence for stored
data application
Data processing is independentof sequence of input data
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Analysis
accurate estimation
Optimization
process of generating the best design
Estimation techniques forms foundation fordesign optimization
Low Power VLSI Design
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Power Estimation Techniques
Accuracy vs Computing resources (Time and memory)
Abstraction level computing resources Analysis accuracy
Algorithms least WorstSoftware and system
Hardware behavior
Resistor transfer
Logic (gate) level
Circuit (transistor) level
Device level Worst Best
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Power Measurement
Simulation based approach
Higher accuracy
Not feasible for large circuits
Large memory and
Large simulation time
Probabilistic approach
Power dissipation due to transitions only
Sacrifice accuracy
Complexity
switching activity estimation
Not suitable for small circuits
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Probabilistic Technique
Switching power estimation of full adder
Where
D(yi): # of the transitions per time interval
Ci : capacitance at node i
( )i
n
1ii
2
ddav yDCV2
1
P ==
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a0
b0
c0
s0
cy
n18y8
y7
n16
y6
y5n19
y4
y2
y3
y1
y9
y10
1-Bit Full Adder Example
Layout in 1.5m, Tanner
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Power Components in FA Switching Power ?
Short ckt. Power lower for smaller FT, RT
Leakage power
Constt. (Small)
Ckt Total power
(W)
Dynamic power
(W)
Dynamic vs
Total
Adder 1204 1197 99.4%
NAND2 37 35 94.6%
2_1 MUX 211 202 95.7%
XOR 328 325 99.0%
Tool used for Switching power estimation
Tanner SPICE
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Power Minimization
Technique Switching power is major contributor
More than 80% of total power (small
circuits)
Minimize the internal switching activity
by selecting appropriate sequence of the
input data
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Agenda
Objective: Find sequence of input-vectors withminimum power dissipation
Procedure:
Enumerate pair of O/P transitions Enumerate corresponding 2 I/P vectors
Enumerate sequence of O/P transitions Enumerate sequence of I/P vectors
Estimate power in switching between 2 I/Pvectors
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Output and Input Transitionsn bn fn
0 0 00 1 1
1 0 1
1 1 0
fn fn+10 0
0 1
1 0
1 1
fn fn+10 0
nb
n
an+1bn+100 0000 11
11 00
11 11
a, b, f {0,1}
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Problem Definition
Problem: Which is minimum powersequence of I/P vectors out of (2k-1)!sequences?
Model: Directed graph Gof 2k nodes & lP2edges
Solution: Find minimum weightHamiltonian cycle in G. Know theedge weights (Power in I/P pair).
k 2 3 =2
k 4 8
2P
12 56
)!1( 6 5040
k Number of I/Ps =2
k Number of I/Pvectors
2P
Number of pairs of
I/P vectors
)!1(
Possible number of
sequences of I/P
vectors
00
10 11
01
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Tracing of Hamiltonian Cycle-
Time complexity ILP Based Exact algorithm
Sub tours elimination constraints
Edge cover heuristic
Sorting edges in ascending order of weight
Selection of edges till completion of the HC
O(E)
=
2
2
l
kk
lC
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Char. of IPPs for Low Power
Input Pattern Pair (IPP) A pair of consecutive input vectors called IPP Select the suitable sequence of IPPs
minimize the power dissipation
Hamiltonian cycle closed path in a digraph, which starts and ends on
the same node, passing through all the nodes only
once
Problem Def: Finding a minimum weight Hamiltonian cycle
(HC) in a complete digraph
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IPPs for 3-bit Input Circuit
Input vectors are l=2ne.g. (000,
001, 010, etc)
7 IPPs corresponding to eachinput vector.
Total number of IPPs would be lp2
Sum
Full
Adder
a0
b0
c0
cy
56
8
3
2 =
=
=
P
n
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Power component in full adder
Ex. parasitic In. parasitic % Difference
Total Power
using
simulation
587.7w 1197.2 w 42.5% contr.
by parasitic
Dy. Power
using prob.
Method
956.3 w 79.8% to the
total power
r t=rise time=.01ns, f t= fall time=.01ns, p w=pulse width=10ns, Adder delay =3.63ns
Di h R t ti f All
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011
000
001
010
100
101
110
111
A node in a digraphcorresponds to an inputvector
An edge of the digraphcorresponds to inputvector transition
The edge weight C ij
the power consumed intransition.
Possible transitions of input vectors for a 3-input circuit
Digraph Representation of All
Possible IPPs
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Time complexity
ILP Sub tours elimination constraints
Heuristic
Sorting in ascending order Selection of edges till completion of the HC
O(E)
=
2
2
l
k
klC
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0-1 ILP Based Solution
Find minimum weight Hamiltonian cycle
(HC) in a complete digraph
ILP provides the exact solution
Formulation
Objective function
Constraints equations
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Introducing a decision variable 0-1 variable Xijsuch that
=
otherwise
cyclenHamiltoniainisjtoiedgetheif
ij
X
0
1
The constraint equations to satisfy two conditions
every node must have exactly one in-degree and one
out-degree
sub cycles which are the disjoint loops in the diagraph
must be eliminated.
0-1 ILP Based Solution (Contd.)
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jiforn
j
n
i ijXijC
functionObjective
= =
,1 1
min
:
{ }nkforki kj
ijX
ijandnjforn
i ijX
ijandniforn
j ijX
thatSuch
.......,2,12
.......,2,11
1
.......,2,11
1
==
=
==
=
# of equations required
very large O(2l)
146 even for 3-input circuit
Represents In degree 1.
Represents Out degree 1.
Sub cycles eliminationconstraints
ILP Formulation
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Proposed Heuristic: Minimum
Power Edge Cover (MPEC)
Minimum-Power Edge-Cover G (V, E)
1. R=E; // R is remaining edge
2. C=; // C is cycle edge
3. While R is not empty
3.1 Remove the shortest edge (v, w) from R
3.2 Check for cycle and in/out degree of a node
3.3 If [(v,w) does not make a cycle with edges in C]
AND [(v,w) would not be second out going or
second incoming edge in C incident on v or w]
3.3.1 Add (v, w) to C3.4 Continue loop
4. Add the edge connecting the end points of the path in C
5. Return C;
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VDAT 2002 Power aware Charaterization of IPPS 24
Power in HCs: XORGate
ExampleSequence Power Sequence Power
0, 1, 2, 3 258 w 2, 0, 1, 3 290 w
0, 1, 3, 2 286 w 2, 0, 3, 1 326 w
0, 2, 1, 3 253 w 2, 1, 3, 0 256 w
0, 2, 3, 1 283 w 2, 1, 0, 3 329 w
0, 3, 1, 2 321 w 2, 3, 0, 1 257 w
0, 3, 2, 1 329 w 2, 3, 1, 0 285 w
1, 0, 2, 3 285 w 3, 0, 1, 2 258 w
1, 0, 3, 2 328 w 3, 0, 2, 1 257 w
1, 2, 0, 3 324 w 3, 1, 0, 2 285 w1, 2, 3, 0 256 w 3, 1, 2, 0 324 w
1, 3, 0, 2 255 w 3, 2, 0, 1 288 w
1, 3, 2, 0 287 w 3, 2, 1, 0 329 w
Average Sequence Power = 289.54
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Cell HC/ [Power] using
ILP
HC/ [Power] using
Heuristic
% Difference
XOR 0, 2, 1, 3 [253 w] 3, 0, 2, 1 [257w]
0, 1, 2, 3 [33w]
2, 1, 3 [161 w]
1.32%
NAND 2, 0, 1, 3 [28 w] 15.2%
S-R FF 2, 1, 3 [161 w] 0%
Comparing Two Techniques: Low
Power IPPs Sequence
Minimum power HC comparisons using ILP versus Heurist ic
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Cell Min. Power HC Avg. Min. Power
3-input NAND 1, 4, 2, 0, 3, 5, 6, 7 52 w
3-input OR 0, 1, 2, 4, 6, 5, 3, 7 78w
3-input NOR 0, 2, 3, 4, 6, 7, 5, 1 70w
2_1 MUX 2, 6, 0, 4, 1, 3, 7, 5 87 w
ADDER 6, 7, 0, 1, 4, 2, 3, 5 2160 w
AND-2 NOR-2 2, 4, 0, 3, 5, 1, 6, 7 337w
OR-2 AND-2 1, 0, 2, 4, 6, 3, 5, 7 94w
AOI 15, 13, 6, 3, 2, 7, 11, 9, 12, 0, 10, 8,
1, 4, 5, 14
85 w
MPEC Heuristic Results: Min. Power
Bound
MPEC H i ti R lt M P
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Cell Max. Power Hamiltonian cycle Avg. Max.
Power
2-input NAND 3, 1, 0, 2 37w
2-input XOR 1, 0, 3, 2 328w
3-input NAND 7, 3, 0, 6, 1, 2, 5, 4 69 w
3-input OR 5, 4, 0, 6, 1, 3, 7, 2 126w
3-input NOR 4, 0, 3, 6, 1, 2, 5, 7 99w
2_1 MUX 1, 6, 3, 4, 7, 2, 7, 5 211 w
continued
MPEC Heuristic Results: Max. Power
Bound
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Cell Max. Power Hamiltonian cycle Avg. Max. Power
ADDER 0, 3, 6, 5, 2, 7, 4, 1 2460 w
S_R FF 3, 1, 2 305 w
AND-2 NOR-2 1, 7, 0, 5, 4, 3, 6, 2 2626w
OR-2 AND-2 4, 1, 5, 0, 3, 6, 7, 2 248w
AOI 5, 12, 4, 8, 3, 11, 2, 10, 9, 1, 7, 6, 13,
14, 15, 0
106 w
MPEC Heuristic Results: Max. Power
Bound (Contd.)
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Conclusions
Dynamic power
major contributor
Efficient method for power characterization using
IPPs advantageous in technology mapping for low power
Results using proposed heuristic
optimal or nearly optimal sequence