VIETMOBILE.VN IPHONE XS MAX SCHEMATIC
VIETMOBILE.VN
IPHONE XS MAX SCHEMATIC
VIETMOBILE.VN
VIETMOBILE.VN
VIETMOBILE.VN
VIETMOBILE.VN
D32/D33 Top MLB: EVT (D32 Build)
BOM:639-03991 (Ultimate)
MCO:056-05750
BOM:639-03992 (Extreme)BOM:639-03990 (Max)
1 OF 60
SYSTEM:BOM Tables FF SpecificSYSTEM: Mechanical Components
BOOTSTRAPPING
12
LAST_MODIFICATION=Wed Jan 31 16:37:18 2018
10/13/2016
04/05/201704/05/2017
test_mlb
Interposer: Pins 286-359
10/13/201610/13/201610/13/2016
10/13/2016
60
I/O: B2B Dock
SYSTEM: AP I2CSYSTEM: ISP I2C
SYSTEM: SOC/PMU GPIOs
Interposer: Pins 1-144
SOC: MIPI
SOC: GPIO & UART
SOC: POWER (3/3)
SYSTEM POWER: PMU Bucks (1/4)
08/29/2017
04/17/2017
51
51
I/O: HydraI/O: USB PDI/O: Gecko
CAMERA: PMU (1/2)
SYSTEM POWER: Boost
SYSTEM POWER: PMU LDOs (3/4)
10/13/2016
10/13/2016
03/22/2017
test_mlb
5
test_mlb
03/22/2017
41
57
10/13/2016
SYSTEM POWER: B2B Batterytest_mlb
03/22/2017
10/17/2016
test_mlb
10/13/2016
14
test_mlb
10/13/2016
30
CAMERA: B2B Tele [MT]
test_mlb
10/13/2016
test_mlb
SYSTEM POWER: PMU (4/4)
20
26SYSTEM POWER: B2B Cyclone + ButtonSENSORS
CAMERA: PMU (2/2)test_mlb
34
27 3510/13/2016
29
CAMERA: B2B Fcam
129
1317
35
38
50
I/O: Overvoltage Cut-Off Circuit
3
SOC: LPDP
44
04/05/2017
59
test_mlb
11
32
31
33 41
33 SYSTEM POWER: Charger
18
46
36
06/01/2017
10/13/2016
04/05/2017
10/17/2016
10/13/2016
48
03/10/2017
Interposer: Pins 145-285
5453
10/13/2016
5756
10/17/2016
1
4
04/05/2017
83
I/O: LDCM
B2B: Interposer Bot
SYSTEM: AOP GPIOs
Interposer: Top Aliases
2
4
6
28
31
3940
4243
45
4647
4950
52
55
585960
26
32
36
38
40
42
44
616263646566676870
8182
85
test_mlbtest_mlbtest_mlb
test_mlbtest_mlb
test_mlb
test_mlbtest_mlbtest_mlb
test_mlbtest_mlb
test_mlbtest_mlbtest_mlb
test_mlbtest_mlbtest_mlbtest_mlbtest_mlb
08/09/2017
10/13/2016
04/07/2017
08/17/2017
03/10/2017
03/10/2017
10/13/201610/13/2016
06/06/2017
08/30/2017
05/09/201705/09/2017
08/30/201708/17/201708/30/2017
30
test_mlb
161514
SYSTEM:BOM Tables
11
10/13/2016
AUDIO: SOUTH SPKAMP
10
ARC: AMP
37
SYSTEM: Testpoints (Top)
27
2117
10/13/2016PEARL: B2B Rosaline + Sensor
29
test_mlb45
43
32
1
test_mlb
8
25
13
7
AUDIO: NORTH SPKAMP
AUDIO: CODEC (1/2)
PEARL: B2B Romeo + Juliet
39 10/13/2016
03/22/2017
SOC: PCIESOC: JTAG,USB,XTAL
65
15
1819
21
23
49
test_mlb
CAMERA: Strobe Drivers
CAMERA: B2B Strobe + Hold ButtonPEARL: Power
37
CAMERA: B2B Wide (TX)
SOC: DEV BOARD ALIASES2016
test_mlb
test_mlb
SOC: LPDP ALIASES
SOC: POWER (2/3)SOC: POWER (1/3)
10
24
TABLE OF CONTENTS
47
CG: B2B Display
SYSTEM: AOP/SMC I2C
71
NAND
SYSTEM POWER: PMU Bucks (2/4)2822
SOC: SERIAL
SOC: AOP
19
48 AUDIO: CODEC (2/2)
SCH,MLB,TOP,D32051-02545
2018-02-0500111753087 ENGINEERING RELEASED
1 OF 85
7.0.0
051-02545 SCHSCH,MLB_TOP,D32 CRITICAL ?1
PCBPCB,MLB_TOP,D32 ?CRITICAL820-00997 1
TABLE OF CONTENTS
BRANCH
8
REVISION
ECNREV DESCRIPTION OF REVISION2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
CKAPPD
2 1
124567
B
D
6 5 4 3
C
A
PAGE
C
A
D
DATE
SHEET
DSIZEDRAWING NUMBER
7
B
3
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
PROPRIETARY PROPERTY OF APPLE INC.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
DRAWING TITLE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
VIETMOBILE.VN
XTAL Alternate
NEON Alternate
ANSEL Alternate
NAND
Display CMC's
Ultimate
Max
Extreme
Denali Inductors
Global R/C AlternatesYangtze Inductors
2 OF 60
7.0.0
2 OF 85
051-02545
ALL152S00872 ALT_PARTS IND,MLD,0.47UH,TDK152S00918
ALT_PARTS ALL152S00847 IND,MLD,0.47UH,CYN152S00918
SYSTEM:BOM TablesSYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
CAP,CER,X5R,2.2UF,20%,6.3V,0201ALT_PARTS ALL138S00049 138S0831
138S0652 ALL CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO138S0648 ALT_PARTS
ALL CAP,CER,X5R,0.22UF,20%,6.3V,20%ALT_PARTS138S0706138S0739
335S00340335S00288 SAMSUNG, 3DV4, ULTALT_PARTS U2600
335S00286 U2600335S00340 ALT_PARTS SANDISK, BICS3, ULT
U2600 SAMSUNG, 3DV4, SUPREME335S00276 ALT_PARTS335S00342
TOSHIBA, 3DV4, SUPREME335S00358 U2600ALT_PARTS335S00342
SANDISK, BISC3, SUPREMEU2600335S00247 ALT_PARTS335S00342
335S00342 EXTREMECRITICAL1 U2600HYNIX, 3DV4, Extreme
335S00359 335S00340 U2600ALT_PARTS TOSHIBA, BICS3, ULT
1 HYNIX, 3DV4, MAX CRITICAL MAX335S00343 U2600
335S00343 SAMSUNG, 3DV4, MAXU2600ALT_PARTS335S00339
HYNIX, 3DV4. ULTIMATE CRITICAL ULTIMATEU26001335S00340
ALT_PARTS 0402-3T,10.5uF@1V, KyoceraALL138S00148 138S00149
IND,MLD,0.47UH,20%,4.5A,47MOHM,H=.8,2012152S00822
ALT_PARTS ALL152S00825 152S00823 IND,MLD,1UH,20%,3A,60MO,H=.65,2016
ALT_PARTS152S00821 ALL152S00826 IND,MLD,1UH,20%,2.1A,52MO,H=.80,2012
ALT_PARTS ALL152S00866 152S00821 IND,MLD,1UH,20%,2.1A,52MO,H=.80,2012
0201,3uF@1V138S00139
IND,MLD,0.22UH,20%,5.8A,40MOHM,H=.65,1608152S00918
ALT_PARTS152S00822 IND,MLD,0.47UH,20%,4.5A,50MOHM,H=.80,2012ALL152S00827
ALT_PARTS152S00829 152S00817 ALL IND,MLD,0.1UH,20%,9.0A,22MOHM,H=0.8,2012
ALT_PARTS152S00819 ALL152S00824 IND,MLD,1UH,20%,2A,69MO,H=.65,2012
ALT_PARTS152S00828 152S00820 ALL IND,MLD,0.47UH,20%,3.2A,400MO,H=.80,2012
152S00831 IND,MLD,0.22UH,20%,5.8A,40MOHM,H=.65,1608
XTAL, 24M, 1612197S00118 ALT_PARTS197S0612 Y1000
138S00141 0201,1.1uF@3V
IND,MLD,0.1UH,20%,9.4A,22MOHM,H=0.65,1608152S00817
152S00820 IND,MLD,0.47UH,20%,3.2A,42MO,H=.80,2012
152S00819 IND,MLD,1UH,20%,1.7A,69MO,H=.65,2012
152S00823 IND,MLD,1UH,20%,3.0A,60MO,H=.65,2016
152S00821 IND,MLD,1UH,20%,2.2A,60MO,H=.80,2012
ALT_PARTS TY, IND152S00875152S00716 L3700138S00141 ALL 0201,1.1uF@3V, Taiyo138S00166 ALT_PARTS
138S00141 ALT_PARTS ALL138S00140 0201,1.1uF@3V, Kyocera
138S00141 ALLALT_PARTS 0201,1.1uF@3V, SEMCO138S00142
ALL 0402,16uF@1V, TY138S00163 ALT_PARTS138S00144
ALT_PARTS152S00818 IND,MLD,0.22UH,20%,5.9A,36MOHM,H=.65,1608,CYNALL152S00831
138S00144 0402,16uF@1V
0402,5.1uF@3V138S00146
138S00149 0402-3T,10.5uF@1V
155S00391155S00415 ALT_PARTS ALL CMC,35OSM,7HGz,MUR
ALT_PARTS 0402-3T,10.5uF@1V, SEMCOALL138S00150 138S00149
0402-3T,10.5uF@1V, TYALT_PARTS138S00151 ALL138S00149
ALL 0402,16uF@1V, Kyocera138S00143 138S00144 ALT_PARTS
0201,3uF@1V, TY138S00139138S00164 ALLALT_PARTS
0201,3uF@1V, Kyocera138S00139 ALL138S00138 ALT_PARTS
0402,5.1uF@3V, Kyocera138S00221 ALT_PARTS138S00146 ALL
152S00876 L4100, L4120 TY, IND152S00721 ALT_PARTS
197S00118 XTAL, 24M, 1612197S00120 ALT_PARTS Y1000
ALT_PARTS152S00820 ALL IND,MLD,0.47UH,20%,3.8A,270MO,H=.80,2012152S00834
ALT_PARTS152S00819 ALL152S00833 IND,MLD,1UH,20%,2.1A,62MO,H=.65,2012
ALT_PARTS152S00877 152S00817 ALL IND,MLD,0.1UH,20%,9A,20MOHM,H=0.8,2012
ALT_PARTS ALL IND,MLD,0.47UH,20%,4.5A,40MOHM,H=.80,2012152S00822152S00835
ALT_PARTS152S00831 ALL152S00878 IND,MLD,0.22UH,20%,5.9A,36MOHM,H=.65,1608
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALTABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_ALT_ITEM
TABLE_ALT_ITEM
VIETMOBILE.VN
Cyprus OMIT
EEEE Codes
Combo Stiffener
Cyprus ALTs
3 OF 60
7.0.0
3 OF 85
051-02545
SYNC_MASTER= SYNC_DATE=08/09/2017
SYSTEM:BOM Tables FF Specific
ULTIMATEEEEE_HWV1825-7691 1 EEEE FOR (MLB_TOP,639-03991,ULTIMATE) CRITICAL
EEEE FOR (MLB_TOP,639-03992,EXTREME) EXTREMEEEEE_HWV21825-7691 CRITICAL
EEEE_HWV01825-7691 EEEE FOR (MLB_TOP,639-03990,MAX) MAXCRITICAL
339S00510 1 SOCU1000 CRITICALCYPRUS 4GB Micron
ST04011604-19651 Combo Stiffener CRITICAL ALL
U1000339S00510339S00511 CYPRUS 4GB HynixALT_PARTS
ALT_PARTS U1000339S00510339S00512 CYPRUS 4GB Samsung
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VIETMOBILE.VN
Crosses
Squares
FIDUCIALS
4 OF 60
7.0.0
4 OF 85
051-02545
21
R0401
21
R0402
21
R0403
1
SB0401
1
ST0401
21
CL0402
1SH0402
1SH0401
1SH0403
1
FD0408
1
FD0406
1
FD0407
1
FD0404
1
FD0403
1
FD0402
1
FD0401
1
FD0412
1
FD0405
1
FD0410
1
FD0411
1
CL0400
1
CL0401
1
CL0403
CKPLUS_WAIVE=TERMSHORTED
CKPLUS_WAIVE=TERMSHORTED
CKPLUS_WAIVE=TERMSHORTED
CKPLUS_WAIVE=TERMSHORTED
2.10R1.60-NSPMF
01005
0.00
0%1/32W
1/32W0%
0.00
01005MF
MF01005
0.00
0%1/32W
0P5SQ-CROSS-NSP
SYSTEM: Mechanical Components
2.10R1.60-NSP
2.10R1.60-NSP
STDOFF-2.9OD1.4ID-0.77H-SM1
OMIT_TABLE
SMWELD-AP-D3X
STDOFF-3.0OD1.6ID-H0.62-TH-D32
SM
SHIELD-S-MLB-D32
SM
SHIELD-W-MLB-D32
SHIELD-N-MLB-D32
SM
FID0P5SQ-SMP3SQ-NSP
ROOM=ASSEMBLY
ROOM=ASSEMBLY
FID0P5SQ-CROSS-NSP
FID
ROOM=ASSEMBLY
0P5SQ-CROSS-NSP
0P5SQ-CROSS-NSPFID
ROOM=ASSEMBLY
ROOM=ASSEMBLY
0P5SQ-CROSS-NSPFID
ROOM=ASSEMBLY
0P5SQ-CROSS-NSPFID
ROOM=ASSEMBLY
FID
FID
ROOM=ASSEMBLY
0P5SQ-SMP3SQ-NSP
0P5SQ-SMP3SQ-NSPFID
ROOM=ASSEMBLY
FID
ROOM=ASSEMBLY
0P5SQ-SMP3SQ-NSP
0P5SQ-SMP3SQ-NSPFID
ROOM=ASSEMBLY
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VIETMOBILE.VN
PMU XTAL
Hydra VBUS
Rigel
SOC Debug
LVCCPEARL
BUMP SENSE
NAND
Sensors
PMU
METROLOGY
VALIDATION PP's
WALLET MODE
CCG SWD
PCIE Refclk
5 OF 60
7.0.0
5 OF 85
051-02545
1
PP0533
1
PP0532
1
PP0525
1
PP0524
1
PP0599
1
PP0518
1
PP0517
1
PP0598
1
PP0597
1
PP0596
1
PP0595
1
PP0594
1
PP0567
1
PP0566
1
PP0591
1
PP0590
1
PP0588
1
PP0565
21
XW0510
21
XW05111
PP0511
1
PP0510
1
PP0551
1
PP0553
1
PP0552
1
PP0507
1
PP0506
1
PP0593
1
PP0592
1
PP0586
1
PP0587
1
PP0505
1
PP0547
1
PP0546
1
PP0544
1
PP0571
1
PP0570
1
PP0504
1
PP0564
1
PP0563
1
PP0522
1
PP0562
1
PP0521
1
PP0516
1
PP0514
1
PP0561
1
PP0560
1
PP0550
1
PP0542
1
PP0541
1
PP0540
1
PP0531
1
PP0530
1
PP0520
1
PP0513
1
PP0512
1
PP0503
1
PP0502
1
PP0501
1
PP0500 XTAL_TO_PMU_CLK32K_2NAND_ANI0_VREF
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
SPMI_PMU_BI_PMGR_SDATA
PHOSPHORUS_TO_AOP_INT
HYDRA_TO_YANGTZE_VBUS1_VALID_L
NFC_TO_ARC_RESET_L
NFC_TO_ARC_TRIG
AP_TO_NAND_RESET_L
PP_ROMEO_DENSE_ANODE
SOC_SENSE_POS
SOC_SENSE_NEG
CPU_PCORE_SENSE_NEG
BOARD_ID0
SOC_DEBUG2
SOC_DEBUG3
PMU_TO_AP_PRE_UVLO_L
VDDQL_SENSE_POS
GPU_SENSE_POS
GPU_SENSE_NEG
VDDQL_DCS_SENSE_NEG
PP_ROMEO_CATHODE
CPU_PCORE_SENSE_POS
SWD_AP_BI_NAND_SWDIO
AP_TO_PMU_TEST_CLKOUT
DFU_STATUS
PP_GPU_LVCC
SPI_AOP_TO_IMU_MOSIPP_CPU_PCORE_LVCCPP_CPU_PCORE
PP_GPU
AOP_TO_DDR_SLEEP1_READY_PROBE
PMU_TO_AP_HYDRA_ACTIVE_READY
SPI_AOP_TO_IMU_SCLK
CCG2_TO_SMC_INT_L
UART_AP_DEBUG_RXD
SPI_IMU_TO_AOP_MISO
DCS_SENSE_POS
NAND_ANI1_VREF
CAMPMU_TO_RIGEL_ENABLE
SPKAMP_TO_OTHERS_SYNC
PMU_TO_AOP_CLK32K
CAMPMU_TO_JULIET_DVDD_LDO_EN
RIGEL_TO_ISP_INT
COMPASS_TO_AOP_INT
IMU_TO_AOP_DATARDY
SPI_CODEC_TO_AP_MISO
SPKAMP_BOT_ARC_TO_AOP_INT_L
GECKO_TO_AOP_IRQ_L
SPI_AP_TO_CODEC_MOSIAP_TO_CCG2_SWCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
PAD_MTR_ANALOG_TEST_P
PAD_MTR_ANALOG_TEST_N
AP_BI_CCG2_SWDIO
SWD_AOP_TO_MANY_SWCLK
90_PCIE_AP_TO_NAND_REFCLK_N
90_PCIE_AP_TO_NAND_REFCLK_P
90_PCIE_BB_TO_AP_RXD_C_N
90_PCIE_BB_TO_AP_RXD_C_P
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
SYSTEM: Testpoints (Top)17 8
17 8
P2MM-NSM
ROOM=TEST
SM
SMP2MM-NSM
ROOM=TEST
57 43
57 43
SM
ROOM=TEST
P2MM-NSM
SMP2MM-NSM
ROOM=TEST
50 43 42 41 40 13
ROOM=TEST
SMP2MM-NSM
15
15
15
15
15
P2MM-NSMSM
ROOM=TEST
P2MM-NSM
ROOM=TEST
SM
40 11 SM
ROOM=TEST
P2MM-NSM
40 11
ROOM=TEST
SMP2MM-NSM
49 12 SM
P2MM-NSM
ROOM=TEST
30 17
ROOM=TEST
SMP2MM-NSM
23 13
ROOM=TEST
SMP2MM-NSM
48 11
P2MM-NSMSM
ROOM=TEST
43 42 41
P2MM-NSMSM
ROOM=TEST
56 43 41
P2MM-NSM
ROOM=TEST
SM
56 47
P2MM-NSMSM
ROOM=TEST
23
ROOM=TEST
SMP2MM-NSM
19 7 SM
P2MM-NSM
ROOM=TEST
SHORT-10L-0.05MM-SM
SHORT-10L-0.05MM-SMP2MM-NSMSM
ROOM=TEST
P2MM-NSMSM
ROOM=TEST
P2MM-NSMSM
ROOM=TEST
ROOM=TEST
SMP2MM-NSM
P2MM-NSMSM
ROOM=TEST
SMP2MM-NSM
ROOM=TEST
SMP2MM-NSM
ROOM=TEST
12
12
P2MM-NSMSM
ROOM=TEST
ROOM=TEST
SMP2MM-NSM
48 11
P2MM-NSM
ROOM=TEST
SM
48 11
P2MM-NSMSM
ROOM=TEST
23 12 7
P2MM-NSMSM
ROOM=TEST
56 28
ROOM=TEST
P2MM-NSMSM
56 27
ROOM=TEST
SMP2MM-NSM
56 28 SM
ROOM=TEST
P2MM-NSM
ROOM=TEST
SMP2MM-NSM
36 23 9
36 30
P2MM-NSMSM
ROOM=TEST
12
19 SM
ROOM=TEST
P2MM-NSM
SM
ROOM=TEST
P2MM-NSM
19
P2MM-NSMSM
ROOM=TEST
49 23 7
19 11 6
P2MM-NSMSM
ROOM=TEST
23 13
P2MM-NSMSM
ROOM=TEST
15
SMP2MM-NSM
ROOM=TEST
15
SMP2MM-NSM
ROOM=TEST
58 19 13
19 13
49 26
28 13
28 13
28 13
19 8
19 8
13
23 15
23 15
9
9
12 6
23 7
SM
ROOM=TEST
P2MM-NSM
SM
ROOM=TEST
P2MM-NSM
ROOM=TEST
P2MM-NSMSM
ROOM=TEST
SMP2MM-NSM
SM
ROOM=TEST
P2MM-NSM
ROOM=TEST
SMP2MM-NSM
SM
ROOM=TEST
P2MM-NSM
ROOM=TEST
P2MM-NSMSM
ROOM=TEST
P2MM-NSMSM
SM
ROOM=TEST
P2MM-NSM
SMP2MM-NSM
ROOM=TEST
SMP2MM-NSM
ROOM=TEST
ROOM=TEST
SMP2MM-NSM
P2MM-NSM
ROOM=TEST
SM
P2MM-NSMSM
ROOM=TEST
SMP2MM-NSM
ROOM=TEST
37 36
37 36
58
58 20 17
20 17
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
IN
PP
PP
IN
IN
PP
PP
IN PP
IN
IN
IN
IN
IN
PP
PP
IN PP
IN PP
IN PP
IN PP
IN PP
IN PP
IN PP
IN PP
IN PP
IN PP
IN PP
PP
PP
PP
PP
PP
PP
PP
IN
IN
PP
PP
IN PP
IN PP
IN PP
IN PP
IN PP
IN PP
PPIN
IN PP
IN
IN PP
PPIN
PPIN
IN PP
IN PP
IN
PP
IN
PP
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
VIETMOBILE.VN
SELECTED -->
DEFAULT -->
<-------Removed at EVT
No connect
POR -->
No connect
TOP BOARD ONLY CONFIGURATION IS D33 MLB MAVBOTTOM BOARD SELECTS ICE/MAV and D32/D33
BOOT CONFIGBOARD ID
BOOTSTRAPPING:BOARD REV
On mlb_bot
6 OF 60
CKPLUS_WAIVE=SINGLE_NODENET
PP1V8_IO
CKPLUS_WAIVE=SINGLE_NODENET
PP1V8_IO
7.0.0
6 OF 85
051-02545
21
R0602
21
R0623
21
R0622
21
R0601
21
R0620
21
R0621BOARD_REV1
BOARD_ID2
BOARD_REV3
BOARD_ID0
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1
BOARD_ID4
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
PP1V8_IO
MAKE_BASE=TRUE
MAKE_BASE=TRUE
BOARD_REV2
BOARD_REV0
BOOTSTRAPPINGSYNC_DATE=10/13/2016SYNC_MASTER=test_mlb
MF
1%1/32W
ROOM=SOC01005
4.7K
ROOM=SOC01005
5%
MF
1.00K
1/32W
1.00K
1/32WMF
5%
ROOM=SOC01005
NOSTUFF4.7K
01005ROOM=SOC
1/32W1%
MF
1.00K
01005ROOM=SOC
5%
MF1/32W
01005ROOM=SOC
NOSTUFF1.00K
5%
MF1/32W
19 11
19 11
19 11 5
12 5
12
57 12
11
12
55
55
55
55 53 52 44
37 36 34 32 31 30 29 20 19 17
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VIETMOBILE.VN
VDD18_XTAL:1.06-1.17V @ 2mA MAX
CONNECTED TO GND OFFPAGE ON MLB
CONNECTED TO GND OFFPAGE ON MLB
CONNECTED TO GND OFFPAGE ON MLB
VDD33_USB*: 3.14-3.46V @ 12mA MAX
VDD_FIXED_USB*: 0.765V - 0.84V @ 5mA MAX
CTM_TRIGGER
(Analog)
ALT_FUNC
SOC - USB, JTAG, XTAL
USB Reference
VDD18_USB: 1.62V - 1.98V @ 20mA MAX
10 OF 85
7 OF 60
051-02545
7.0.0
GND17
GND17
GND17
PP0V8_SOC_FIXED_S18 9 10 14 17
PP3V3_USB 17
PP1V8_IO15 17
2
1
XW1001
2
1 C1093
4
31
2
Y1000
AW25AY25
AP23
AM14
AM15
AP14
AR14
AP27
AP13
AP15
AT15
AU14
AU15
AW17AY17
G37
AE3
J4
J5
P4
AP32
AP29
AR34AP30
AR35
AP33
AE2
N4N5
P2
AU13
AT14
AT13
AY16AW16
N2N3
AP28
AR33H2
AJ35
U1000
21
FL1092
2
1C1098
21
R1093
21
R1091
21
R1090
2
1 R1001
2
1 C1097
2
1C1096
2
1 C10952
1 C1092
2
1 C1090
2
1 R1010
21R1011
2
1 C10102
1 C1011
2
1 R1000
USB_VBUS_DETECT
AP_TO_PMU_SOCHOT_L
AP_TO_PMU_AMUX_OUT
AP_TO_NAND_FW_STRAP
PMU_TO_AP_HYDRA_ACTIVE_READY
AP_TO_NAND_RESET_L
PMU_TO_SYSTEM_COLD_RESET_L
AP_TO_PMU_TEST_CLKOUT
PMU_TO_SYSTEM_COLD_RESET_L
SWD_DOCK_TO_AP_SWCLK
NC_JTAG_TDINC_JTAG_TDO
SWD_DOCK_BI_AP_SWDIO
NC_JTAG_TRST_L
NC_DBG_USB_ID
PP3V3_USB_DEBUG
90_USB_DBG_DATA_N
NC_AP_USB_ID
PMU_TO_AP_THROTTLE_GPU0_L
PMU_TO_AP_PRE_UVLO_L
AP_TO_PMU_WDOG_RESET
AP_USB_REXT
90_USB_DBG_DATA_P
DBG_USB_VBUS_REXT
AP_USB_REXT
90_USB_AP_DATA_N90_USB_AP_DATA_P
XTAL_AP_24M_OUT
SOC_24M_O
PMU_TO_AP_THROTTLE_GPU1_L
XTAL_AP_24M_IN
XTAL_GND
PMU_TO_AP_THROTTLE_ECORE_LPMU_TO_AP_THROTTLE_PCORE_L
DBG_USB_VBUS_REXT
PP1V8_USB_DEBUG
PP0V8_USB_DEBUG
PP3V3_USB_DEBUG
PP1V8_XTAL
SOC: JTAG,USB,XTALSYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
SHORT-20L-0.05MM-SMROOM=SOC
OMIT
0201
20%4UF
ROOM=SOC
X5R4V
24MHZ-30PPM-9.5PF-60OHM1.60X1.20MM-SM
ROOM=SOCCRITICAL
CRITICALROOM=SOC
CYP-4GB-M-TMJA47A0-C7WLCSP
OMIT_TABLE
240OHM-25%-0.2A-0.9OHM
01005ROOM=SOC
6.3V20%
ROOM=SOC01005
X5R-CERM
0.1UF
0.00
MF
0%1/32W
ROOM=SOC01005
0%
ROOM=SOC01005MF
0.00
1/32W
MF
0%1/32W
01005ROOM=SOC
0.00
49
49
ROOM=SOC01005MF1/32W1%200
0.1UF6.3V20%X5R-CERM
ROOM=SOC
01005
01005ROOM=SOC
X5R-CERM6.3V20%
0.1UF
X5R-CERM6.3V0.1UF
01005ROOM=SOC
20%
20%6.3VX5R-CERM
0.1UF
01005ROOM=SOC
6.3V20%
ROOM=SOC
01005X5R-CERM
0.1UF
49
49
19
19 5
23 5
57 23 15 7
49 23 5
57 23 15 7
26
49
49
23
23
23
55
23
23 12 5
511K1/32W1%
ROOM=SOC01005MF
NOSTUFF
01005ROOM=SOC
1/32WMF
5%
1.00K
23
ROOM=SOC
12PF
01005
16V5%CERM
23
ROOM=SOC01005CERM16V5%12PF
ROOM=SOC01005MF1/32W1%200
7
7
7
7
7
7
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC GND
SYM 1 OF 16
VDD1
8_US
B_DE
BUG
VDD1
8_XT
AL
ANALOGMUX_OUT
TESTMODE
HOLD_RESET
SSD_BFH
CFSB
SSD_RESET*
COLD_RESET*
TST_CLKOUT
CFSB_AON
JTAG_TCK
JTAG_TDIJTAG_TDO
JTAG_TMS
JTAG_TRST*
JTAG_SEL
DBG_USB_REXT
DBG_USB_ID
DBG_USB_VBUS
DBG_USB_DM
XO0XI0
WDOG
VDD3
3_US
B_DE
BUG
VDD3
3_US
B
VDD1
8_US
B
VDD_
FIXE
D_US
B_DE
BUG
VDD_
FIXE
D_US
B
USB_VBUS
USB_REXT
USB_ID
USB_DPUSB_DM
SOCHOT1
GPU_TRIGGER1GPU_TRIGGER0
DROOP
CPU_TRIGGER1CPU_TRIGGER0
DBG_USB_DPBI
BI
BI
IN
OUT
OUT
OUT
IN
IN
IN
IN
BI
BI
OUT
IN
OUT
IN
OUT
IN
IN
IN
VIETMOBILE.VN
SOC - PCIE
PCIe Reset Pull-Downs
PCIE
LIN
K 0
PCIE
LIN
K 4
PCIe BB CLKREQ PU on BB domain
PCIe Clock Request Pull-Ups
Hardwired as Input
PCIE
LIN
K 3
VDD12_PCIE_REFBUF:1.14V - 1.26V @ 30mA MAXVDD12_PCIE:1.14V - 1.26V @ 130mA MAX
VDD_FIXED_PCIE:0.769V - 0.85V @ 105mA MAXVDD_FIXED_PCIE_REFBUF:0.769V - 0.85V @ 65mA MAX
8 OF 60
PP1V8_IO17
PP1V2_SOC10 17
PP0V8_SOC_FIXED_S1 7 9 10 14 17
7.0.0
11 OF 85
051-02545
2
1 C11912
1C11992 1
XW1101
2 1
XW1100
AK27
AL26
AL27
AL30
AL28
AM31
AM29
AU34AV34
AU32AV32
AU30AV30
AU28AV28
AU26AV26
AY35AW35
AY33AW33
AY31AW31
AY29AW29
AY27AW27
AY23AW23
AY22AW22
AW21AY21
AW20AY20
AW19AY19
AT31AR31
R35
R37
T34T35
T36
T37
U34
U35U36
U37
U1000
2
1 R1140
2
1 C1140
2
1 C119821
R1195
21
R1194
2
1 C11942
1 C1193
2
1R1130
2
1R1100
2
1R1131
2
1R1121
2
1R1101
PCIE_AP_TO_BB_PERST_L90_PCIE_AP_TO_BB_TXD_C_N90_PCIE_AP_TO_BB_TXD_C_P
PCIE_AP_TO_WLAN_PERST_L
NC_PCIE2_CLKREQ1_L
NC_PCIE2_RX1_PNC_PCIE2_RX1_N
90_PCIE_NAND_TO_AP_RXD_C_P
90_PCIE_AP_TO_WLAN_TXD_C_P
90_PCIE_BB_TO_AP_RXD_C_P90_PCIE_BB_TO_AP_RXD_C_N
90_PCIE_WLAN_TO_AP_RXD_C_P
90_PCIE_AP_TO_BB_REFCLK_P90_PCIE_AP_TO_BB_REFCLK_N
NC_PCIE2_REF_CLK_N
PCIE_BB_BI_AP_CLKREQ_L
90_PCIE_AP_TO_WLAN_REFCLK_N
PCIE_WLAN_BI_AP_CLKREQ_L
90_PCIE_AP_TO_NAND_TXD_C_N
PCIE_AP_TO_NAND_PERST_LPCIE_AP_TO_BB_PERST_LPCIE_AP_TO_WLAN_PERST_L
PCIE_RCAL_NEG
PCIE_NAND_BI_AP_CLKREQ_LPCIE_WLAN_BI_AP_CLKREQ_L
90_PCIE_AP_TO_WLAN_TXD_C_N
NC_PCIE2_REF_CLK_P
PP1V2_SOC_PCIE_REFBUF_XW
PP0V8_SOC_FIXED_PCIE_REFBUF PP0V8_SOC_FIXED_PCIE_REFBUF_XW
PCIE_NAND_BI_AP_CLKREQ_L
PP1V2_SOC_PCIE_REFBUF
90_PCIE_WLAN_TO_AP_RXD_C_N
90_PCIE_AP_TO_WLAN_REFCLK_P90_PCIE_AP_TO_NAND_REFCLK_P90_PCIE_AP_TO_NAND_REFCLK_N
90_PCIE_NAND_TO_AP_RXD_C_N
NC_PCIE1_RX1_P
90_PCIE_AP_TO_NAND_TXD_C_P
PCIE_AP_TO_NAND_PERST_L
NC_PCIE1_RX1_N
NC_PCIE1_REF_CLK_NNC_PCIE1_REF_CLK_P
NC_PCIE1_TX1_N
NC_PCIE1_PERST_L
NC_PCIE2_TX1_PNC_PCIE2_TX1_N
NC_PCIE2_PERST_L
PCIE_RCAL_POS
NC_PCIE1_TX1_P
NC_PCIE1_CLKREQ1_L
SYNC_DATE=04/07/2017
SOC: PCIE
0.1UF20%6.3V
ROOM=SOC
01005X5R-CERM
ROOM=SOC
1/32WMF
0.00
0%
01005
ROOM=SOC
0.00
MF01005
0%1/32W
01005ROOM=SOC
20%0.1UF
X5R-CERM6.3V
0.1UF
01005
20%6.3VX5R-CERM
ROOM=SOC
ROOM=SOC01005
MF1/32W
5%100K
ROOM=SOC01005
MF1/32W
5%100K
ROOM=SOC01005
MF1/32W
5%100K
ROOM=SOC01005
MF1/32W
5%100K
ROOM=SOC01005
MF1/32W
5%100K
6.3V20%2.2UF
X5R-CERM0201
ROOM=SOC
X5R-CERM
2.2UF20%
6.3V
0201
OMIT
SHORT-20L-0.05MM-SM
ROOM=SOC
OMIT
ROOM=SOC
SHORT-20L-0.05MM-SM
WLCSPCYP-4GB-M-TMJA47A0-C7
17
17 17
17
17 5
17 5
17
17
17
17
17
17
ROOM=SOC01005MF1/32W1%200
ROOM=SOC01005CERM16V
10PF5%
57 8
57
57
57
57 8
58
58 8
58
19 5
19 8
19 5
19 8
19 8
57 8
57 8
19 8
58 8
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
LINK4
LINK1 LINK2
NAND LINK
SYM 2 OF 16
LINK3
PCIE_TX0_NPCIE_TX0_P
PCIE_RX3_P
PCIE_TX3_PPCIE_TX3_N
PCIE_PERST3*PCIE_PERST0*
PCIE_RX0_PPCIE_RX0_N
PCIE_REF_CLK2_P
VDD1
2_PC
IE
PCIE_CLKREQ3*
PCIE_REF_CLK3_PPCIE_REF_CLK3_N
PCIE_CLKREQ2*
PCIE_CLKREQ4*
PCIE_PERST2*
PCIE_PERST4*
PCIE_REF_CLK2_N
PCIE_REF_CLK4_NPCIE_REF_CLK4_P
PCIE_RX2_N
PCIE_RX3_N
PCIE_RX4_NPCIE_RX4_P
PCIE_TX2_NPCIE_TX2_P
PCIE_TX4_NPCIE_TX4_P
VDD_
FIXE
D_PC
IE0
VDD_
FIXE
D_PC
IE1
VDD_
FIXE
D_PC
IE_R
EFBU
F
PCIE_RX2_P
VDD1
2_PC
IE_R
EFBU
FVD
D12_
PCIE
_REF
BUF
PCIE_RCAL_NPCIE_RCAL_P
PCIE_PERST1*
PCIE_TX1_NPCIE_TX1_P
PCIE_RX1_PPCIE_RX1_N
PCIE_REF_CLK1_PPCIE_REF_CLK1_N
PCIE_CLKREQ1*
PCIE_REF_CLK0_NPCIE_REF_CLK0_P
PCIE_CLKREQ0*
IN
IN IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
BI
OUT
OUT
BI
OUT
OUT
VIETMOBILE.VN
Juli
et M
IPI
PLL_DIGOBS_IN_0 and
SOC_DEBUG2
MIPI lanes can all flip polarity for routing purposes
PLL_DIGOBS_IN_1 andISP_FCAM_SPMI_SDATA
SENSOR3_CLK
GNDed offpage on MLB
MIPI Reference
Series Terminations Offpage
VDD_FIXED_MIPID_PLL 0.769V - 0.85V @ TBDmA MAXVDD_FIXED_MIPIC 0.769V - 0.85V @ TBDmA MAXVDD_FIXED_MIPID 0.769V - 0.85V @ TBDmA MAX
MTR_ADC_CLKOUT and SOC_DEBUG3
DISP_SPMI_SCLKDISP_SPMI_SDATA
ALT FUNC's
VDD18_MIPI*:1.62V - 1.98V @ TBDmA MAX
ISP_SPMI_SDATAISP_SPMI_SCLK
SIO_LEAP_MADI_OUT and AOP_LEAP_MADI_OUT
MTR_ADC_DOUT and
NEED MIPI LANE AND POLAIRTY SWAPPING MAP
(Analog)
SOC - MIPI
ISP_FCAM_SPMI_SCLK
ALT FUNC's
SIO_LEAP_MADI_IN and AOP_LEAP_MADI_IN
< CANT SWAP DUE TO BiDi
< CANT SWAP DUE TO BiDi
Disp
lay
MIPI
GNDed offpage on MLB
9 OF 60
PP1V8_IO17 PP0V8_SOC_FIXED_S17 8 10 14 17
GND
GNDGND
GND
GND
GND17
GND
GND
7.0.0
12 OF 85
051-02545
AP9
AM9
F17
AL10
G18
B17B14A14
AU9
AW4
AW5
AW7
AY8
AY6
AY4
AY5
AY7
AW8
AW6
D10
B6
A8
A7
A6
B8
B7
D11
A11
B9
B10
B11
A9
A10
A20A19
C22A18
B20A17
C21A16
D20B13A13C20B19A15B22A21A22A23
AH4
AH3AG4
AA2
AE5
AG2AG3
U1000
2
1R1251
2
1R1250
2
1 C12962
1 C12952
1C12912
1C1290
21R1240
MIPID_REXT
AP_TO_FCAM_JULIET_RIGEL_CLK_RAP_TO_TOUCH_SCAN_CLK
90_MIPI_AP_TO_DISPLAY_CLK_N90_MIPI_AP_TO_DISPLAY_CLK_P
90_MIPI_AP_TO_DISPLAY_DATA2_P
90_MIPI_AP_TO_DISPLAY_DATA1_N
I2C3_ISP_SCL
I2C2_ISP_SCL
AP_TO_TELE_CLK_R
AP_TO_WIDE_CLK_R
I2C3_ISP_SDA
I2C2_ISP_SDA
I2C1_ISP_SDAI2C1_ISP_SCL
I2C0_ISP_SDAI2C0_ISP_SCL
RIGEL_TO_ISP_INTISP_TO_DISPLAY_FLASH_INT
NC_ISP_GPIO_7
ISP_TO_FCAM_SHUTDOWN_L
NC_ISP_GPIO_3SOC_DEBUG2
ISP_TO_TELE_SHUTDOWN_LISP_TO_WIDE_SHUTDOWN_L
NC_DISP_POL
NC_DISP_I2C_SDA
AP_TO_WIDE_CLK
MIPI0C_REXT
90_MIPI_JULIET_TO_AP_DATA0_P90_MIPI_JULIET_TO_AP_DATA0_N
90_MIPI_JULIET_TO_AP_DATA1_N
90_MIPI_JULIET_TO_AP_CLK_P
90_MIPI_AP_TO_DISPLAY_DATA1_P
90_MIPI_AP_TO_DISPLAY_DATA3_P
90_MIPI_AP_TO_DISPLAY_DATA2_N
90_MIPI_JULIET_TO_AP_DATA1_P
MIPI0C_REXTMIPID_REXT
NC_DISP_I2C_SCL
ISP_TO_JULIET_SHUTDOWN_L
SOC_DEBUG3
90_MIPI_AP_TO_DISPLAY_DATA0_N
90_MIPI_AP_TO_DISPLAY_DATA3_N
90_MIPI_JULIET_TO_AP_CLK_N
90_MIPI_AP_TO_DISPLAY_DATA0_P
NC_DISP_BSYNC1
DISPLAY_TO_AP_BSYNC_WATCHDOG
SOC: MIPI
X5R-CERM6.3V
ROOM=SOC01005
0.1UF20%
2.2UF
X5R-CERM6.3V20%
ROOM=SOC0201
2.2UF20%
ROOM=SOC0201
6.3VX5R-CERM
6.3VX5R-CERM
0.1UF20%
ROOM=SOC01005
33.2
1/32WMF
1%
01005ROOM=SOC
31
44
17
17
17
17
17
17
17
57
44
44
44
44
44
44
44
44
44
44
37
37
37
37
37
37
WLCSPCYP-4GB-M-TMJA47A0-C7
36 23 5
44
34
37
53
53
53
5
5
31
32
53
53
53
53
53
2001%
1/32W
ROOM=SOC
MF01005
2001%
1/32WMF
01005ROOM=SOC
9
17
17
9
9
9
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
IN
IN
IN
IN
IN
IN
BI
BI
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
IN
IN
IN
IN
BI
BI
SYM 3 OF 16
MIPI1C_DNDATA0MIPI1C_DPDATA0
DISP_I2C_SCLDISP_I2C_SDA
DISP_POL
DISP_TE
DISP_TOUCH_BSYNC0DISP_TOUCH_BSYNC1
DISP_TOUCH_EB
ISP_GPIO_0ISP_GPIO_1ISP_GPIO_2ISP_GPIO_3ISP_GPIO_4ISP_GPIO_5ISP_GPIO_6ISP_GPIO_7ISP_GPIO_8ISP_GPIO_9
ISP_I2C0_SCLISP_I2C0_SDA
ISP_I2C1_SCLISP_I2C1_SDA
ISP_I2C2_SCLISP_I2C2_SDA
ISP_I2C3_SCLISP_I2C3_SDA
MIPI0C_DNCLK
MIPI0C_DNDATA0
MIPI0C_DNDATA1
MIPI0C_DPCLK
MIPI0C_DPDATA0
MIPI0C_DPDATA1
MIPI0C_REXT
MIPI1C_DNCLK
MIPI1C_DNDATA1
MIPI1C_DPCLK
MIPI1C_DPDATA1
MIPI1C_REXT
MIPID_DNCLK
MIPID_DNDATA0
MIPID_DNDATA1
MIPID_DNDATA2
MIPID_DNDATA3
MIPID_DPCLK
MIPID_DPDATA0
MIPID_DPDATA1
MIPID_DPDATA2
MIPID_DPDATA3
MIPID_REXT
SENSOR0_CLKSENSOR1_CLKSENSOR2_CLK
VDD_
FIXE
D_M
IPIC
VDD_
FIXE
D_M
IPID
VDD_
FIXE
D_M
IPID
_PLL
VDD1
8_M
IPIC
VDD1
8_M
IPID
IN
OUT
OUT
OUT
BI
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
BI
VIETMOBILE.VN
VDD12_PLL_LPDP 1.14V - 1.26V @ 8mA MAXVDD12_LPDP_RX 1.14V - 1.26V @ 60mA MAX
Desense for Wifi frequencies
VDD_FIXED_LPDP_RX 0.769V - 0.85V @ 50mA MAXVDD_FIXED_PLL_LPDP 0.769V - 0.85V @ 4mA MAX
(Analog)
Tele: 3-5Fcam: 6-7
SOC - LPDP
GND'd offpageGND'd offpage
LPD Assigned off page
Wide: 0-2Dan LPDP Lane Assignment
Fcam: 0-1Tele: 5-7Wide: 2-4
Justin LPDP Lane Assignment
10 OF 60
GND17
GND17
90_LPDP_FCAM_TO_AP_D1_N
90_LPDP_FCAM_TO_AP_D0_N90_LPDP_FCAM_TO_AP_D0_P
90_LPDP_TELE_TO_AP_D1_N90_LPDP_TELE_TO_AP_D1_P
90_LPDP_TELE_TO_AP_D0_N
90_LPDP_WIDE_TO_AP_D1_N90_LPDP_WIDE_TO_AP_D1_P
90_LPDP_WIDE_TO_AP_D0_N90_LPDP_WIDE_TO_AP_D0_P
90_LPDP_FCAM_TO_AP_D1_P
90_LPDP_TELE_TO_AP_D0_P
90_LPDP_WIDE_TO_AP_D2_P
PP0V8_SOC_FIXED_S17 8 9 14 17 PP1V2_SOC8 17
90_LPDP_WIDE_TO_AP_D2_N
90_LPDP_TELE_TO_AP_D2_P90_LPDP_TELE_TO_AP_D2_N
7.0.0
13 OF 85
051-02545
AM11
G28
F31
AY11AW11
AY12AW12
AY13AW13
AY14AW14
AU10AT10
AY10AW10
AM12
AM13
AM10
F29
F27
A33B33
B32C32
A31B31
B30C30
B28C28
A27B27
B26C26
A25B25
A29B29
D33D31D29D27D25C24D24D23
AF2AF4
U1000
2
1 R1300
2
1 C1301
2
1 C13952
1 C13962
1 C13902
1 C13912
1 C13922
1 C13932
1 C1394
NC_LPDP_AUX_P
LPDP_FCAM_BI_AP_AUXNC_LPDP_D6_AUXNC_LPDP_D5_AUXNC_LPDP_D4_AUXNC_LPDP_D3_AUXNC_LPDP_D2_AUX
NC_LPDP_TX3_N
NC_LPDP_TX2_PNC_LPDP_TX2_N
NC_LPDP_TX1_PNC_LPDP_TX1_N
NC_LPDP_TX0_N
NC_LPDP_RCAL_P
NC_LPDP_AUX_N
NC_EPD_HPDNC_DP_WAKEUP
NC_LPDP_TX3_P
NC_LPDP_RCAL_N
LPDP_TELE_BI_AP_AUXLPDP_WIDE_BI_AP_AUX
LPDPRX_RCAL_NEG
LPDPRX_RCAL_POS
NC_LPDP_TX0_P
SYNC_DATE=10/13/2016SYNC_MASTER=test_mlb
SOC: LPDP
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
WLCSPCYP-4GB-M-TMJA47A0-C7
34
32
ROOM=SOC01005MF1/32W1%200
10PF5%
CERM01005
16V
ROOM=SOC
X5R-CERM6.3V20%2.2UF
0201ROOM=SOC
X5R-CERM
2.2UF
ROOM=SOC
6.3V20%
0201
6.3VX5R-CERM
2.2UF
ROOM=SOC
20%
0201X5R-CERM6.3V
ROOM=SOC0201
20%2.2UF
20%
01005
6.3V
0.1UF
X5R-CERM
ROOM=SOC ROOM=SOC
X5R01005
10%6.3V
0.01UF
ROOM=SOC
16VNP0-C0G-CERM
15PF5%
01005
31
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
SYM 4 OF 16
LPDPRX_RX_D2_P
LPDP_AUX_P
LPDPRX_RX_D2_N
VDD1
2_PL
L_LP
DP
VDD1
2_LP
DP_T
X
VDD1
2_LP
DP_R
X
VDD_
FIXE
D_PL
L_LP
DP
VDD_
FIXE
D_LP
DP_T
X
VDD_
FIXE
D_LP
DP_R
X
LPDPRX_RX_D7_PLPDPRX_RX_D7_N
LPDPRX_RX_D6_PLPDPRX_RX_D6_N
LPDPRX_RX_D5_PLPDPRX_RX_D5_N
LPDPRX_RX_D4_PLPDPRX_RX_D4_N
LPDPRX_RX_D3_PLPDPRX_RX_D3_N
LPDPRX_RX_D1_PLPDPRX_RX_D1_N
LPDPRX_RX_D0_PLPDPRX_RX_D0_N
LPDPRX_RCAL_PLPDPRX_RCAL_N
LPDPRX_AUX_D7_PLPDPRX_AUX_D6_PLPDPRX_AUX_D5_PLPDPRX_AUX_D4_PLPDPRX_AUX_D3_PLPDPRX_AUX_D2_PLPDPRX_AUX_D1_PLPDPRX_AUX_D0_P
LPDP_TX3PLPDP_TX3N
LPDP_TX2PLPDP_TX2N
LPDP_TX1PLPDP_TX1N
LPDP_TX0PLPDP_TX0N
LPDP_RCAL_PLPDP_RCAL_N
LPDP_AUX_N
EDP_HPDDP_WAKEUP
BI
BI
BI
VIETMOBILE.VN
Hardwired as Board_ID3 -->
AP_PDM_IN1_DAT
SPMI SDATA
ALT FUNC'S
SPI: Route as Daisy-Chain. No T's Allowed
SOC - SERIAL INTERFACES
Lynx
Series Terminations Offpage
AP_PDM_IN2_DAT
Place series terminations close to SoC Pins
.
I2C bus descriptions on 66-68
GPIO SMC INT 9
AP_PDM_OUT0_CLK
GPIO SMC INT 8
AP_PDM_IN2_CLK
SPMI SCLKALT FUNC'SAP_PDM_IN1_CLK
At EVT, check if we can remove
11 OF 60
NC_DWI_PMGR_TO_BACKLIGHT_DATA17
NC_DWI_PMGR_TO_BACKLIGHT_CLK17
I2C4_AP_SDA52
I2C4_AP_SCL52
PP1V8_IO
PP1V8_IO 17
7.0.0
14 OF 85
051-02545
2
1C1490
C3C2B3B2
A1
B1A2 C1
A3
U1401
21R1461
F37
AF36
F35E37
AD4AD2AD3AD5
V35W34W35V37
AH37AH34AH35AH36
AF35AG35AG37AF34
AT20AR23
AR24AU20
AT24AU24
W36
AF37
AE35
AE36AE37
AE34
AC37
AB35
AA37AB36
AB34
AA35
Y34
Y36Y35
Y37
AD35
AC34
AC36AC35
AD37
G34G35
M5M4
L34K37
K5L2
D17C15
J3J2
AP21
U1000
21
R1464
21R1462
21R1465
21R1480
21R1460
CCG2_TO_SMC_INT_L
I2S_AP_TO_CODEC_ASP3_BCLK
I2C3_AP_SCL
I2C2_AP_SDA
I2C1_AP_SDAI2C1_AP_SCL
I2C0_AP_SDA
I2C4_AP_SDA
I2S_AP_TO_SPKAMP_TOP_MCLK_R
I2S_BB_TO_AP_LRCLKI2S_BB_TO_AP_BCLK
CODEC_TO_AP_INT_L
SPI_AP_TO_RACER_MOSI
AP_TO_CCG2_SWCLK
SPI_AP_TO_CODEC_SCLK
I2C4_AP_SCL
I2C3_AP_SDA
I2S_CODEC_ASP3_TO_AP_DIN
I2C0_SMC_SCL
I2C0_AP_SCL
SPI_CODEC_TO_AP_MISO
I2C0_SMC_SDA
AP_TO_NAND_SYS_CLK_R
NC_I2S1_MCLK
AP_BI_CCG2_SWDIONC_I2S1_BCLK
I2C2_AP_SCL
AP_TO_RACER_REF_CLK_R
I2S_AP_TO_CODEC_MCLK1
I2C1_SMC_SDAI2C1_SMC_SCL
IKTARA_TO_SMC_INT
I2S_BB_TO_AP_DIN
I2S_AP_TO_CODEC_ASP3_LRCLK
I2S_AP_TO_CODEC_MCLK1_R
I2S_AP_TO_CODEC_ASP3_DOUT
SPI_AP_TO_CODEC_MOSI
AP_TO_NAND_SYS_CLK
PMU_TO_AP_DOUBLE_CLICK_DET_L
SPI_AP_TO_CODEC_CS_LSPI_AP_TO_CODEC_SCLK_R
NC_SPI4_MISO
NC_SPI4_SCLK
NC_SPI2_MISO
NC_SPI2_SCLKNC_SPI2_MOSI
NC_I2S3_LRCLKNC_I2S3_BCLKNC_I2S3_MCK
NC_AP_PDM_OUT0_DAT
SPI_RACER_TO_AP_MISO
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
NC_I2S3_DINNC_I2S3_DOUT
SPI_AP_TO_RACER_CS_LSPI_AP_TO_RACER_SCLK
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0_R
I2S_AP_TO_BB_DOUT
NC_SPI2_CS_L
I2S_AP_TO_SPKAMP_TOP_MCLK
SPI_AP_TO_RACER_SCLK_R
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
SYNC_MASTER=test_mlb SYNC_DATE=04/05/2017
SOC: SERIAL
X5R-CERM0201
ROOM=SOC
2.2UF6.3V20%
STLNXA1L9YZ2
CRITICALWLCSP
0.00
01005ROOM=SOC
0%
MF1/32W
58
WLCSPCYP-4GB-M-TMJA47A0-C7
40
48 5
48 5
42 33.2
1/32W
ROOM=SOC
1%
MF01005
40
40
0%
MF
0.00
01005ROOM=SOC
1/32W40
40 5
40 5
52
52
23
57
57
57
57
19 6 0.00
0%1/32W
ROOM=SOC
MF01005
17
60
48 5
54
54
58 52
58 52
19 6 5
19 6
19
60 54
52
52
52
60 54
52
52
52
58
6
40
58
58
40
40
40
0.00
MF
ROOM=SOC
0%1/32W
01005
33.2
1%1/32WMF
01005ROOM=SOC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VSS
NCSDA NCSCL
VCC
OUT
SYM 6 OF 16
I2S1_DOUTI2S1_DIN
AP_PDM_OUT0_DAT
CLK24M_OUT
DWI_CLKDWI_DO
I2C0_SCLI2C0_SDA
I2C1_SCLI2C1_SDA
I2C2_SCLI2C2_SDA
I2C3_SCLI2C3_SDA
I2C4_SCLI2C4_SDA
I2S0_BCLK
I2S0_DINI2S0_DOUT
I2S0_LRCK
I2S0_MCK
I2S1_BCLKI2S1_LRCK
I2S1_MCK
I2S2_BCLK
I2S2_DINI2S2_DOUT
I2S2_LRCK
I2S2_MCK
I2S3_BCLK
I2S3_DINI2S3_DOUT
I2S3_LRCK
I2S3_MCK
NAND_SYS_CLK
SMC_I2CM0_SCLSMC_I2CM0_SDA
SMC_I2CM1_SCLSMC_I2CM1_SDA
SMC_UART0_RXDSMC_UART0_TXD
SPI0_MISOSPI0_MOSISPI0_SCLKSPI0_SSIN
SPI1_MISOSPI1_MOSISPI1_SCLKSPI1_SSIN
SPI2_MISOSPI2_MOSISPI2_SCLKSPI2_SSIN
SPI3_MISOSPI3_MOSISPI3_SCLKSPI3_SSIN
SPI4_MISOSPI4_MOSISPI4_SCLK
NCNC
IN
OUT
BI
OUT
OUT
OUT
OUT
OUT
IN
BI
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
BI
BI
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
VIETMOBILE.VN
GPIOs are wired on page 70
ALT FUNCSOC_DEBUG1
SOC - GPIO INTERFACES
12 OF 60
BOARD_REV255
NC_UART_WLAN_TO_AP_RXDNC_UART_AP_TO_WLAN_RTS_LNC_UART_WLAN_TO_AP_CTS_L
DISPLAY_TO_AP_PANEL_ID55
CAMPMU_TO_AP_IRQ_L55
AP_TO_NFC_DEV_WAKE55
AP_TO_BB_PEAK_POWER_INDICATOR55
BB_TO_AP_RESET_DETECT_L55
BOARD_REV055
AP_TO_SPKRAMP_TOP_RESET_L55
AP_TO_GNSS_TIME_MARK55
SPKRAMP_TOP_TO_AP_INT_L55
BB_TO_AP_COEX55
BT_TO_AP_TIME_SYNC55
AP_TO_BB_RESET_L55
BOARD_REV155
BB_TO_AP_PEAK_POWER_INDICATOR55
AP_TO_BB_COREDUMP_TRIG55
AP_TO_BB_COEX55
AP_CANARY255
NC_AP_GPIO2755
NC_AP_GPIO2855
AP_TO_RACER_RESET_L55
GNSS_TO_AP_LOW_PWR_IND55
BOARD_REV355
AP_TO_BBPMU_RADIO_ON_L55
AP_CANARY155
NC_AP_GPIO855
PMU_TO_AP_BUTTON_VOL_UP_L55
NC_UART_AP_TO_WLAN_TXD
AP_TO_CAMPMU_RESET_L55
PP1V8_IO
AP_TO_BT_DEVICE_WAKE55
AP_TO_PMU_AMUX_SYNC55
AP_TO_NFC_FW_DWLD_REQ55
7.0.0
15 OF 85
051-02545
L36L35
C18D19
W5W4W3Y4
N34M37M35L37
P35P34N36N35
V5V4V3V2
P37P36
R3R4R5
M2M3
AL35AL34
AK37AK36
AM37AM36
AA5K4
AC4AB5AC2AB4H37J35D14C14D13D16AB3J37K34G36K35K36
L4H34H35
K2AA4AA3
Y2U2U4T2T3T4K3
C17
C16
T5R2
H36C13
U1000
2
1 R1501MTR_RREF_PMTR_RREF_N
BOARD_ID0
UART_AP_TO_NFC_RTS_LUART_NFC_TO_AP_RXD
UART_GNSS_TO_AP_CTS_LUART_AP_TO_GNSS_RTS_L
DFU_STATUS
PAD_MTR_ANALOG_TEST_P
NC_PAD_MTR_VREF_NNC_PAD_MTR_VREF_P
PMU_TO_AP_BUTTON_POWER_KEY_LPMU_TO_AP_BUTTON_VOL_DOWN_L
PMU_TO_AP_PRE_UVLO_LNC_TMR32_PWM1
AP_TO_WLAN_TIME_SYNC
UART_NFC_TO_AP_CTS_L
UART_GNSS_TO_AP_RXDUART_AP_TO_GNSS_TXD
NC_UART6_RXD_LNC_UART6_TXD_L
UART_ACCESSORY_TO_AP_RXDUART_AP_TO_ACCESSORY_TXD
UART_AP_DEBUG_RXD
UART_AP_TO_NFC_TXD
UART_AP_DEBUG_TXD
UART_BT_TO_AP_RXDUART_AP_TO_BT_RTS_LUART_BT_TO_AP_CTS_L
UART_AP_TO_BT_TXD
PAD_MTR_ANALOG_TEST_N
BOARD_ID4BOARD_ID2
HYDRA_TO_AP_FORCE_DFU
SYNC_MASTER=test_mlb SYNC_DATE=04/05/2017
SOC: GPIO & UART
17
17
17
17
WLCSPCYP-4GB-M-TMJA47A0-C7
57
57
57
57
57
49
49
58
58
58
58
39.2K1%1/32WMF01005
ROOM=SOC
5
5
5
57 49
23 7 5
57 6
6
6 5
57
57
49
57
57
49 5
23
23
6
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
IN
OUT
IN
SYM 5 OF 16
GPIO[25]
GPIO[14]GPIO[13]GPIO[12]
UART1_TXD
UART3_RTS*UART3_RXDUART3_TXD
UART4_CTS*UART4_RTS*
GPIO[21]
BOARD_ID0BOARD_ID1BOARD_ID2BOARD_ID4
DFU_STATUS
FORCE_DFU
GPIO[0]GPIO[1]
GPIO[10]GPIO[11]
GPIO[15]GPIO[16]GPIO[17]GPIO[18]GPIO[19]
GPIO[2]
GPIO[20]
GPIO[22]GPIO[23]GPIO[24]
GPIO[26]GPIO[27]GPIO[28]GPIO[29]
GPIO[3]
GPIO[30]
GPIO[4]GPIO[5]GPIO[6]GPIO[7]GPIO[8]GPIO[9]
PAD_MTR_ANALOG_TEST_NPAD_MTR_ANALOG_TEST_P
PAD_MTR_RREF_NPAD_MTR_RREF_P
PAD_MTR_VREF_NPAD_MTR_VREF_P
REQUEST_DFU1REQUEST_DFU2
TMR32_PWM0TMR32_PWM1TMR32_PWM2
UART0_RXDUART0_TXD
UART1_CTS*UART1_RTS*
UART2_CTS*UART2_RTS*UART2_RXDUART2_TXD
UART3_CTS*
UART4_RXDUART4_TXD
UART6_RXDUART6_TXD
UART7_RXDUART7_TXD
UART1_RXD
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
VIETMOBILE.VN
V
I2C bus descriptions on 66-68
1.62V - 1.98V @ 10mA MAX
AOP_PDM_CLK2
AOP_PDM_IN2_CLKAOP_PDM_IN2_DAT
ALT FUNC's
SMC_UART1_RXD
SCM_SPI CS & Trig
AOP_PDM_CLK2ALT FUNC
AOP_LPPLL
|
|
<
SOC - AOP
V
||
AOP_PDM_CLK3
<--
<
ALT FUNC's
V
SCM_I2CM0 TRIGGER
ALT FUNC's|
AOP_PDM_IN1_CLK
SCM_I2CM1 TRIGGER
SMC_UART1_TXD
AOP_PDM_CLK4
ALT FUNC's
NUB_PDM_CLK1
13 OF 60
PP1V8_S215 17
POTASSIUM_TO_AOP_INT56
COMPASS_TO_AOP_INT56
IMU_TO_AOP_DATARDY56
SPI_AOP_TO_IMU_CS_L56
AOP_TO_SPKAMP_BOT_RESET_L56
SPI_AOP_TO_PHOSPHORUS_CS_L56
PHOSPHORUS_TO_AOP_INT56
ROMEO_TO_AOP_B2B_DETECT56
HALL_CASE_TO_AOP_NORTH_L 56
AOP_TO_GECKO_RESET_L
SPKAMP_BOT_ARC_TO_AOP_INT_L56
ALS_TO_AOP_INT_L56
AOP_TO_BBPMU_COEX56
RACER_TO_AOP_INT_L56
AOP_TO_CODEC_RESET_L56
NC_AOP_FUNC856
HALL_FLAP_TO_AOP_IRQ_L56
NFC_TO_AOP_HOST_WAKE56
HALL_CASE_TO_AOP_SOUTH_L56
PROX_BI_AOP_INT_L56
AOP_TO_HALOGEN_AFE_EN56
AOP_TO_CODEC_CLP_EN56
GECKO_TO_AOP_IRQ_L 56
NC_AOP_FUNC1256
NC_AOP_FUNC1156
NC_AOP_FUNC1056
IMU_TO_AOP_INT56
7.0.0
16 OF 85
051-02545
2
1 C1690
AP20AM
25AM
23AM
19AM
17
B16C19
AP26
AP22AR26
AP24
AR29AR21
AR27
AP25
AT4AP4
AT16AU16
AR6AR5
AP16AP7AP6
AT23AU22
AU23AT22AT21
AU12AU6
AT19AU5
AR20AU7
AU8
AU19AU11
AT5AR17
AP5AP17
AT12AU4
AT11AU18
AT8AT18AP19
AT9AR18
AT7AR12AR15AU17AR11AP12AR9
AP18AP11AT17AR8AT6
AP10AP8
AU21
U1000
21
R1605
21
R1604
21
R1601
21
R1603
2
1 C1691
21R1602
NC_SWD_TMS3
AOP_TO_DDR_SLEEP1_READY_PROBE
SWD_AP_BI_NAND_SWDIO
I2C0_AOP_SCLI2C0_AOP_SDA
AOP_TO_WLAN_CONTEXT_A
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
I2S_AOP_TO_CODEC_ASP2_DOUT
I2S_AOP_TO_CODEC_MCLK2_RI2S_AOP_TO_CODEC_ASP2_LRCLK
I2S_CODEC_ASP2_TO_AOP_DINI2S_AOP_TO_CODEC_ASP2_BCLK
UART_AOP_TO_RACER_TXD
UART_AOP_TO_BB_TXD
SPI_IMU_TO_AOP_MISOSPI_AOP_TO_IMU_MOSISPI_AOP_TO_IMU_SCLK_R
UART_BB_TO_AOP_RXD
UART_RACER_TO_AOP_RXD
AOP_TO_WLAN_CONTEXT_B
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT
SPMI_PMGR_TO_PMU_SCLK
HYDRA_TO_NUB_DOCK_CONNECT
SWD_AOP_BI_BB_SWDIOSWD_AOP_BI_RACER_SWDIO
SPMI_PMGR_TO_PMU_SCLK_R
SWD_AOP_TO_MANY_SWCLK
HYDRA_TO_NUB_INT
SPMI_PMU_BI_PMGR_SDATA
PMU_TO_AOP_CLK32K
I2C1_AOP_SDAI2C1_AOP_SCL_SOC
CODEC_TO_AOP_GPIO2
SPI_AOP_TO_IMU_SCLK
I2S_AOP_TO_CODEC_MCLK2
AOP_TO_CODEC_GPIO1
SOC: AOP
CYP-4GB-M-TMJA47A0-C7WLCSP
50 43 42 41 40
1%
ROOM=SOC
MF1/32W
01005
49.9
50 43 42 41 40 5
ROOM=SOC
49.9
MF1/32W1%
01005
50 43 40
40
MF
ROOM=SOC
1%
33.2
01005
1/32W
23 0.00
1/32WMF
0%
01005ROOM=SOC
23 5
43 42 41 40
49
49
40
23 5
58 19 5
57
58
19 5
54
54
54
54
0.1UF20%6.3VX5R-CERM01005ROOM=SOC
40
40
40
40
1%
01005MF
33.2
1/32W
ROOM=SOC
40
28 5
28 5
57
57
58
58
58
58
28 5
5
ROOM=SOC0201X5R-CERM
2.2UF20%6.3V
56
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 7 OF 16
VDDIO18_AOP
SWD_TMS3SWD_TMS2
RT_CLK32768
NUB_SWD_TMS1NUB_SWD_TMS0
NUB_SWD_TCK_OUT
NUB_SPMI_SDATANUB_SPMI_SCLK
NUB_DOCK_CONNECT
NUB_DOCK_ATTENTION
AOP_UART2_TXDAOP_UART2_RXD
AOP_UART1_TXDAOP_UART1_RXD
AOP_UART0_TXDAOP_UART0_RXD
AOP_SPI_SCLKAOP_SPI_MOSIAOP_SPI_MISO
AOP_PDM_OUT0_CLKAOP_PDM_DATAOUT
AOP_PDM_DATA1AOP_PDM_DATA0
AOP_PDM_CLK0
AOP_I2S1_MCKAOP_I2S1_LRCKAOP_I2S1_DOUT
AOP_I2S1_DINAOP_I2S1_BCLK
AOP_I2S0_MCKAOP_I2S0_LRCK
AOP_I2S0_DOUT
AOP_I2S0_DINAOP_I2S0_BCLK
AOP_I2CM1_SDAAOP_I2CM1_SCL
AOP_I2CM0_SDAAOP_I2CM0_SCL
AOP_FUNC[9]AOP_FUNC[8]AOP_FUNC[7]AOP_FUNC[6]AOP_FUNC[5]AOP_FUNC[4]AOP_FUNC[3]
AOP_FUNC[22]AOP_FUNC[21]AOP_FUNC[20]
AOP_FUNC[2]
AOP_FUNC[19]AOP_FUNC[18]AOP_FUNC[17]AOP_FUNC[16]AOP_FUNC[15]AOP_FUNC[14]AOP_FUNC[13]AOP_FUNC[12]AOP_FUNC[11]AOP_FUNC[10]
AOP_FUNC[1]AOP_FUNC[0]
AON_SLEEP1_RESET*
IN
IN
OUT
OUT
OUT
BI
IN
IN
IN
IN
IN
OUT
BI
BI
BI
OUT
BI
OUT
BI
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
VIETMOBILE.VN
0.570V @ 3.1A MAX
Remote sense XW's for Buck0 Buck1 and Buck11 live off pagefor dev board compapability
SOC - CPU, GPU & SOC RAILS
VDD_FIXED_MTR 0.769V - 0.85V @ TBDmAVDD_FIXED_ECPU: 0.769V - 0.85V @ 5mA
0.975V @ 1.4A MAX0.765V @ 0.33A MAX
VDD_LOW: 0.691V - 0.756V @ 75mA MAX
1.06V @ 0.6A MAX0.725V @ 0.41A MAX0.685V @ 0.39A MAX
0.905V @ 12.9A MAX0.527V @ 2.4A MAX
1.06V @ 13.8A MAX
1.02V @ 2.1A MAX
1.06V @ 14.5A MAX
0.517V @ 0.62A MAX
0.945V @ 2.9A MAX0.626V @ 1.2A MAX
VDD_FIXED_PLL_ANE: 0.81V @ 5mAVDD_FIXED_PLL_GPU: 0.81V @ 5mAVDD_FIXED_PLL_SOC: 0.81V @ 9mA
VDD_FIXED_PLL_DDR0: 0.81V @ 8mA
VDD12_PLL_SOC: 1.14 - 1.26V @ 8mA MAX
VDD_FIXED_PCPU: 0.81V @ 5mA
VDD_FIXED_PLL_DDR2: 0.81V @ 8mAVDD_FIXED_PLL_DDR3: 0.81V @ 8mA
0.595V @ 2.1A MAX
0.783V @ 4.2A MAX0.661V @ 2.6A MAX
VDD_FIXED_PLL_DDR1: 0.81V @ 8mAVDD_FIXED_PLL_LPDP: 0.81V @ 2mA
0.725V @ 6.3A MAX
VDD_LOW_ULPPLL: 0.691V - 0.756V @ 0.3mA MAX
VDD12_PLL_GPU: 1.14 - 1.26V @ 7mA MAXVDD12_PLL_ECPU: 1.14 - 1.26V @ 7mA MAXVDD12_PLL_PCPU: 1.14 - 1.26V @ 7mA MAXVDD12_PLL_ANE: 1.14 - 1.26V @ 7mA MAX
14 OF 60
PP0V8_SOC_FIXED_S1 14 17
PP1V2_SOC 17
PP0V7_VDD_LOW_S217
PP_CPU_SRAM17
PP0V8_SOC_FIXED_S1 14 17
PP0V8_SOC_FIXED_S1 14 17
PP0V8_SOC_FIXED_S1 7 8 9 10 17
PP_SOC_S1 17
PP_GPU 17
PP_GPU_SRAM17
PP_CPU_ECORE 17
PP_CPU_PCORE17
7.0.0
17 OF 85
051-02545
2
1 C1794
2
1 C1723
2
1 C17312
1 C1730
2
1C1751
2
1 C17422
1C1750
Y27Y25Y21Y19W30W28W24W22W18V27V25V21V19V15U30U28U24U22U18U16U8T27T25T21T19T15R30R28R24R22R18R16P27P25P19P15N28N18N16M27L28K27J28
J10H27G19F22
AK25AK21AK19AJ28AJ24AJ22AJ18AJ16AH27AH25AH19AH10AG28AG24AG22AG18AF27AF25AF21AF19AE28AE18AD27AD25AD21AD19AC28AC24AC22AC18AB27AB25AB21AB19AA30AA28AA24AA22AA18AA8
U1000
U11
Y17Y9
AL20
M23
N26N24N22
V9
AE24AE22
N29D7AJ29AH5
AD23
U12AD31
AD22
W16W14W10V13V11
AK15AK13AJ10AG10AF15AF13AE16AE12AE10AD17AD9
AM21
AL24AL22AL18AL16
M19M15G22K21K13J24H19H15H11F13
N20M25M21M17M13L26L24L22L20L14L12L10K23K15K11J26H23J22J20J14J12H25H21H17H13G26G24K25G20G16G14G12G10F15F11
M11
T13T9P13P9N10
W12U10N12
AK11AH15AF11AE14AB17AB9
AE23
U13M12
AD24
U1000
21
R1702
2
1 C174321
R1701
2
1 C1765
2
1 C17222
1 C17212
1 C1720
4
3
2
1
C1793
4
3
2
1
C1792
4
3
2
1
C1791
4
3
2
1
C1736
4
3
2
1
C1735
4
3
2
1
C1734
4
3
2
1
C1733
4
3
2
1
C1732
4
3
2
1
C1739
4
3
2
1
C1738
4
3
2
1
C1737
4
3
2
1
C1782
4
3
2
1
C1781
4
3
2
1
C1773
4
3
2
1
C1772
2
1 C1703
4
3
2
1
C1707
4
3
2
1
C1713
2
1
C1702
4
3
2
1
C1706
4
3
2
1
C1705
4
3
2
1
C1712
4
3
2
1
C1711
4
3
2
1
C1704
4
3
2
1
C1710
4
3
2
1
C1709
4
3
2
1
C1708
4
3
2
1
C1764
2
1 C1761
4
3
2
1
C1763
4
3
2
1
C1762
2
1 C1760
PP0V7_VDD_LOW_FLPPLL_R
PP0V7_VDD_LOW_ULPPLL_R
SOC: POWER (1/3)
0201ROOM=SOC
X5R-CERM
2.2UF20%6.3V
6.3V20%
X5R-CERMROOM=SOC
2.2UF
0201
0201
2.2UF6.3V20%X5R-CERM
ROOM=SOC
2.2UF20%6.3VX5R-CERM0201
ROOM=SOC
0201
4VX5R
20%4UF
ROOM=SOC 20%
0201ROOM=SOC
X5R4V
4UF
X5R4V
14UF
0402-D2X-1
ROOM=SOC
20%
20%4UF
ROOM=SOC
X5R4V
0201
CYP-4GB-M-TMJA47A0-C7WLCSP
CYP-4GB-M-TMJA47A0-C7WLCSP
1/32W
100
ROOM=SOC01005
5%
MF
20%6.3V
0.47UF
01005X5R
ROOM=SOC
5%1/32W
01005MF
10
ROOM=SOC
X5R4V
ROOM=SOC
0201
4UF20%
X5R
ROOM=SOC
4V
0201
4UF20%
20%6.3VX5R-CERM01005ROOM=SOC
0.1UF
01005ROOM=SOC
6.3V20%0.1UF
X5R-CERM20%0.1UF
01005ROOM=SOC
X5R-CERM6.3V
ROOM=SOC
14UF4VX5R
0402-D2X-1
20%
X5R0402-D2X-1
14UF4V
ROOM=SOC
20%
0402-D2X-1X5R
ROOM=SOC
14UF4V20%
ROOM=SOC
14UF20%
X5R4V
0402-D2X-1
0402-D2X-1X5R
ROOM=SOC
4V
14UF20%
0402-D2X-1
4V
ROOM=SOC
X5R
14UF20%20%
0402-D2X-1X5R
14UF4V
ROOM=SOCROOM=SOC
14UF
0402-D2X-1X5R4V20%
X5R
ROOM=SOC
14UF
0402-D2X-1
4V20%
4V
14UF
ROOM=SOC
20%
X5R0402-D2X-1
ROOM=SOC
X5R4V
0201
4UF20%
0402-D2X-1
20%14UF4VX5R
ROOM=SOC
14UF
X5R4V
ROOM=SOC
20%
0402-D2X-1
20%
X5R4V
ROOM=SOC
0402-D2X-1
14UF
0402-D2X-1
ROOM=SOC
14UF
X5R4V20%
4V
ROOM=SOC
X5R0402-D2X-1
14UF20%
14UF4VX5R
ROOM=SOC
20%
0402-D2X-1X5R
ROOM=SOC
4V
14UF20%
0402-D2X-1
4V
ROOM=SOC
X5R0201
4UF20%
X5R4V
14UF
ROOM=SOC
0402-D2X-1
20%
0402-D2X-1X5R
ROOM=SOC
4V20%14UF
ROOM=SOC
4VX5R0201
4UF20%
14UF
X5R
ROOM=SOC
0402-D2X-1
4V20%
ROOM=SOC
4V
0402-D2X-1
20%14UF
X5R
14UF20%
X5R
ROOM=SOC
0402-D2X-1
4VX5R4V20%
0402-D2X-1
14UF
ROOM=SOC
0402-D2X-1
4VX5R
14UF
ROOM=SOC
20%
X5R4V20%
ROOM=SOC
0402-D2X-1
14UF
0402-D2X-1
4V
14UF
X5R
ROOM=SOC
20%14UF
0402-D2X-1
4VX5R
20%
ROOM=SOC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 9 OF 16
VDD_SOC
SYM 8 OF 16
VDD_LOW
VDD_CPU_SRAM
VDD_ECPU
VDD_FIXED_MTRVDD_FIXED_PCPU
VDD_FIXED_PLL_ANE
VDD_FIXED_PLL_DDR0VDD_FIXED_PLL_DDR1VDD_FIXED_PLL_DDR2VDD_FIXED_PLL_DDR3
VDD_FIXED_PLL_GPUVDD_FIXED_PLL_SOC
VDD_GPU
VDD_GPU_SRAM
VDD_LOW_FLPPLLVDD_LOW_ULPPLL
VDD_PCPU
VDD12_PLL_ANE
VDD12_PLL_ECPUVDD12_PLL_GPU
VDD12_PLL_PCPU
VDD12_PLL_SOC
VDD_FIXED_ECPU
VIETMOBILE.VN
VDD2_DDR*: 1.06V - 1.17V @ 2.2A MAX
VDD1_DDR*: 1.70V - 1.95V @ 220mA MAX
VDD12_PLL_DDR* Total: 1.14V - 1.26V @ 10mA MAX
rdar#: 29793211, This pin replaces the 4 DDR* sys alive pins1.8V @ 5.3mA MAX (CPU)1.8V @ 1.1mA MAX (GPU)1.8V @ 3.3mA MAX (SOC)1.8V @ 0.3mA MAX (AMUX)
1.8V @ 1mA MAX (FMON)1.8V @ 0.03mA MAX (ULPPLL)
1.8V @ 1.5mA MAX (TSADC_SOC)
Current included in VDD2
0.761V @ 600mA MAX0.912V @ 950mA MAX
Place caps on SoC Corners
0.631V @ 350mA MAX
SOC - CPU, GPU & SOC RAILS
0.8V @ 900mA MAX
GRP2 IS AOP
1.8V @ 0.03mA MAX (MTR)
VDDQL* TOTAL: 0.573V - 0.63V @ 620mA MAX
DDR IMPEDANCE CONTROL
1.8V @ 75mA MAX (GRP)
Place caps on SoC Corners
15 OF 60
PP1V8_S2 17
PP1V1_S2 15 17
PP1V8_IO 7 15 17
PP1V1_S215 17
PP0V8_SOC_FIXED_S117
PP0V6_VDDQL_S115 17
PP1V8_S2 13 17
PP1V2_SOC 17
PP_DCS_S117
PP0V6_VDDQL_S115 17
PP1V8_IO 7 15 17
PP1V8_IO17
7.0.0
18 OF 85
051-02545
2
1 C17412
1C1871
21
R1801
AL14
AD30
F25F23F21
Y31V31T31P31
AB31
V8M8
AD8
AL21
M9D34AE29
G15
N13U14AE8AA17AF16P14
AC29
AC30R8
AJ34
U1000
C4
A4
AL3
V38T38P38M31H38H31F38D38
V1T1P1L8H1F8F1D1
AU38AR38AN38AK31AG38AF31AE38AC38
AU1AR1AN1AL8AG8AG1AE1AC1
N30D6AK29AG5
C35G5
AN34AL5
M30G30
K9F9
AK30AE30
AL9AF9
W37N38L38J38D36
W2N1L1J1D3
AU36AM38AK38AH38AB37
AU3AM1AK1AH1AB2
Y38C37
Y1C2
AV37AA38
AV2AA1
N37
D35G4AN35
AH2
AL4
U1000
B4AH20AH16P22
AH21AG16
P21
Y29Y23W26W20W8V29V23V17U26U20T29T23T17R26R20R14P29P23P17N14N8M29K29H29
F19AL12AK23AK17AJ26AJ20AH29AH23AH17AG26AG20AF29AF23AF17AE26AE20AD29AC26AC20AC8
AB29AB23AA26AA20
U1000
2
1C1810
21
R1802
2
1C18112
1C18122
1C1813
2
1 C1843
2
1 C18422
1 C18412
1 C1840
2
1 C18532
1 C18522
1 C18512
1 C1850
2
1 R1870
2
1 R1871
2
1 R1863
2
1 R1862
2
1 R1861
2
1 R1860
2
1 C18632
1 C18622
1 C18612
1 C1860
2
1 C18332
1 C18322
1 C18312
1 C1830
4
3
2
1
C1801
2
1 C18052
1 C18042
1 C18032
1 C1802
PP1V8_FMON_R
CPU_PCORE_SENSE_POS
GPU_SENSE_POS
DDR3_ZQDDR0_ZQ
DDR3_RREFDDR2_RREFDDR1_RREFDDR0_RREF
CPU_PCORE_SENSE_NEGGPU_SENSE_NEG
VDDQL_DCS_SENSE_NEG
SOC_SENSE_NEG
PP1V8_ULPPLL_R
SOC_SENSE_POS
PMU_TO_SYSTEM_COLD_RESET_L
VDDQL_SENSE_POS
DCS_SENSE_POS
SOC: POWER (2/3)
ROOM=SOC
4VX5R0201
4UF20%
0201
4VX5RROOM=SOC
4UF20%
2.2UF6.3V20%
0201ROOM=SOC
X5R-CERM
ROOM=SOC
49.901005
1%MF
1/32W
CYP-4GB-M-TMJA47A0-C7WLCSP
WLCSPCYP-4GB-M-TMJA47A0-C7
WLCSPCYP-4GB-M-TMJA47A0-C7
20%4V
0402-0.1MMX5R
ROOM=SOC
26UF
01005ROOM=SOC
100
1/32W5%
MF
ROOM=SOC
4VX5R0201
4UF20%
20%4UF
0201X5R4V
ROOM=SOC0201
20%4UF
ROOM=SOC
4VX5R X5R
20%4UF
0201
4V
ROOM=SOC
X5R-CERMROOM=SOC
2.2UF6.3V
0201
20%
ROOM=SOC
X5R
4UF4V
0201
20%
X5R-CERMROOM=SOC
2.2UF6.3V
0201
20%X5R-CERM
2.2UF
ROOM=SOC
6.3V
0201
20%2.2UF
X5R-CERMROOM=SOC
6.3V
0201
20%
4VX5R
ROOM=SOC0201
4UF20%
X5R4V
ROOM=SOC0201
4UF20%
ROOM=SOC
4VX5R0201
4UF20%
ROOM=SOC
4VX5R0201
4UF20%
ROOM=SOC01005MF1/32W1%240
ROOM=SOC01005MF1/32W1%240
ROOM=SOC01005MF1/32W1%240
ROOM=SOC01005MF1/32W1%240
ROOM=SOC01005MF1/32W1%240
ROOM=SOC01005MF1/32W1%240
4VX5RROOM=SOC0201
4UF20%
X5R4V
ROOM=SOC0201
4UF20%
4VX5RROOM=SOC0201
4UF20%
X5R4V
ROOM=SOC0201
4UF20%
4VX5R
ROOM=SOC
4UF20%
0201
X5R4V
ROOM=SOC0201
4UF20%
X5R4V
0201
4UF20%
ROOM=SOC
X5R4V
ROOM=SOC0201
4UF20%
X5R4V
ROOM=SOC0201
4UF20%
4V
ROOM=SOC
0402-D2X-1X5R
20%14UF
23 5
23 5
5
5
5
5 5
57 23 7
5
5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 12 OF 16
VDDIO18_GRP3
VDDIO18_MTR
VDDIO18_GRP1
VDD18_ULPPLL
VDD18_TSADC_SOC2VDD18_TSADC_SOC1VDD18_TSADC_SOC0
VDD18_TSADC_GPU0
VDD18_TSADC_CPU5VDD18_TSADC_CPU4VDD18_TSADC_CPU3VDD18_TSADC_CPU2VDD18_TSADC_CPU1VDD18_TSADC_CPU0
VDD18_FMON
VDD18_EFUSE2VDD18_EFUSE1
VDD18_AMUX
VDDIO18_GRP4
VDD18_TSADC_ANE
SYM 11 OF 16
VDDQL_DDR0
VDD_DCS_DDR1
VDD_DCS_DDR2
DDR3_ZQ
DDR3_RREFDDR2_RREFDDR1_RREF
DDR0_ZQ
DDR0_RREF
VDDQL_DDR2
VDDQL_DDR1
VDDIO12_PLL_DDR3VDDIO12_PLL_DDR2VDDIO12_PLL_DDR1VDDIO12_PLL_DDR0
VDDIO11_RET_DDR3VDDIO11_RET_DDR2VDDIO11_RET_DDR1
VDD2_DDR3
VDD2_DDR2
VDD2_DDR1
VDD1_DDR2
VDD1_DDR1
VDD1_DDR0
VDD_DCS_DDR3
VDD_DCS_DDR0
LP4_IN_RESET*
VDD2_DDR0
VDD1_DDR3
VDDQL_DDR3
VDDIO11_RET_DDR0
VDDQL_SENSE
VDD_DCS_SENSE
SYM 10 OF 16
VDD_FIXED VDD_FIXED
VDD_SOC_SENSEVDD_PCPU_SENSE
VSS_GPU_SENSEVSS_PCPU_SENSE
VDD_GPU_SENSE
VSS_SENSEVSS_DDR_SENSE
VIETMOBILE.VN
SOC - POWER SUPPLIES
16 OF 60
7.0.0
19 OF 85
051-02545
AE4Y30Y28Y26Y24Y22Y20Y18Y8Y5Y3W38W31W29W27W25W23W21W19W17W15W13W11W9
W1V36V34V30V28V26V24V22V20V18V16V14V12V10U38U31U29U27U25U23U21U19U17U15 U1000
AJ2U9U5U3U1T30T28T26T24T22T20T18T16T14T8R38R36R34R31R29R27R25R23R21R19R17R15R13R9R1P30P28P26P24P20P18P16P8P5P3N31N27N25N23N21N19N17N15N11N9M38M36M34M28M26M24M22M20M18M16M14M10M1L29L27L25L23L21L15L13L11L9L5L3K38K28
K26K24K22K20K14K12K10K8K1
J36J34J29J27J25J23J21J15J13J11H30H28H26H24H22H20H18H16H14H12H10H5H4H3
G38G31G29G27G25G23G21G17G13G11G3G2G1
F36F34F30F28F26F24F20F18F16F14F12F10F5F4F3F2
E38E36E35E34E5E4E3E2E1
D37D32D30D28 U1000
D26D22D21D18D15D12D9D8D5D4D2C38C36C34C33C31C29C27C25C23C12C11C10C9C8C7C6C5C3C1B38B37B36B35B34B24B23B21B18B15B12B5B3B2B1AY38AY37AY36AY34AY32AY30AY28AY26AY24AY18AY15AY9AY3AY2AY1AW38AW37AW36AW34AW32AW30AW28AW26AW24AW18AW15AW9AW3AW2AW1AV38AV36AV35AV33
AV31AV29AV27AV25AV24AV23AV22AV21AV20AV19AV18AV17AV16AV15AV14AV13AV12AV11AV10AV9AV8AV7AV6AV5AV4AV3AV1
AU37AU35AU33AU31AU29AU27AU25AU2
AT38AT37AT36AT35AT34AT33AT32AT30AT29AT28AT27AT26AT25AT3AT2AT1
AR37AR36AR32AR30AR28AR25AR22AR19AR16AR13AR10AR7AR4AR3AR2
AP38AP37AP36AP35AP34AP31AP3AP2AP1
AN37AN36AN5 U1000
AN4AN3AN2AM35AM34AM30AM28AM24AM22AM20AM18AM16AM8AM5AM4AM3AM2AL38AL37AL36AL31AL29AL25AL23AL19AL17AL15AL13AL11AL2AL1AK35AK34AK28AK26AK24AK22AK20AK18AK16AK14AK12AK10AK5AK4AK3AK2AJ38AJ37AJ36AJ27AJ25AJ23AJ21AJ19AJ17AJ15AJ5AJ3AJ1AH28AH26AH24AH22AH18AJ4AG36AG34AG29AG27AG25AG23AG21AG19AG17AG15AG9AF38
AF30AF28AF26AF24AF22AF20AF18AF14AF12AF10AF8AF5AF3AF1
AE31AE27AE25AE21AE19AE17AE15AE13AE11AE9
AD38AD36AD34AD28AD26AD20AD18AD1
AC31AC27AC25AC23AC21AC19AC17AC9AC5AC3
AB38AB30AB28AB26AB24AB22AB20AB18AB8AB1
AA36AA34AA31AA29AA27AA25AA23AA21AA19AA9A38A37A36A35A34A32A30A28A26A24A12A5A3A2A1 U1000
SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
SOC: POWER (3/3)
CYP-4GB-M-TMJA47A0-C7WLCSPWLCSP
CYP-4GB-M-TMJA47A0-C7CYP-4GB-M-TMJA47A0-C7WLCSP
CYP-4GB-M-TMJA47A0-C7WLCSP
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 16 OF 16
VSSVSS
SYM 15 OF 16
VSSVSS
SYM 14 OF 16
VSSVSS
SYM 13 OF 16
VSSVSS
VIETMOBILE.VN
Dev Board Compatibility FB XW's
FF Touch Compatibility Compatibility
Place Near PMU
Should live on PMU LDO page by caps
Dev Board Power Compability
FF Display Compatibility
FF Specific CLK Series Terminations
Place near SOC Balls
Medusa Compatibility
Dev Board Compatiblity GNDs
PCIE Series Caps
UF Dam Caps
17 OF 60
PMU_TO_TOUCH_CLK32K23
NC_DISPLAY_TO_CHESTNUT_PWR_EN23
PP1V2_SOC 14
PP_VDD_MAIN 21
PP_VDD_MAIN 21
GND9
GND9
GND9
GND7
GND7
PP_VDD_MAIN 21
NC_DWI_PMGR_TO_BACKLIGHT_CLK 11
NC_UART_WLAN_TO_AP_CTS_LNC_UART_AP_TO_WLAN_RTS_L
NC_UART_WLAN_TO_AP_RXDNC_UART_AP_TO_WLAN_TXD
GND22
PP1V8_IO 8
PP1V8_IO 15
PP1V8_IO 9
PP1V8_IO 7 15
PP1V8_S2 15
PP1V2_SOC 15
PP_VDD_BOOST 22
PP_VDD_MAIN 21
PP_VDD_MAIN 21
PP_VDD_MAIN 21
PP_VDD_MAIN 21
PP_CPU_ECORE14 17
PP_DCS_S1 15
PP_CPU_ECORE 14 17
PP3V3_USB 7
PP_GPU_SRAM 14
PP_CPU_SRAM 14
PP1V2_SOC 8 10
PP_SOC_S1 14
PP_VDD_MAIN 21
PP_VDD_MAIN 21
PP_VDD_MAIN 21
PP_VDD_MAIN 21
PP1V8_S2 23
PP1V8_S2 13 15
GND10
GND10
GND9
PP_VDD_MAIN 21
GND7
PP_VDD_MAIN 22
PP_VDD_MAIN 21
BUCK11_FB23
PP_CPU_PCORE14 17
GND9
GND9
PP1V8_IO 11
PP_VDD_MAIN 22
PP0V6_VDDQL_S1 15
PP0V7_VDD_LOW_S2 14
PP_VDD_BOOST 22
PP_VDD_BOOST 22
PP_VDD_BOOST 22
PP_VDD_BOOST 22
PP1V1_S2 22
PP_GPU 14 17
PP1V8_ALWAYS
PP_CPU_PCORE 14 17
PP1V1_S2 22
PP1V26_S2 22
PP1V1_S2 15
PP2V5_LDO0_S2 22
GND22
PP0V8_SOC_FIXED_S1 14
PP0V8_SOC_FIXED_S1 15
PP0V8_SOC_FIXED_S1 7 8 9 10 14
NC_DWI_PMGR_TO_BACKLIGHT_DATA 11
GND9
GND9
GND 23
GND
GND 23
GND 23
GND 23
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP_GPU14 17
MAKE_BASE=TRUE
7.0.0
20 OF 85
051-02545
21C1100
21C1101
21C1102
A2A1
B2
B1
U4002
2
1 C4082
2
1C40812
1C4080
2
1 C2000
2 1
XW17902 1
XW170121
XW1731
21C1103
21R1481
2 1
XW2990
2
1 C3072
21R1241
21R1242
21
R1243
21
R1244
21C1120
21C1121
21C1122
21C1123
21C1130
21C1131
21C1132
21C1133
MAKE_BASE=TRUE
PMU_TO_TOUCH_CLK32K
MAKE_BASE=TRUEACORN_GECKO_ANSEL_TO_PMU_ADC
AP_TO_TELE_CLK_R
90_PCIE_BB_TO_AP_RXD_C_P 90_PCIE_BB_TO_AP_RXD_P
MAKE_BASE=TRUEPP_GPU
MAKE_BASE=TRUEPP_SOC_S1
90_PCIE_AP_TO_BB_TXD_N90_PCIE_AP_TO_BB_TXD_P
90_PCIE_AP_TO_BB_TXD_C_N
90_PCIE_BB_TO_AP_RXD_C_N
90_PCIE_NAND_TO_AP_RXD_C_P 90_PCIE_NAND_TO_AP_RXD_P90_PCIE_NAND_TO_AP_RXD_C_N 90_PCIE_NAND_TO_AP_RXD_N
90_PCIE_AP_TO_NAND_TXD_P
90_PCIE_AP_TO_WLAN_TXD_C_P90_PCIE_AP_TO_WLAN_TXD_C_N
90_PCIE_WLAN_TO_AP_RXD_P
90_PCIE_AP_TO_NAND_TXD_N
90_PCIE_AP_TO_WLAN_TXD_N
PP_CPU_PCOREMAKE_BASE=TRUE
NC_UART_WLAN_TO_AP_CTS_LMAKE_BASE=TRUE
NC_UART_AP_TO_WLAN_RTS_LMAKE_BASE=TRUE
BUCK11_FBMAKE_BASE=TRUE
MAKE_BASE=TRUENC_UART_AP_TO_WLAN_TXD
PP1V8_IOMAKE_BASE=TRUE
PP1V8_S2MAKE_BASE=TRUE
AP_TO_TELE_CLK
AP_TO_RACER_REF_CLK_R
BUCK0_FBBUCK11_FB
PP_CPU_ECOREMAKE_BASE=TRUE
PP0V6_VDDQL_S1MAKE_BASE=TRUE
PP_GPU_SRAMMAKE_BASE=TRUE
PP_DCS_S1MAKE_BASE=TRUE
PP_CPU_SRAMMAKE_BASE=TRUE
BUCK1_FB
AP_TO_RIGEL_CLK
PP1V8_ALWAYSMAKE_BASE=TRUE
AP_TO_FCAM_JULIET_RIGEL_CLK_R
MAKE_BASE=TRUENC_DWI_PMGR_TO_BACKLIGHT_DATA
MAKE_BASE=TRUENC_DWI_PMGR_TO_BACKLIGHT_CLK
PP_VDD_MAIN
VDD_MAIN_SNS
NC_DISPLAY_TO_CHESTNUT_PWR_ENMAKE_BASE=TRUE
90_PCIE_AP_TO_WLAN_TXD_P
90_PCIE_BB_TO_AP_RXD_N
90_PCIE_AP_TO_BB_TXD_C_P
90_PCIE_WLAN_TO_AP_RXD_N
PP1V1_CAM_JULIET_DVDD
AP_TO_JULIET_CLK
AP_TO_FCAM_CLK
MAKE_BASE=TRUENC_UART_WLAN_TO_AP_RXD
MAKE_BASE=TRUEPP1V2_SOC
MAKE_BASE=TRUEPP_VDD_BOOST
PP_VDD_MAINMAKE_BASE=TRUE
90_PCIE_WLAN_TO_AP_RXD_C_N
90_PCIE_AP_TO_NAND_TXD_C_N90_PCIE_AP_TO_NAND_TXD_C_P
PP3V3_USBMAKE_BASE=TRUE
MAKE_BASE=TRUEPP2V5_LDO0_S2
MAKE_BASE=TRUEPP1V1_S2
PP0V7_VDD_LOW_S2MAKE_BASE=TRUE
MAKE_BASE=TRUEPP0V8_SOC_FIXED_S1
PP0V6_VDDQL_S1
AP_TO_RACER_REF_CLK
MAKE_BASE=TRUEPP1V26_S2
90_PCIE_WLAN_TO_AP_RXD_C_P
CAMPMU_TO_JULIET_DVDD_LDO_EN
PP1V26_S2
SOC: DEV BOARD ALIASES
SYNC_DATE=04/17/2017SYNC_MASTER=
32
1%
ROOM=SOC01005
1/32W
33.2
MF
37
34
36
1/32W
ROOM=SOC
33.2
MF
1%
01005
ROOM=SOC
MF1/32W
01005
1%
33.2
MF01005
33.2
ROOM=SOC
1%1/32W
57
57
57
57
20% 6.3V01005
0.1UFGND_VOID
ROOM=SOCX5R-CERM
0.1UF
X5R-CERM20% 6.3VGND_VOID
ROOM=SOC01005
X5R-CERM20% 6.3V
0.1UF
01005GND_VOID
ROOM=SOC
20% 6.3VGND_VOIDX5R-CERM
ROOM=SOC
0.1UF
PACK_TYPE=01005
58
58
58
58
0.1UF20% 6.3VGND_VOID
X5R-CERMROOM=SOC
01005
20% 6.3VX5R-CERM
ROOM=SOC
GND_VOID
01005
0.1UF
20% 6.3V01005
GND_VOID0.1UF
ROOM=SOCX5R-CERM
0100520% 6.3VGND_VOID
0.1UF
ROOM=SOCX5R-CERM
19
19
19
19 6.3V
X5R20%
ROOM=SOC
GND_VOID
0.22UF
01005-1
GND_VOID
0.22UF
ROOM=SOCX5R 01005-1
6.3V20%
GND_VOID
0.22UF
ROOM=SOC
20%X5R 01005-1
6.3V
ROOM=B2B_PEARLCRITICAL
WLCSPSCY99224-1.20V
ROOM=B2B_PEARL
X5R-CERM
20%6.3V
0201
2.2UF
ROOM=B2B_PEARL
20%
X5R6.3V
0.47UF
01005
20%
X5R6.3V
01005
0.47UF
ROOM=B2B_PEARL
220PF25V
01005COGROOM=SOC
5%
12
12
12
12
21 17
ROOM=SOC
SHORT-20L-0.05MM-SM
OMIT
20
SHORT-20L-0.05MM-SM
ROOM=SOC
OMIT
20 ROOM=SOC
OMIT
SHORT-20L-0.05MM-SM
NO_XNET_CONNECTION
GND_VOID
0.22UF
ROOM=SOC
20%X5R 01005-1
6.3V
58
0%
MF1/32W
0.00
01005ROOM=SOC
OMIT
SHORT-20L-0.05MM-SM
ROOM=PMU
21
ROOM=PMU
1000PF
X5R10V10%
01005
58
60 47 30 23
9
8 5
20 5
20
8
8 5
8
8
8
8
20 5
21 17
53 52 44 37 36 34 32 31 30 29 20 19 6
59 54 50 49 48 42 41 40 38 25 20
11
21
21 17
20
20
20
57 26 23 22
9
59 47 45 44 43 42 41 36 33 29 26 24 22 17
8
37
22
59 47 46 40 36 29 24 22
59 47 45 44 43 42 41 36 33 29 26 24 22 17
8
8
8
22
22
20
22
20
21 17
44 29 22 20 17
8
30 5
44
29 22 20 17
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN OUT
GND
EN
IN
OUT
IN
OUT
OUT OUTOUT
OUT
OUT
VIETMOBILE.VN
18 OF 60
90_LPDP_TELE_TO_AP_D1_P 10
90_LPDP_TELE_TO_AP_D1_N 10
90_LPDP_TELE_TO_AP_D0_N 10
90_LPDP_WIDE_TO_AP_D2_P 10
90_LPDP_WIDE_TO_AP_D2_N 10
90_LPDP_FCAM_TO_AP_D1_P 10
90_LPDP_FCAM_TO_AP_D1_N 10
90_LPDP_WIDE_TO_AP_D0_P 10
90_LPDP_WIDE_TO_AP_D0_N 10
90_LPDP_WIDE_TO_AP_D1_P 10
90_LPDP_WIDE_TO_AP_D1_N 10
90_LPDP_TELE_TO_AP_D0_P 10
90_LPDP_TELE_TO_AP_D2_P 10
90_LPDP_TELE_TO_AP_D2_N 10
90_LPDP_FCAM_TO_AP_D0_P 10
90_LPDP_FCAM_TO_AP_D0_N 10
7.0.0
21 OF 85
051-02545
90_LPDP_TELE_TO_AP_D0_NMAKE_BASE=TRUE
MAKE_BASE=TRUE
90_LPDP_WIDE_TO_AP_D0_N MAKE_BASE=TRUE
90_LPDP_WIDE_TO_AP_D0_P
90_LPDP_WIDE_TO_AP_D2_PMAKE_BASE=TRUE
90_LPDP_TELE_TO_AP_D0_PMAKE_BASE=TRUE
MAKE_BASE=TRUE
90_LPDP_FCAM_TO_AP_D1_P
MAKE_BASE=TRUE
90_LPDP_FCAM_TO_AP_D1_N
MAKE_BASE=TRUE
90_LPDP_FCAM_TO_AP_D0_P
MAKE_BASE=TRUE
90_LPDP_FCAM_TO_AP_D0_N
MAKE_BASE=TRUE
90_LPDP_TELE_TO_AP_D2_P
MAKE_BASE=TRUE
90_LPDP_TELE_TO_AP_D2_N
MAKE_BASE=TRUE
90_LPDP_TELE_TO_AP_D1_P
MAKE_BASE=TRUE
90_LPDP_TELE_TO_AP_D1_N
90_LPDP_WIDE_TO_AP_D2_NMAKE_BASE=TRUE
MAKE_BASE=TRUE
90_LPDP_WIDE_TO_AP_D1_P90_LPDP_WIDE_TO_AP_D1_N
MAKE_BASE=TRUE
SYNC_DATE=08/17/2017
SOC: LPDP ALIASES
32
32
32
32
32
34
34
34
31
31
31
31
31
31
32
34
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
VIETMOBILE.VN
932mA MAX
S4E NAND
Place near C2629
Board trace <= 0.2Ohm
391mA MAX
1100mA MAX (1us peak power)
19 OF 60
7.0.0
26 OF 85
051-02545
2 1
XW2600
2
1 C26382
1 C26392
1 C2634
2
1 C2635
2
1 C26122
1 C26182
1 C26142
1 C2615
2
1 C2617
2
1 C26092
1 C26072
1 C2608
2
1 C2604
C10K3
G2
U12
U10U8U6U4U2T13T9T7T1R10
P13
P11P7P3P1N10N4M
13M7
M5
M1
L10
K13K7K5K1J10
H13
H11H9H5H3H1F13
F11F9F7F5F1D13
D11D1C12C2B13B1A12
A10A8A6A4A2
F3P9T5N2K9J2E10
E2 R4R8R6L8L6G8
G6
R2L12
G4
E12
D3
G10
L4
R12T11
M11N12
K11J12
P5
J8N8
H7
J6M9
N6
E4
E6
D7
E8
B11B9C8B7C6B5C4B3
D5
D9
T3
M3
L2 J4G12
U2600
2
1 C26362
1 C2637
2
1 C26012
1 C2600
2
1 C2624
2
1 C26222
1 C2627
2
1 R2601
2
1 C2641
2
1 C2652
2
1 C2611
2
1 C26472
1 C26452
1 C2643
2
1 C2630
2
1 C26032
1 C2606
2
1 C26402
1 C26422
1 C26442
1 C2646
2
1 C26492
1 C26502
1 C2651
2
1 C2629
2
1 C2626
2
1 R2600
2
1 C26212
1 C26192
1 C26162
1 C2613
2
1 C26052
1 C2602
2
1 C2610
2
1 R2604
AP_TO_NAND_SYS_CLK
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
PCIE_AP_TO_NAND_PERST_L
SWD_AOP_TO_MANY_SWCLK
SYSTEM_ALIVE
90_PCIE_AP_TO_NAND_REFCLK_N
90_PCIE_NAND_TO_AP_RXD_P
AP_TO_NAND_RESET_L
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
90_PCIE_AP_TO_NAND_REFCLK_P
PCIE_NAND_BI_AP_CLKREQ_L
PCIE_NAND_RESREF
90_PCIE_AP_TO_NAND_TXD_P90_PCIE_AP_TO_NAND_TXD_N
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1
AP_TO_NAND_FW_STRAPPMU_TO_NAND_LOW_BATT_BOOT_L
PP1V8_IO
90_PCIE_NAND_TO_AP_RXD_N
NAND_ZQ_NAND
SWD_AP_BI_NAND_SWDIO
NAND_ZQ_ANI
PP2V63_NAND
NAND_ANI0_VREFNAND_ANI1_VREF
PP0V9_NAND
PP1V8_IO
PP1V8_IO_PCI_AVDD
SYNC_MASTER=test_mlb SYNC_DATE=03/22/2017
NAND
OMIT
SHORT-20L-0.05MM-SM
ROOM=NAND
5%100PF
01005NP0-C0G16V
ROOM=NAND
5%
01005NP0-C0G
68PF16V
ROOM=NAND
5%
01005
47PF
CERM16V
ROOM=NAND
5%
01005
16V
22PF
CERM
ROOM=NAND
ROOM=NAND
5%
01005
25VCOG
220PF
NP0-C0G
100PF5%
01005
16V
ROOM=NAND
16V
01005
5%
ROOM=NAND
68PF
NP0-C0G
47PF
ROOM=NAND01005
5%16VCERM
22PF5%
01005ROOM=NAND
CERM16V
5%100PF
01005NP0-C0G16V
ROOM=NAND
5%
01005NP0-C0G
68PF16V
ROOM=NAND ROOM=NAND
5%
01005CERM16V
47PF 22PF5%
01005
16VCERM
ROOM=NAND
H23Q2T8QK6MES-BCLGA
ROOM=NANDBOMOPTION=OMIT_TABLE
CRITICAL
5%
01005ROOM=NAND
COG25V
220PF5%100PF
01005NP0-C0G16V
ROOM=NAND
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
5
5
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
11 6
11 6
11 6 5
ROOM=NAND01005MF
3000.1%1/32
26 23
8
58 13 5
13 5
7
55
7 5
17
17
17
17
8
8 5
8 5
11
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NAND
6.3VX5R-CERM0201
2.2UF20%
5%
01005COG25V
ROOM=NAND
220PF
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NANDROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NANDCERM
15UF
0402-0.1MM
6.3V20%
5%
01005ROOM=NAND
25VCOG
220PF5%
ROOM=NAND
220PF
COG25V
01005
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NAND
X5R-CERM
2.2UF6.3V
0201
20%
ROOM=NAND
6.3VX5R-CERM0201
2.2UF20%
ROOM=NAND
6.3VX5R-CERM0201
2.2UF20%
ROOM=NAND
6.3VX5R-CERM0201
2.2UF20%
CERM
15UF
0402-0.1MMROOM=NAND
6.3V20%
ROOM=NANDX5R-CERM
2.2UF6.3V
0201
20%
1/32W
1000.1%
MF01005
ROOM=NAND
ROOM=NAND
CERM0402-0.1MM
15UF6.3V20%
ROOM=NAND
CERM0402-0.1MM
15UF6.3V20%
ROOM=NAND
CERM0402-0.1MM
15UF6.3V20%
ROOM=NAND
CERM0402-0.1MM
15UF6.3V20%
26UF
ROOM=NAND0402-0.1MM
4VX5R
20%
ROOM=NAND
26UF
0402-0.1MM
4VX5R
20%
01005
0.1UF
ROOM=NANDX5R-CERM6.3V20%
3.01K1%1/32WMF01005ROOM=NAND
53 52 44 37 36 34 32 31 30 29 20 19 17 6
22
22
53 52 44 37 36 34 32 31 30 29 20 19 17 6
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
AVDD
18_P
LL
CLK_IN
ANI0
_VRE
F
VSS
EXT_D2/BOOT2/SPINAND_SCLK
EXT_NCE/PERST*
EXT_NRE/JTAG_TMS
EXT_NWE/JTAG_TCK
EXT_RNB/JTAG_TDO
EXT_CLE/JTAG_TDI
EXT_ALE/JTAG_SEL
EXT_D1/BOOT1EXT_D0/BOOT0
EXT_D7/SPF
DROOP_N
WP_N
PCIE_REFCLK_M
PCIE_TX0_PPCIE_TX0_M
RESET*
TRST*
ZQ_CZQ_N
VPP
VDD_
PLL
VCC
VDDI
O
VDD
ANI1
_VRE
F
PCI_
VDD_
1PC
I_VD
D_2
PCI_
AVDD
_H
PCI_
AVDD
_CLK
_1PC
I_AV
DD_C
LK_2
EXT_D3/SWD_UID0/SPINAND_MISO
EXT_D6/UART_TX
EXT_D4/UART_RX
PCIE_REFCLK_P
PCIE_CLKREQ_N
PCI_RESREF
PCIE_RX0_PPCIE_RX0_M
EXT_D5/SWD_UID1/SPINAND_MOSI
OUT
OUT
NC
NC
IN
IN
OUT
IN
IN
IN
BI
IN
IN
IN
OUT
OUT
IN
IN
BI
IN
IN
IN
NC
NC
VIETMOBILE.VN
Trim
med
to 1
.4A
Max
(Place C2763 Close to Ansel)
BUCK
80.4V - 1.15V
13.8A MAX
1.03V for overdrive only0.4V - 1.06V
0.67V/0.80V
BUCK
94.
9A M
AX2.
1A M
AX
BUCK
72.1A
MAX
BUCK2
(Place in TTS)
BUCK3
BUCK
42.5A MAX
BUCK04.9A MAX
2.1A
MAX
1.25
A MA
X
0.675V - 1.06V
0.600V - 0.875V
BUCK
6
BUCK114.3A Capable Trimmed to 10A Max
BUCK
51.
7A C
apab
le
0.735V - 1.01V
20 OF 60
7.0.0
27 OF 85
051-02545
2
1 C2764
2
1 C2793
2
1 C2763
2 1
L2790
2 1
L2780
21
L2741
21
L2721
21
L2711
21
L2701
2 1
L2770
2 1
L2760
21
L2730
C17
Y3
C6
B2
C15
C2C1
G2G1
F4
B17A17
E14
W18W17W16
T13
W3V3
T4
B6A6
E5
Y5W5V5
Y7W7V7
T5
D1E1D2
B1A2
C4B4A4
E4
Y11W11V11
Y9W9V9
T12
C9B9A9
C11B11A11
C13B13A13
B15A15
E9
U18U17U16
R18R17R16
N18N17N16
L18L17L16
N13
U2700
21
L2750
21
L2740
21
L2720
21
L2712
21
L2710
21
L2703
21
L2702
21
L2700
21
XW2720
2
1 C27322
1 C2731
2
1 C27622
1 C2761
2
1 C27142
1 C2715
2
1 C2724
2
1 C2790
2
1 C2706
21
XW2790
2
1 C2780
2
1 C2770
2
1 C27822
1 C2781
2
1 C27722
1 C2771
2 1
XW2780
2 1
XW2770
2
1 C2760
2 1
XW2760
2
1 C27522
1 C27512
1 C2750
2 1
XW2750
2
1 C2716
2
1 C2741
2
1 C27912
1 C27922
1 C2721
2
1 C2742
2 1
XW2740
2
1 C27442
1 C27432
1 C2740
21
XW2730
2
1 C27222
1 C2723
2
1 C2730
2
1 C2720
2
1 C27102
1 C27112
1 C27122
1 C2713
2
1 C27002
1 C27052
1 C27042
1 C27032
1 C27022
1 C2701
PP1V26_S2
PP_DCS_S1
BUCK1_LX1
BUCK1_LX0
PP1V1_S2
BUCK6_FB
PP0V8_SOC_FIXED_S1
BUCK6_LX0
PP_CPU_PCORE
BUCK2_LX1
PP1V8_S2
BUCK9_LX0
BUCK5_LX0
BUCK4_FB
BUCK4_LX1
BUCK4_LX0
BUCK3_LX0
BUCK0_LX0
BUCK2_FB
NC_BUCK1_LX3_2NC_BUCK1_LX3_3
BUCK0_LX3
BUCK0_LX1
BUCK7_LX0
BUCK8_LX0
BUCK5_FB
BUCK2_LX0
BUCK7_FB
BUCK0_LX2
PP1V8_IO
BUCK1_FB
NC_BUCK1_LX3_1
BUCK1_LX2
BUCK9_FB
BUCK0_FB
BUCK8_FB
BUCK3_FB
PP1V8_IMU_S2PP1V8_NFC_S2
PP1V8_TOUCH_RACER_S2
PP_GPU
PP_SOC_S1
PP_GPU_SRAM
PP_CPU_SRAM
SYSTEM POWER: PMU Bucks (1/4)SYNC_DATE=03/10/2017SYNC_MASTER=test_mlb
ROOM=PMU0201
4VX5R
4UF20%
4UF6.3V
0201ROOM=PMU
20%
CERM-X5R
NOSTUFF
20%4V
26UF
X5R0402-0.1MMROOM=PMU
1UH-20%-2A-0.069OHM
2012ROOM=PMU
1UH-20%-2A-0.069OHM
2012ROOM=PMU
17
1608
0.22UH-20%-5.3A-0.04OHM
ROOM=PMU
0.22UH-20%-5.3A-0.04OHM
1608ROOM=PMU
1608ROOM=PMU
0.22UH-20%-5.3A-0.04OHM
0.22UH-20%-5.3A-0.04OHM
1608ROOM=PMU
1UH-20%-3.0A-0.06OHM
ROOM=PMUPIJR2016-SM
PIJR2016-SMROOM=PMU
1UH-20%-3.0A-0.06OHM
1UH-20%-3.0A-0.06OHM
PIJR2016-SMROOM=PMU
D2542A0P0VQAVACWLCSP
CRITICALROOM=PMU
ROOM=PMUPIJR20120H-SM
1UH-20%-2.2A-0.06OHM
0.47UH-20%-4.5A-0.047OHM
PIJR20120H-SMROOM=PMU
PIJR20120H-SM
ROOM=PMU
0.47UH-20%-4.5A-0.047OHM
0.1UH-20%-9.4A-0.022OHM
1608ROOM=PMU
PIJR20120H-SMROOM=PMU
0.47UH-20%-4.5A-0.047OHM
1608ROOM=PMU
0.1UH-20%-9.4A-0.022OHM
0.1UH-20%-9.4A-0.022OHM
ROOM=PMU1608
ROOM=PMUPIJR20120H-SM
0.47UH-20%-4.5A-0.047OHM
ROOM=SOC
SHORT-20L-0.05MM-SM
NO_XNET_CONNECTION
OMIT
ROOM=PMU
X5R
26UF4V
0402-0.1MM
20%
0402-0.1MMROOM=PMU
26UF4V20%
X5R
26UF
ROOM=PMU
20%
X5R4V
0402-0.1MMROOM=PMU
26UF
X5R4V20%
0402-0.1MM
26UF
X5R0402-0.1MMROOM=PMU
4V20%
4VX5R0402-0.1MM
26UF
ROOM=PMU
20%
26UF
ROOM=PMU
20%4VX5R0402-0.1MM
17
ROOM=PMU
5%25VCOG01005
220PF
X5R0402-0.1MMROOM=PMU
4V20%26UF
ROOM=PMU
SHORT-20L-0.05MM-SM
OMIT
01005COG25V5%
ROOM=PMU
220PF
25V5%
COG
220PF
01005ROOM=PMU
0402-0.1MM
4VX5R
26UF20%
ROOM=PMU
26UF20%
ROOM=PMUX5R0402-0.1MM
4V
26UF
X5R4V20%
0402-0.1MMROOM=PMU
26UF20%
X5R
ROOM=PMU0402-0.1MM
4V
ROOM=PMU
SHORT-20L-0.05MM-SM
OMIT
ROOM=PMU
SHORT-20L-0.05MM-SM
OMIT
ROOM=PMU01005
220PF
COG
5%25V
ROOM=PMU
SHORT-20L-0.05MM-SM
OMIT
X5R4V
26UF20%
ROOM=PMU0402-0.1MM
26UF20%4VX5RROOM=PMU0402-0.1MM
5%
01005ROOM=PMU
25V
220PF
COG
SHORT-20L-0.05MM-SM
ROOM=PMU
OMIT
26UF
X5R
20%4V
ROOM=PMU0402-0.1MM
ROOM=PMU
20%4VX5R
26UF
0402-0.1MM
0402-0.1MM
4VX5R
20%26UF
ROOM=PMU
20%26UF
X5R0402-0.1MMROOM=PMU
4V
ROOM=PMU
4V
0402-0.1MM
26UF20%
X5R
4VX5R
ROOM=PMU0402-0.1MM
20%26UF
ROOM=PMU
SHORT-20L-0.05MM-SM
OMIT
20%
0402-0.1MMX5R4V
26UF
ROOM=PMU
26UF4VX5R
20%
ROOM=PMU0402-0.1MM
220PF
COG25V
ROOM=PMU
5%
01005
ROOM=PMU
SHORT-20L-0.05MM-SM
OMIT
0402-0.1MMROOM=PMU
4VX5R
26UF20%
0402-0.1MMROOM=PMU
20%26UF
X5R4V
ROOM=PMU
220PF5%
01005COG25V
220PF
01005
25V
ROOM=PMU
COG
5%
220PF5%25VCOG01005ROOM=PMU 0402-0.1MM
4V20%
X5R
26UF
ROOM=PMU
X5R
20%
0402-0.1MM
4V
26UF
ROOM=PMU
26UF
X5R
ROOM=PMU
4V20%
0402-0.1MM
01005ROOM=PMU
220PF5%
COG25V
ROOM=PMU
4VX5R
26UF
0402-0.1MM
20%
ROOM=PMU
20%
0402-0.1MMX5R
26UF4V
0402-0.1MMX5R
20%
ROOM=PMU
26UF4V
ROOM=PMU
26UF4VX5R0402-0.1MM
20%26UF
X5R
20%
ROOM=PMU0402-0.1MM
4V
44 29 22 17
17
17
17
17 5
59 54 50 49 48 42 41 40 38 25 17
53 52 44 37 36 34 32 31 30 29 19 17 6
54 50 28 27
58
59
17 5
17
17
17
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
SYM 2 OF 5
BUCK8_LX0
VBUCK3_SW
BUCK9_LX0
BUCK9_FB
BUCK8_FB
BUCK7_LX0
BUCK7_FB
BUCK6_LX0
BUCK6_FB
BUCK5_LX0
BUCK5_FB
BUCK4_LX1
BUCK4_FB
BUCK3_SW4BUCK3_SW3BUCK3_SW2
BUCK3_SW1
BUCK3_LX0
BUCK3_FB
BUCK2_LX1
BUCK2_LX0
BUCK2_FB
BUCK1_LX3
BUCK1_LX2
BUCK1_LX1
BUCK1_LX0
BUCK1_FB
BUCK0_LX3
BUCK0_LX2
BUCK0_LX0
BUCK0_FB
BUCK4_LX0
BUCK0_LX1
IN
VIETMOBILE.VN
0.415V - 1.06V
PMU - BUCKS 1.25A MAX
2.9A MAX
BUCK11BUCK10
21 OF 60
PP_VDD_MAIN17
PP_VDD_MAIN17
PP_VDD_MAIN17
PP_VDD_MAIN17
PP_VDD_MAIN17
PP_VDD_MAIN17
PP_VDD_MAIN17
PP_VDD_MAIN17
PP_VDD_MAIN17 21
PP_VDD_MAIN17
PP_VDD_MAIN17
PP_VDD_MAIN17
PP_VDD_MAIN17 21
PP_VDD_MAIN17 21
PP_VDD_MAIN17 21
7.0.0
28 OF 85
051-02545
2
1 C2581
21
L2800
21
L2811
2
1C2862
2
1C2866
M2
D18
Y2
C7
R12
P13V13
T7F12
F6
H18H17H16
K2K1
F2F1
C18B18
Y17Y16Y15
W2V2
B7A7
Y6W6V6
C3B3A3
Y10W10V10
D10C10B10A10
D14C14B14A14
T18T17T16T15
M18M17M16M15
G18G17G16
J18J17J16
F14
J2J1
K4
U2700
21
L2810
2
1 C2814
2
1C28652
1C28642
1C28672
1C2863
2
1C2861
2
1C28602
1C28592
1C2858
2
1C2857
2
1C2856
2
1C28552
1C2854
2
1 C28122
1 C2813
2
1 C2801
2
1 C2810
2
1 C2800
2 1
XW2800
2
1 C2811
2
1 C28502
1 C2852
VDD_MAIN_SNS PP0V6_VDDQL_S1
BUCK10_FB
BUCK11_LX1
BUCK11_FB
PP_CPU_ECORE
BUCK10_LX0
BUCK11_LX0
SYSTEM POWER: PMU Bucks (2/4)SYNC_DATE=06/01/2017SYNC_MASTER=test_mlb
0201CERM-X5R
6.3V20%4UF
ROOM=PMU
4UF6.3V
0201ROOM=PMU
CERM-X5R
20%
17
0402-0.1MM
4V
ROOM=PMU
20%
X5R
26UF
ROOM=PMU
4VX5R
26UF20%
0402-0.1MM
4V
ROOM=PMU0402-0.1MMX5R
20%26UF
COG
ROOM=PMU
5%25V
01005
220PF
ROOM=PMU
COG01005
220PF5%25VOMIT
SHORT-20L-0.05MM-SM
ROOM=PMU
4V
ROOM=PMUX5R0402-0.1MM
20%26UF
0402-0.1MM
20%
CER-X5R6.3V
18UF
ROOM=PMU
6.3VCERM
20%
ROOM=PMU0402-0.1MM
15UF
ROOM=PMU
1UH-20%-2A-0.069OHM
2012
0.22UH-20%-5.3A-0.04OHM
1608ROOM=PMU
0201
4UF
CERM-X5R6.3V20%
ROOM=PMU
20%
0201CERM-X5R
ROOM=PMU
4UF6.3V
D2542A0P0VQAVACWLCSP
ROOM=PMU0402-0.1MM
20%6.3VCER-X5R
18UF
ROOM=PMUPIJR20120H-SM
0.47UH-20%-3.2A-0.042OHM
0402-0.1MM
20%
X5R
26UF4V
ROOM=PMU
ROOM=PMU0201
20%4UF6.3V
CERM-X5R
17
4UF
ROOM=PMU
6.3V
0201CERM-X5R
20%
6.3VCERM-X5R
0201
4UF20%
ROOM=PMU
4UF6.3V
CERM-X5R
20%
0201ROOM=PMU
20%6.3V
0201
4UF
CERM-X5R
ROOM=PMU
ROOM=PMU0201
4UF20%
6.3VCERM-X5R
6.3V
4UF
0201CERM-X5R
20%
ROOM=PMU
CERM-X5R
ROOM=PMU0201
6.3V20%4UF
CERM-X5R
20%6.3V
0201
4UF
ROOM=PMU
0201
20%4UF6.3V
ROOM=PMU
CERM-X5R
17
17
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
SYM 3 OF 5
BUCK11_LX1
VDD_BUCK10
BUCK10_FB
BUCK10_LX0
BUCK11_FB
BUCK11_LX0
VDD_BUCK0_01
VDD_BUCK0_23
VDD_BUCK1_01
VDD_BUCK1_23
VDD_BUCK11
VDD_BUCK2
VDD_BUCK3
VDD_BUCK4
VDD_BUCK5
VDD_BUCK6
VDD_BUCK7
VDD_BUCK8
VDD_BUCK9
VDD_MAIN_0VDD_MAIN_1VDD_MAIN_2VDD_MAIN_3VDD_MAIN_4VDD_MAIN_5
VDD_MAIN_SNSIN
VIETMOBILE.VN
XW to VDD_MAIN_SNS lives on alias page
LDO10 250 mA MAXLDO11 250 mA MAX
LDO3 50 mA MAXLDO4 250 mA MAX
Job Taken by Gecko
LDO7 250 mA MAX
LDO14 250 mA MAX
LDO0 250 mA MAX
LDO1 50 mA MAXLDO2 50 mA MAX
LDO5 1.15 A MAXLDO6 110 mA MAX
LDO8 800 mA MAXLDO9 10 mA MAX
LDO12 50 mA MAXLDO13 250 mA MAX
VDD_LDO5
D3X Cap Off page
D3X Cap Off page
STability caps off page LDO 2,4,8 and 5 all have
PMU - LDOs
VPUMP: 10nF min. @4.6V
SHORTED TO BOOST ON D3X
This cap also services LDO 14
22 OF 60
PP_VDD_BOOST17
PP1V1_S217
PP2V5_LDO0_S217
GND17
PP_VDD_BOOST17
PP1V0_DISPLAY_DVDD44
PP3V0_DISPLAY44
PP_VDD_MAIN17
PP_VDD_BOOST17
PP_VDD_BOOST17
GND17
PP1V26_S217
PP1V1_S217
PP_VDD_MAIN17
PP_VDD_BOOST17
7.0.0
29 OF 85
051-02545
2
1 C2917
A2A1
B2
B1
U2900
2
1 C2980
2
1 C2916
U1
L6
R6
E2
E13
P3N3P4N5P7
L5R2L3
L2
T2M3P5M5P6
R3R4
N4R7
R1L4
M1W1V1T1
R5M4
L1
N6
N12
U2700
H15H3D4E17W15U3D6U7D3U10D9T14
P2
K18K17K16K15
P18P17P16P15
F18F17F16
H2H1
C16B16A16
C5B5A5
Y4W4V4
Y8W8V8
Y12W12V12
C8B8A8
D12C12B12A12
V18V17V16
Y18Y1
V15U15U12U11U9U8U6U5U4T8T6T3
R15R14R11R10R9R8
P14P11
P8N15N14N11N10N9M8M6
L15K14
K3J15
J3G15G3
E18E16E11D17D16D15D13D11D8D7D5
A18A1 U2700
2
1 C29702
1 C2971
2
1 C2900
2 1
XW2995
2
1 C2913
2
1 C29202
1 C2907
2
1 C29092
1 C2911
2
1 C2903
2
1 C2901
2
1 C2991
PP2V5_LDO0_S2
NC_DENALI_LDO12
PP3V0_PENROSE
PP3V0_S2
PP1V8_ALWAYS
PP1V2_SOC
PP0V9_NAND
PP2V63_NAND
PP1V8_AUDIO_VA_S2
NC_DENALI_LDO6
PMU_VSS_RTC
PMU_LDO5_UVLO_DET
PP1V26_S2
PP3V3_USB
PP1V2_CODEC_S2
PP0V7_VDD_LOW_S2
PMU_VPUMP
PP1V1_RACER_S2
PP_VDD_MAIN
PP_VDD_BOOST
SYNC_MASTER=test_mlb SYNC_DATE=03/10/2017
SYSTEM POWER: PMU LDOs (3/4)ROOM=PMU
X5R-CERM6.3V
0201
20%2.2UF
WLCSPSCY99224-1.10V
ROOM=PMUCRITICAL
ROOM=CAM_PMU0201X5R4V
4UF20%
0.47UF20%6.3VX5R01005ROOM=PMU
D2542A0P0VQAVACWLCSP
WLCSPD2542A0P0VQAVAC
2.2UF
ROOM=CAM_PMU
X5R-CERM6.3V
0201
20%
ROOM=CAM_PMU
2.2UF
X5R-CERM6.3V
0201
20%23
2.2UF20%
0201
6.3VX5R-CERM
ROOM=PMU
OMIT
ROOM=PMU
SHORT-20L-0.05MM-SM
20%
0201
6.3VX5R-CERM
2.2UF
ROOM=PMU
47NF
01005ROOM=PMU
X5R-CERM6.3V20%
2.2UF
ROOM=PMU
X5R-CERM6.3V
0201
20%
10VX5R-CERM
1.0UF20%
ROOM=PMU0201-1
6.3V
0201
20%
X5R-CERM
2.2UF
ROOM=PMU
ROOM=PMU
X5R-CERM0201
20%6.3V
2.2UF
2.2UF
X5R-CERM6.3V
0201
20%
ROOM=PMU
6.3VCER-X5R
20%18UF
ROOM=PMU0402-0.1MM
17
35
58 49 48 38
57 26 23 17
17
19
19
40
23
44 29 20 17
17
42 41 40
17
59
59 47 45 44 43 42 41 36 33 29 26 24 17
59 47 46 40 36 29 24 17
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN OUT
GND
EN
SYM 1 OF 5VDD_LDO0VDD_LDO1_3VDD_LDO2
VPUMP
VPP_OTP
VLDO9VLDO8VLDO7
VLDO6VLDO5VLDO4VLDO3VLDO2
VLDO14VLDO13VLDO12VLDO11VLDO10
VLDO1VLDO0
VDD_LDO9
VDD_LDO8VDD_LDO7
VDD_LDO6
VDD_LDO5
VDD_LDO14VDD_LDO12
VDD_LDO11_13VDD_LDO10
VDD_BYPASS
VCC_LDOG
TP_DET
VDD_LDO4
SYM 5 OF 5
VSSA_BUCK9VSSA_BUCK8VSSA_BUCK7VSSA_BUCK6VSSA_BUCK5VSSA_BUCK4VSSA_BUCK3
VSSA_BUCK11VSSA_BUCK10
VSSA_BUCK1VSSA_BUCK0
VSS_XTAL
VSS_SW_BUCK9_10
VSS_SW_BUCK5_3
VSS_SW_BUCK4_6
VSS_SW_BUCK2_4
VSS_SW_BUCK2
VSS_SW_BUCK11
VSS_SW_BUCK1_5
VSS_SW_BUCK1
VSS_SW_BUCK0_7
VSS_SW_BUCK_0_11
VSSA_BUCK2
VSS_SW_BUCK8_1
VSS
VSS_SW_BUCK_0
OUT
NC
VIETMOBILE.VN
REAR CAMERA NTC
Only has DS control when powered by VBUCK3Only has DS control when powered by VBUCK3
RADIO PA NTC on MLB Bottom
nmapedit @mlb_top_lib.mlb_top(sch_1):page39;
NOTE (4):OUTPUT OPEN-DRAIN, REQUIRES PULL-UPNOTE (3):INPUT PULL-UP OR DOWN 100k-300k
TODO: UpdateCONTROL PIN NOTES:
NOTE (1):INPUT PULL-DOWN 100-300kNOTE (2):INPUT PULL-DOWN 1M
NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC
PMU - GPIOs
NTCs
AP NTC
CHARGER NTC on Chrager Page
FOREHEAD NTC
COLD_RESET & SYSTEM_ALIVE
23 OF 60
GND
GND17
PMU_TO_TOUCH_CLK32K
I2C1_SMC_SDA
YANGTZE_TO_PMU_INT_L55
PMU_TO_NFC_VDD_MAIN_EN55
PMU_TO_NAND_LOW_BATT_BOOT_L55
PMU_TO_WLAN_REG_ON55
PMU_MASK_NFC_TO_ARC_TRIG55
CODEC_TO_PMU_WAKE_L55
PP1V8_S2 17
PMU_TO_BBPMU_RESET_R_L55
PMU_TO_DISPLAY_RESET_L55
PMU_TO_PHALANX155
NC_BT_TO_PMU_HOST_WAKE55
PMU_TO_BT_REG_ON55
PMU_TO_WLAN_CLK32K55
PMU_TO_GNSS_EN55
PMU_NFC_TO_ARC_RESET_L55
BB_TO_PMU_PCIE_HOST_WAKE_L55
WLAN_TO_PMU_HOST_WAKE55
PMU_TO_DISPLAY_LDO_EN55
PMU_TO_DISPLAY_PANICB55
PMU_TO_BOOST_EN55
NC_PMU_GPIO2155
PMU_TO_NFC_EN55
PMU_TO_PHALANX255
PMU_TO_AP_THROTTLE_GPU1_L55
PMU_TO_CCG2_RESET_L55
GND17
GND17
NC_DISPLAY_TO_CHESTNUT_PWR_EN
PMU_TO_IKTARA_EN_EXT_1V855
BUCK11_FBI2C1_SMC_SCL
7.0.0
30 OF 85
051-02545
2
1C3051
2
1
XW3000
3
1
4
2
Y3000
2
1 C3030
21
C3010
2
1 R3020
21
R3010
H13
J14
N1P1
P10
N7
N8
N2
T10
E15
F15
E8
F8
M13
M14
W13V14W14Y14Y13
U14
K13
K6
G13
H6
G6H7
G7
M10J8H8
F13
P12
K7
U2
P9
T9
K11K12H12J12L10H11J11L11L12L14J10F9H9J9K10G11G9G8F7E10H10K9F10F11G10
L9
G14
M9G12
M12L13M11
J13
H14
U13R13
M7L7K5L8K8J7J5J4J6
H5H4G5G4F5F3E3E7E6
T11
E12
U2700
2
1 C3031
2
1 R3011
2
1 R3061
2
1 R3062
2
1 C3020
2
1
R3044
2
1
R3042
2
1C3041
2
1C3042
2
1C3044
2
1
R3041
21
XW3044
21
XW3041
21
XW3042
DISPLAY_TO_PMU_AMUX
HYDRA_TO_PMU_USB_BRICK_ID_TIAACORN_GECKO_ANSEL_TO_PMU_ADC
FOREHEAD_NTC_RETURN
ACORN_GECKO_ANSEL_TO_PMU_ADC
NC_AMUX_B3NC_AMUX_B4
PMU_TO_AP_HYDRA_ACTIVE_READY
PMU_TO_AOP_CLK32K
PMU_VDD_MAIN_VSENSE
PMU_TO_AP_THROTTLE_ECORE_LPMU_TO_AP_THROTTLE_GPU0_L
HYDRA_TO_PMU_HOST_RESET
PMU_VBATT_VSENSEHYDRA_TO_PMU_USB_BRICK_ID_TIA
PMU_VDD_MAIN_ISENSE
PMU_LDO5_UVLO_DET
PMU_TO_AP_THROTTLE_PCORE_L
AP_NTC
PMU_VSS_RTC
AP_NTC
SYSTEM_ALIVE
PMU_TO_WLAN_CLK32K
CPU_PCORE_SENSE_POS
AP_TO_PMU_WDOG_RESET
AP_TO_PMU_AMUX_OUT
AP_TO_PMU_SOCHOT_L
NC_PMU_SHDNPMU_TO_SYSTEM_COLD_RESET_L
PMU_TO_AP_BUTTON_POWER_KEY_LPMU_TO_AP_BUTTON_VOL_UP_L
PMU_TO_AP_BUTTON_VOL_DOWN_L
BUTTON_RINGER_A
BUTTON_VOL_DOWN_L
BUTTON_VOL_UP_L
FOREHEAD_NTC
NC_PMU_AMUX_A7
BUTTON_POWER_KEY_L
AP_NTC_RETURN
PMU_TO_SYSTEM_COLD_RESET_L
PMU_TO_IKTARA_RESET_L
PMU_AMUX_AY
AP_TO_PMU_AMUX_SYNC
RADIO_PA_NTCRCAM_NTCFOREHEAD_NTC
PMU_TO_AP_PRE_UVLO_L
PMU_IREF
PMU_VREF
PMU_AMUX_BY
GPU_SENSE_POS
AP_TO_PMU_TEST_CLKOUT
PMU_TCAL
PMU_VDD_REF
XTAL_TO_PMU_CLK32K_2
PMU_VSS_RTC
XTAL_TO_PMU_CLK32K_2
PP1V8_ALWAYS
TOUCH_TO_MANY_FORCE_PWMSYSTEM_ALIVE
PMU_TO_AP_DOUBLE_CLICK_DET_LNC_PMU_CRASH_L
RIGEL_TO_ISP_INT
SPMI_PMU_BI_PMGR_SDATASPMI_PMGR_TO_PMU_SCLK
CHARGER_NTC
PMU_VDD_RTC
RCAM_NTC
RCAM_NTC_RETURN
SYSTEM POWER: PMU (4/4)SYNC_MASTER=test_mlb SYNC_DATE=03/10/2017
6.3V20%
0.1UF
01005X5R-CERM
SHORT-20L-0.05MM-SM
ROOM=PMU
OMIT
CSP32.768KHZ-10PPM
6.3V20%
X5R01005-1ROOM=PMU
0.22UF
20%6.3VX5R
ROOM=PMU01005-1
0.22UF
3.92K
TK
ROOM=PMU
1/32W0.1%
01005
200K
MF1/32W1%
01005ROOM=PMU
60 47 30 23 17
58 55
17
17
D2542A0P0VQAVACWLCSP
26
20%1.0UF10V
ROOM=PMU
0201-1X5R-CERM
26
26
26
58
36 9 5
55
27
11
ROOM=PMU
200K1%1/32WMF01005
60 47 30 23 17
44
7
17
58 45
22
17
55
12
12
7
7
12 7 5
27
35
27
49 46 23
15 5
15 5
54
54
57
57
13 5
26 23 19
49 7 5
57 23 15 7
7 5
49 46 23
7
13
58 30 24
7
49
7
ROOM=PMU
SHORT-20L-0.05MM-SM
OMIT
100K5%1/32WMF01005ROOM=PMU
100K5%1/32WMF
ROOM=PMU01005
OMIT
ROOM=PMU
SHORT-20L-0.05MM-SM
16VNP0-C0G
5%
ROOM=PMU01005
100PF
16VNP0-C0G
ROOM=PMU
5%100PF
01005
01005ROOM=PMU
10KOHM-1%
10KOHM-1%01005
ROOM=PMU
5%100PF
01005NP0-C0G
16V
ROOM=PMU
16VNP0-C0G
ROOM=PMU
5%
01005
100PF
ROOM=PMU
10KOHM-1%01005
ROOM=PMU
OMIT
SHORT-20L-0.05MM-SM23
23 22
23
26 23 19
23
57 23 15 7
23
23
23 5
23 22
23 5
57 26 22 17
23
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
VDD
CLKOUT
GND
NC
IN
IN
IN
OUT
SYM 4 OF 5
PRE_UVLO
XTAL2XTAL1
VDD_RTC_DIG
VDD_RTC
VDD_REF
VBAT
UV_WARN11_DETUV_WARN1_DETUV_WARN0_DET
TDEV5TDEV4TDEV3TDEV2TDEV1
TCAL
SYS_ALIVE
SLEEP_32K
SHDN
SDASCLK
SCL
RESET_IN1
RESET*
LDO5_UVLO_DET
IREF
IBAT
GPIO9GPIO8GPIO7GPIO6GPIO5GPIO4GPIO3
GPIO25GPIO24GPIO23GPIO22GPIO21GPIO20
GPIO2
GPIO19GPIO18GPIO17GPIO16GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10
GPIO1
FORCE_SYNC
FAULT_OUT*
DBLCLICK_DETCRASH*
BUTTONO3BUTTONO2BUTTONO1
BUTTON4BUTTON3BUTTON2BUTTON1
BRICK_ID2BRICK_ID1
AMUX_BYAMUX_B7AMUX_B6AMUX_B5AMUX_B4AMUX_B3AMUX_B2AMUX_B1AMUX_B0
AMUX_AYAMUX_A7AMUX_A6AMUX_A5AMUX_A4AMUX_A3AMUX_A2AMUX_A1AMUX_A0
ADC_IN
ACTIVE_RDY
SDATA
RESET_IN3RESET_IN2
VREF
OUT_32K
UV_WARN11UV_WARN1UV_WARN0
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
BI
IN
OUT
OUT
BI
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
VIETMOBILE.VN
353S01124When VDD_MAIN < 3.4, boosts to 3.4
Otherwise tracks VDD_MAIN
Boost Enable Pull
Tie directly to GND plane on layer 5
BOOST
24 OF 60
I2C0_AP_SDA
I2C0_AP_SCL
7.0.0
31 OF 85
051-02545
2
1
L3100
2
1
XW3100
21
R3110
B1
B4B3
A4A3
C4C3
C2
B2
D4D3D2
A2
A1
C1
D1
U3100
2
1 R3100
2
1 C31132
1 C31142
1 C3115
2
1C3190
2
1 C31102
1 C31122
1 C3111
PMU_TO_BOOST_EN
BOOST_AGND
PMU_TO_BOOST_EN
PP_VDD_MAIN
PP_VDD_BOOST
TOUCH_TO_MANY_FORCE_PWM
I2C0_AP_BI_BOOST_SDA_R
SYS_BOOST_LX
BOOST IND ALT, TDKL3100152S00869152S00873 ALT_PARTS
152S00871 L3100152S00869 ALT_PARTS BOOST IND ALT, CYN
SYSTEM POWER: BoostSYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
220PF5%
01005COG25V
ROOM=BOOST
20%15UF
0402-0.1MMCERM6.3V
ROOM=BOOST
20%15UF
0402-0.1MMCERM6.3V
ROOM=BOOST
20%15UF
0402-0.1MMCERM6.3V
ROOM=BOOST
ROOM=BOOSTCRITICAL
MCFE2016TR47MHNAMCFE2016-SM
ROOM=BOOST
OMIT
SHORT-20L-0.05MM-SM
1%
ROOM=BOOST
MF1/32W
39.2
01005
CSPSN61280E
ROOM=BOOST
CRITICAL55 24
52
52
58 30 23
511K1%1/32WMF01005ROOM=BOOST
20%15UF
0402-0.1MMCERM6.3V
ROOM=BOOST
20%15UF
0402-0.1MMCERM6.3V
ROOM=BOOST
20%15UF
0402-0.1MMCERM6.3V
ROOM=BOOST
55 24
59 47 45 44 43 42 41 36 33 29 26 22 17
59 47 46 40 36 29 22 17
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VOUT
AGNDPGND
SCL
BYP*
EN
SW
VOUT
SW
GPIO
VIN
VIN
SDA
VSEL
IN
BI
IN
IN
VIETMOBILE.VN
BATTERY CONNECTORRcpt: 516S00232Plug: 516S00233
Gas gauge I2C level translator
25 OF 60
I2C0_SMC_SDA
I2C0_SMC_SCL
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
7.0.0
32 OF 85
051-02545
10
9
87
65
4
321
J3200
2
1
DZ3201
2
1
DZ3200
21
R3202
21
R3201
2
1 C3201
2
1 C3202
21
3
Q3201
21
3
Q3200
2 1
XW3200
2
1 C32942
1 C32932
1 C3292
VBATT_SENSE
PP1V8_S2
I2C0_BMU_SCL_R
I2C0_BMU_SDA_RI2C0_SMC_BI_GG_SDA_CONN
PP_BATT_VCC I2C0_SMC_TO_GG_SCL_CONN
SYSTEM POWER: B2B BatterySYNC_DATE=10/13/2016SYNC_MASTER=test_mlb
330PF16V
01005
10%
ROOM=B2B_BATTERY
CER-X7RNP0-C0G-CERM01005
56PF25V5%
ROOM=B2B_BATTERYROOM=B2B_BATTERY
F-ST-SMB2B-BATT-RCPT
SG-WLL-2-2ESD202-B1-CSP01005
ROOM=B2B_BATTERY
ESD202-B1-CSP01005SG-WLL-2-2ROOM=B2B_BATTERY
01005
1/32W5%
33
MF
33
1/32W5%
01005MF
01005NP0-C0G-CERM
56PF5%25V
ROOM=B2B_BATTERY
01005NP0-C0G-CERM
5%25V
56PF
ROOM=B2B_BATTERY
RV3C002UNDFN
ROOM=B2B_BATTERY
DFN
ROOM=B2B_BATTERY
RV3C002UN
54
54
26
SHORT-20L-0.05MM-SM
ROOM=B2B_BATTERY
NO_XNET_CONNECTION=1PLACE_NEAR=J3200:2mm
25V
220PF
COG
ROOM=B2B_BATTERY01005
5%
59 54 50 49 48 42 41 40 38 20 17
59 26
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
GS
SYM_VER_3
D
GS
SYM_VER_3
D
IN
BI
OUT
VIETMOBILE.VN
NON-ZRB ALTS
BATTERY NTC
CHARGER NTC
YANGTZE CHARGER
26 OF 60
I2C0_SMC_SDAI2C0_SMC_SCL
7.0.0
33 OF 85
051-02545
21
C3392
2
1 R3301
2
1R3300
2
1 C3391
21
C3344
21
C3340
2
1 C33532
1 C3352
2
1 C3380
21
R3380
2
1 C33622
1 C3361
21
R3332
2
1
XW33022
1
XW33012
1
XW3300
2
1 C3345
21
R3303
2
1 C3351
2
1 C33122
1 C33112
1 C3310
G4
F4B4H4E7
A3
F2E2D2C2B2A2
B3
J5H5G5
C3
J3
E5D5C5B5A5
J2J1H1
J7H7G7F7
D7C7B7A7
H3G3
J6H6G6F6F5E6D6C6B6A6
H2
G2E4C4D4
F3
J8H8G8F8E8D8C8B8A8
J4A4
G1
F1E1D1C1B1A1
E3
U3300
21
L330421
L3303
21
L330221
L3301
2
1 C33432
1 C3342
2
1 C3390
2
1 C3360
21
XW3045
2
1
R3045
2
1 C3350
2
1 C3325
2
1 C33042
1 C33032
1 C3341
2
1 C3308
2
1 C33242
1 C3323
2
1 C33072
1 C3306
2
1 C3322
2
1C304521
XW3370
2
1 C3301
2
1 C3305
2
1 R3330
2
1
R33702
1C3370BATTERY_NTC_RETURN CHARGER_NTC
CHARGER_NTC_RETURN
USB_VBUS_DETECT
BATTERY_NTC
PP1V8_ALWAYS
PMU_VBATT_VSENSE_R
YANGTZE_MID2LX
YANGTZE_MID1LX
PMU_VBATT_VSENSE
YANGTZE_LDO
BATTERY_NTC
HYDRA_TO_YANGTZE_VBUS1_VALID_L
PP_BATT_VCC
PP_VBUS2_IKTARA
YANGTZE_TO_PMU_INT_L
YANGTZE_VBUS_DETECT
SYSTEM_ALIVE
PP_VAR_USB_RVP
PP_VBUS1_E75
YANGTZE_PMID
YANGTZE_LX2
YANGTZE_BOOT2
YANGTZE_LX1
YANGTZE_BOOT1
VBATT_SENSE
PP_VDD_MAIN_YANGTZE
PMU_VDD_MAIN_VSENSE_R
PP_VDD_MAIN
PMU_
VDD_
MAIN
_ISE
NSE_
R
PMU_VDD_MAIN_ISENSEPMU_VDD_MAIN_VSENSE
138S00187138S00070 NON-ZRBC3310,C3311,C3312ALT_PARTS
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
SYSTEM POWER: Charger
ROOM=CHARGER01005CER-X7R16V10%330PF
5%220PF
01005COG
ROOM=CHARGER
25V
18UF6.3V
ROOM=CHARGER
CER-X5R20%
0402-0.1MM
25
ROOM=CHARGER01005COG
5%25V
220PF
ROOM=PMU
SHORT-20L-0.05MM-SM
OMIT23
01005ROOM=PMU
10KOHM-1%
I68
10%16VCER-X7R
330PF
01005ROOM=CHARGER
220PF
ROOM=CHARGER
5%
01005COG25V
01005
220PF
COG5%
ROOM=CHARGER
25V
01005
5%220PF
COG25V
ROOM=CHARGER01005
5%COG
220PF
ROOM=CHARGER
25V
25V
ROOM=CHARGER
5%
01005
220PF
COG
MF
100K
ROOM=CHARGER01005
1/32W5%
COG01005
ROOM=CHARGER
220PF5%25V
ROOM=CHARGER01005
5%25V220PF
COG
220PF5%COG
ROOM=CHARGER01005
25V
55
5%
ROOM=CHARGER
COG
220PF
01005
25V
COG5%220PF
01005ROOM=CHARGER
25V
7
ROOM=PMU
100PF
NP0-C0G01005
16V5%
54
23 19
54
49 5
ROOM=CHARGER
SHORT-20L-0.05MM-SM
OMIT
01005ROOM=CHARGER
10KOHM-1%
I2
1UF
X5R
10%
402ROOM=CHARGER
25V
20%6.3VX5R
0.47UF
ROOM=CHARGER01005 1.00K
5%1/32WMF
ROOM=CHARGERNO_XNET_CONNECTION=1
01005MF1/32W
5%1.00K
NO_XNET_CONNECTION=1ROOM=CHARGER
01005
CERM0402-0.1MM
20%15UF6.3V
ROOM=CHARGER
1UF10%
ROOM=CHARGER402X5R25V
01005
20%10VX5R
0.1UF
NO_XNET_CONNECTION
ROOM=CHARGER
X5R
20%10V
0.1UF
ROOM=CHARGER01005
NO_XNET_CONNECTION
10VX5R
20%
ROOM=CHARGER0201
2.2UF 2.2UF
X5R
20%
ROOM=CHARGER0201
10V
6.3VX5R-CERM01005ROOM=CHARGER
0.1UF20%
12K
1%1/32W
01005MF
ROOM=CHARGER
2.2UF20%
0201ROOM=CHARGER
10VX5R
ROOM=CHARGER
2.2UF20%
X5R10V
0201
01005ROOM=CHARGER
MF
39K
1%1/32W
ROOM=BOOST
OMIT
NO_XNET_CONNECTION=1
SHORT-20L-0.05MM-SMSHORT-20L-0.05MM-SMROOM=BOOST
NO_XNET_CONNECTION=1
OMIT
ROOM=BOOST
SHORT-20L-0.05MM-SM
OMIT
NO_XNET_CONNECTION=1
220PF
COG
5%
01005
25V
ROOM=CHARGER
1/3WMF
1%
0.0025
0402
ROOM=CHARGER01005COG25V5%220PF
ROOM=CHARGER
25VCER-X5R0402-0.1MM
4.7UF20%
ROOM=CHARGER
25VCER-X5R
4.7UF20%
0402-0.1MMROOM=CHARGER
25VCER-X5R0402-0.1MM
4.7UF20%
SN2600B0DSBGA
ROOM=CHARGERCRITICAL
0.47UH-20%-5.6A-0.03OHM
NO_XNET_CONNECTION=1
ROOM=CHARGERMEHK2016-SM
0.47UH-20%-5.6A-0.03OHM
MEHK2016-SMROOM=CHARGER
0.47UH-20%-5.6A-0.03OHM
ROOM=CHARGER
NO_XNET_CONNECTION=1
MEHK2016-SMMEHK2016-SM
0.47UH-20%-5.6A-0.03OHM
ROOM=CHARGER
49 48
NP0-C0G
ROOM=CHARGER
100PF
01005
16V5%
26
57 23 22 17
23
26
59 25
59
58 50
59 47 45 44 43 42 41 36 33 29 24 22 17
23 23
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
OUT
OUT
OUT
IN
IN
BI
IN
SCL
AUX1
SDA
SYS_ALIVE
PMIDPMIDPMID
VBUS2_VALID*
VBUS1_DET
INT*
VBUS1
VBUS1
VBUS1
VBUS2
VBUS2
PMID
BAT
BAT
BAT
BAT
BAT
BAT_
SNS
VDD_
MAI
N
VDD_
MAI
N
VDD_
MAI
NVD
D_M
AIN
VDD_
MAI
NVD
D_M
AIN
VBUS1_VALID*
PMIDPMID
PMID
VBUS2
VBUS1
VBUS1
NTC
NC
NCNCNC
ACT_DIODE*
LDO_INLDO_INLDO_IN
LDO_OUT
TEST3TEST2TEST1
SW2
SW1
SW2SW2
SW2
SW1
BOOT1BOOT2
SW1SW1
GND
GND
GND
GND
GND
GND
GND
GND
GND
PMID
PMID
BAT
PMID
OUT
NC
VIETMOBILE.VN
Cyclone + Button ConnnectorRcpt: 516S00289Plug: 516S00290
<-- This one on MLB
Compass
Cyclone Filtering
BUTTONS
27 OF 60
I2C1_AOP_SDACKPLUS_WAIVE=I2C_PULLUP
I2C1_AOP_SCL 27 54
I2C1_AOP_SDA 27 54
I2C1_AOP_SCLCKPLUS_WAIVE=I2C_PULLUP
7.0.0
35 OF 85
051-02545
21
R3520
2
1 C3520
2
1 C3511
2
1 C3501
2 1
FL3550
2
1 C3550
2
1 C3531
2
1 C3532
2
1 C3533
2
1 C3500
2
1 C3510
21
XW3511
21
XW3510
21
XW3501
21
XW3500
2
1C3540
21
R3540
2
1C353021
R3530
2
1 DZ3540
2
1 DZ3530
2
1 DZ3520
1211
109
87
65
4321
J3500
PP1V8_IMU_COMPASS_CONNPP1V8_IMU_S2
IKTARA_COIL2
BUTTON_VOL_UP_CONN_L
IKTARA_COIL2_CONN
BUTTON_VOL_DOWN_CONN_L
BUTTON_VOL_UP_CONN_LBUTTON_RINGER_A_CONN
IKTARA_COIL1_CONN
PP1V8_IMU_COMPASS_CONN
IKTARA_COIL1
IKTARA_COIL2_CONN
IKTARA_COIL1_CONN
BUTTON_RINGER_A BUTTON_RINGER_A_CONN
BUTTON_VOL_UP_L
BUTTON_VOL_DOWN_L BUTTON_VOL_DOWN_CONN_L
COMPASS_TO_AOP_INT
COMPASS_TO_AOP_INT
SYSTEM POWER: B2B Cyclone + Button
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
ROOM=B2B_BUTTON
01005-112V-33PF
ROOM=B2B_BUTTON
12V-33PF01005-1
01005ROOM=B2B_BUTTON
1%
MF1/32W
499
ROOM=B2B_BUTTON
22PF2%50VC0G-CERM0201
50V
0201
220PF
C0G
2%
ROOM=B2B_BUTTON
220PF
0201ROOM=B2B_BUTTON
50V2%
C0G
59
59
FERR-150OHM-25%-200MA
01005ROOM=B2B_BUTTON
01005
220PF
COG25V
ROOM=B2B_BUTTON
5%5.5V-6.2PFROOM=B2B_BUTTON
0201
NOSTUFF
01005ROOM=B2B_BUTTON
56PF25V5%
NP0-C0G-CERM
NP0-C0G-CERM
56PF5%25V
ROOM=B2B_BUTTON01005
NOSTUFF
01005COG
ROOM=B2B_BUTTON
5%25V
220PF
54 27
54 27
56 27 5
220PF2%
0201C0G50V
ROOM=B2B_BUTTON
0201ROOM=B2B_BUTTON
2%
C0G50V
220PF
ROOM=B2B_BUTTON
SHORT-0201
SHORT-0201
ROOM=B2B_BUTTON
SHORT-0201
ROOM=B2B_BUTTON
ROOM=B2B_BUTTON
SHORT-0201
23
23
23
01005ROOM=B2B_BUTTON
5%
COG25V
220PF 01005
5%1/32W
ROOM=B2B_BUTTON
MF
100
01005
25VCOG
5%
ROOM=B2B_BUTTON
220PF 01005
100
MF
ROOM=B2B_BUTTON
1/32W5%
ROOM=B2B_BUTTON
AA36D-S04VA1F-ST-SM
27 54 50 28 20
27
27
27
27
27
27
27
27
27
27
27
56 27 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
BI
BI
IN
BI
OUT
OUT
OUT
OUT
PWR
PWR
VIETMOBILE.VN
Kobol - Accel & Gyro
Phosphorus BOSCH (APN:338S00334)
APN: 338S00367
28 OF 60
7.0.0
36 OF 85
051-02545
116
152
7
346
141312111098
5
U3600
68
534 7
1
2
U3620
2
1R3620
2
1R3601
2
1 C36222
1 C3620
2
1 C36022
1 C36012
1 C3600
SPI_AOP_TO_IMU_MOSI SPI_IMU_TO_AOP_MISO
PHOSPHORUS_TO_AOP_INT
IMU_TO_AOP_INTIMU_TO_AOP_DATARDY
SPI_AOP_TO_IMU_MOSI
PP1V8_IMU_S2
SPI_AOP_TO_IMU_SCLKSPI_AOP_TO_PHOSPHORUS_CS_L
PP1V8_IMU_S2
SPI_IMU_TO_AOP_MISO
PP1V8_IMU_S2
SPI_AOP_TO_IMU_SCLKSPI_AOP_TO_IMU_CS_L
PP1V8_IMU_S2
SENSORSSYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
CRITICAL
BMI282AALGA
ROOM=KOBOL
ROOM=PHOSPHORUSLGA
BMP284BA
56
100K1/32W
ROOM=PHOSPHORUS01005
MF
5%
5%
ROOM=KOBOL01005
MF1/32W
100K
56 5
56 5
28 13 5
56
28 13 5
28 13 5
28 13 5
28 13 5
28 13 5 56
X5R-CERM6.3V
ROOM=PHOSPHORUS0201
2.2UF20%
X5R-CERM6.3V
01005ROOM=PHOSPHORUS
20%0.1UF
0201
20%6.3V2.2UF
X5R-CERM
ROOM=KOBOLROOM=KOBOL
20%6.3V
01005
0.1UF
X5R-CERM6.3V
ROOM=KOBOL
20%
01005
0.1UF
X5R-CERM
54 50 28 27 20
54 50 28 27 20
54 50 28 27 20
54 50 28 27 20
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
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1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
MISOMOSI
SCLK
INTMOTION_INT
CS*
GND
VDDIOVDD
SM
CS*
SDI SDO
VDD VDDIO
IRQ
GND
SCK
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
ININ
VIETMOBILE.VN
<---- D3X has discrete Juliet DVDD LDO
DVDD: Digital SupplySVDD: AF Sensor Supply
ADC: ADC Supply
For GPIO pullups only
PVDD: AF Driver Supply
Camera PMU
<---- Stability Cap on FF specific page
AVDD: Analog Supply (Pixels)
29 OF 60
PP_CAM_TELE_ADC 32
PP2V85_CAM_TELE_AVDD 32
PP1V1_CAM_TELE_DVDD 32
7.0.0
37 OF 85
051-02545
2
1 C3720
2
1 C37982
1 C3797
2
1 C37962
1 C3795
2
1 C3709
2
1 C3718
2
1 C3710
21
L3700
2
1 C3721
2
1 C3719
2
1 C3715
2
1 C3704
J4
G1B7
B8A3
A4B1
A5A6
J2B2
H1A8
A7B3
B4
B5B6
H2
A2
A1
H3
F2
J3
U3700
G4E2C5
J8J7
H8H7
H5
U37002
1 C3791
2
1 C3751
2
1 C3702
2
1 C3790
21
XW3700
2
1C3750
2
1 C37012
1 C3700PP2V85_VAR_CAM_VCM_PVDD
CAMPMU_ON_BUF
PP1V8_IO
CAMPMU_VPUMP
CAMPMU_BUCK_LX0
CAMPMU_BUCK_FB
PP_CAM_WIDE_ADCPP2V85_FCAM_AVDD
PP1V1_FCAM_DVDDPP1V1_CAM_WIDE_DVDD
PP_VDD_MAIN
PP1V26_S2
PP3V3_ROMEO_WIDE_TELE_SVDD
PP2V85_CAM_JULIET_AVDDPP2V85_CAM_WIDE_AVDD
PP_VDD_BOOST
CAMERA: PMU (1/2)SYNC_DATE=10/13/2016SYNC_MASTER=test_mlb
220PF25VCOG
5%
01005ROOM=CAM_PMU
ROOM=CAM_PMU01005
6.3V20%47NF
X5R-CERM
ROOM=CAM_PMU
18UF
0402-0.1MMCER-X5R6.3V20%
ROOM=CAM_PMU
10%330PF
CER-X7R16V
01005CER-X5R
ROOM=CAM_PMU
6.3V20%18UF
0402-0.1MM
18UF6.3V20%
CER-X5R0402-0.1MMROOM=CAM_PMU
SHORT-20L-0.05MM-SM
OMITROOM=CAM_PMU
10%0.22UF
6.3VCER-X5R01005
ROOM=CAM_PMU
20%2.2UF6.3V
ROOM=CAM_PMU
0201X5R-CERM
2.2UF
X5R-CERM6.3V20%
ROOM=CAM_PMU
0201X5R-CERM6.3V
ROOM=CAM_PMU
2.2UF20%
0201
0201X5R-CERM
2.2UF6.3V20%
ROOM=CAM_PMU
2.2UF6.3V20%
X5R-CERM0201ROOM=CAM_PMU
6.3V
2.2UF20%
X5R-CERM0201ROOM=CAM_PMU
20%6.3V
2.2UF
X5R-CERM
ROOM=CAM_PMU
0201
20%6.3V
ROOM=CAM_PMU0402-0.1MMCERM-X5R
10UF
CRITICAL
1UH-20%-2.5A-0.078OHM
ROOM=CAM_PMU
PIWE20120H-SM
2.2UF20%6.3V
0201ROOM=CAM_PMU
X5R-CERM
0201
20%
ROOM=CAM_PMU
6.3VX5R-CERM
2.2UF
X5R-CERM0201
2.2UF20%6.3V
ROOM=CAM_PMU
2.2UF
X5R-CERM6.3V20%
0201ROOM=CAM_PMU
WLCSP
ROOM=CAM_PMU
CRITICAL
D2462A1
D2462A1WLCSP
ROOM=CAM_PMU
CRITICAL 31
53 52 44 37 36 34 32 31 30 20 19 17 6
31
34
34
31
59 47 45 44 43 42 41 36 33 26 24 22 17
44 22 20 17
37 32 31
37
31
59 47 46 40 36 24 22 17
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
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1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
SW OUTPUTSW INPUT
SYM 2 OF 4
LDO OUTPUTLDO INPUT
VLDO9VLDO4
VLDO15VLDO10
VLDO18VLDO17
VLDO20VLDO19
VLDO22VLDO21
ON_BUF
BUCK3_SW1
VDD_LDO9VDD_LDO4_17
VDD_LDO4_17
VDD_LDO19
VDD_LDO18
VDD_LDO20_21
VDD_LDO22VDD_LDO20_21
VDD_LDO10VDD_LDO15
VBUCK3
VPUMP
BUCKS
SYM 1 OF 4
VCC MAIN
VDD_BUCK9
VDD_MAINVDD_MAIN
VDD_MAIN
VDD_BUCK9BUCK9_LX0BUCK9_LX0BUCK9_FB
VIETMOBILE.VN
Pull Downs
Advanced Test Mode (OTP rewrite)
BUCK9_VSELFORCE_SYNC
PRE-UVLO
Alt FuncsLPM_IN
30 OF 60
I2C3_ISP_SDAI2C3_ISP_SCL
PP1V8_IO
7.0.0
38 OF 85
051-02545
F4J6J1H6H4G8G7G6
F1E5D5D2C7C4C3C2
U3700
E1
C1
G5J5
C6
F8E8
F5
D8
D1E3G2G3F3F7D3D4E4D7E6F6
D6
E7
C8
U3700
21
R380321
R3802
2
1 R3801
21
R3811
21
R3810
2
1 R3800
2
1 C38002
1 C3810
CAMPMU_TO_RIGEL_ENABLECAMPMU_TO_AP_IRQ_R_L
PP1V8_IOMAKE_BASE=TRUE
YOGI_TO_RIGEL_STATUS
MAMA_BEAR_BI_RIGEL_STATUS
CAMPMU_TO_AP_IRQ_L
AP_TO_CAMPMU_RESET_L
TOUCH_TO_MANY_FORCE_PWM
I2C3_ISP_SDA_U3700
CAMPMU_IREF
AP_TO_CAMPMU_RESET_L
ACORN_GECKO_ANSEL_TO_PMU_ADC
CAMPMU_VRTC
CAMPMU_VREFMAMA_BEAR_BI_RIGEL_STATUS_R
YOGI_TO_RIGEL_STATUS_R
CAMPMU_TO_JULIET_DVDD_LDO_EN
CAMPMU_TO_STROBE_DRIVER_HWEN
CAMERA: PMU (2/2)SYNC_DATE=03/22/2017SYNC_MASTER=test_mlb
D2462A1WLCSP
ROOM=CAM_PMU
CRITICAL
ROOM=CAM_PMU
CRITICAL
D2462A1WLCSP
17 5
ROOM=CAM_PMU01005MF1/32W1%200K
36 5
ROOM=CAM_PMU01005
1%
49.9
1/32WMF
1%1/32W
ROOM=CAM_PMU
33.2
01005MF
58 24 23
ROOM=CAM_PMU01005MF1/32W5%100K
38 36
37 36
01005
1/32WMF
10K
5%
ROOM=CAM_PMU
10K
01005MF
1/32W5%
ROOM=CAM_PMU
10%0.22UF
01005CER-X5R6.3V
ROOM=CAM_PMU
60 47 23 17
57 55 30
55
53
53 33
ROOM=CAM_PMU
20%
01005
6.3VX5R-CERM
0.1UF
53 52 44 37 36 34 32 31 29 20 19 17 6
57 55 30
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
NC
SYM 4 OF 4
VSSVSS
VSSVSSVSSVSSVSS
VSS
VSSVSSVSSVSSVSSVSSVSS
VSS
TEMPERATURE
REFERENCE
RESET
I2C
SYM 3 OF 4
GPIO
GPIO1
GPIO3GPIO4GPIO5GPIO6
GPIO2
GPIO9GPIO10GPIO11GPIO12GPIO15
SCL
IRQ*
SDA
CRASH*
VREF
IREF
VRTC
RESET_IN
TCAL
TDEV2TDEV1
AMUX_AY
ATM
OUT
NC
NC
NC
NCOUT
IN
IN
BI
OUT
IN
OUT
BI
IN OUT
NC
NC
VIETMOBILE.VN
ISP I2C
IO Filters
Power Filtering
Plug: 516S00314Rcpt: 516S00313Wide Camera Connector
<-- This one on MLB
LPDP Filters
_mod_write
31 OF 60
I2C0_ISP_SDA
I2C0_ISP_SCL
GND_VOID
GND_VOID
GND_VOID
GND_VOID GND_VOID
I2C0_ISP_SCL31 53
GND_VOID
I2C0_ISP_SDA31 53
7.0.0
39 OF 85
051-02545
2
1 C3398
21
R3906
21
R390521
C3951
21
C3950
21
C3941
21
C3940
21
C3931
21
C3930
2
1 C3997
2
1 C3990
32
31
3029
2827
2625242322212019181716151413121110987654321
J3900
21
FL3901
2
1 C3909
2
1 C392521
FL3903
2
1 C399521
FL3995
2
1 C39912
1 C3992
2
1 C3993
2
1 C3994
2
1 C3996
2
1 C3901
2
1 C3900
21
C3960
2
1 C3961
2
1 C3908
2
1 C3907
2
1 C3906AP_TO_WIDE_CLK AP_TO_WIDE_CLK_CONN
WIDE_AND_TELE_TO_STROBE_DRIVER_EN
90_LPDP_WIDE_TO_AP_D2_CONN_P
90_LPDP_WIDE_TO_AP_D0_P
90_LPDP_WIDE_TO_AP_D0_CONN_N90_LPDP_WIDE_TO_AP_D0_CONN_P
90_LPDP_WIDE_TO_AP_D2_CONN_N
LPDP_WIDE_BI_AP_AUX_CONN
WIDE_AND_TELE_TO_STROBE_DRIVER_EN
ISP_TO_WIDE_SHUTDOWN_L
LPDP_WIDE_BI_AP_AUX
90_LPDP_WIDE_TO_AP_D0_CONN_P
90_LPDP_WIDE_TO_AP_D0_CONN_N
90_LPDP_WIDE_TO_AP_D1_CONN_P90_LPDP_WIDE_TO_AP_D1_P
90_LPDP_WIDE_TO_AP_D1_CONN_N90_LPDP_WIDE_TO_AP_D1_N
90_LPDP_WIDE_TO_AP_D2_CONN_P
90_LPDP_WIDE_TO_AP_D2_CONN_N90_LPDP_WIDE_TO_AP_D2_N
90_LPDP_WIDE_TO_AP_D2_P
PP1V8_CAM_WIDE_VDDIO_CONN
PP_CAM_VCM_PVDD_CONNPP2V85_VAR_CAM_VCM_PVDD
90_LPDP_WIDE_TO_AP_D1_CONN_N
ISP_TO_WIDE_SHUTDOWN_L
90_LPDP_WIDE_TO_AP_D0_N
90_LPDP_WIDE_TO_AP_D1_CONN_P
AP_TO_WIDE_CLK_CONNPP3V3_ROMEO_WIDE_TELE_SVDD
PP_CAM_WIDE_ADC
LPDP_WIDE_BI_AP_AUX_CONN
PP1V1_CAM_WIDE_DVDD_CONN
PP2V85_CAM_WIDE_AVDD
PP1V1_CAM_WIDE_DVDD_CONN
PP_CAM_VCM_PVDD_CONN
PP2V85_CAM_WIDE_AVDD_CONN
WIDE_TO_TELE_SYNCPP1V8_CAM_WIDE_VDDIO_CONN
PP1V1_CAM_WIDE_DVDD
PP1V8_IO
PP2V85_CAM_WIDE_AVDD_CONNPP_CAM_WIDE_ADC
PP3V3_ROMEO_WIDE_TELE_SVDD
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
CAMERA: B2B Wide (TX)
01005ROOM=B2B_WIDE_RCAM
25VCOG
220PF5%
01005ROOM=B2B_WIDE_RCAM
25VCOG
220PF5%
ROOM=B2B_WIDE_RCAM
18UF6.3VCER-X5R20%
0402-0.1MM
ROOM=B2B_BUTTON01005
1/32WMF
0%
0.00
ROOM=B2B_WIDE_RCAM
49.9
MF
1%1/32W
01005
ROOM=B2B_WIDE_RCAM
6.3V
0.1UF
01005
20%
X5R-CERM
GND_VOID
GND_VOID
X5R-CERM
20%
01005
0.1UF
6.3V
ROOM=B2B_WIDE_RCAM
GND_VOID
X5R-CERM
20%
01005
0.1UF
6.3V
ROOM=B2B_WIDE_RCAM
GND_VOID
X5R-CERM
20%
01005
0.1UF
6.3V
ROOM=B2B_WIDE_RCAM
GND_VOID
X5R-CERM
20%
01005
0.1UF
6.3V
ROOM=B2B_WIDE_RCAM
GND_VOID
X5R-CERM
20%
01005
0.1UF
6.3V
ROOM=B2B_WIDE_RCAM
ROOM=B2B_WIDE_RCAM
2.2UF
X5R-CERM0201
6.3V20%
5%220PF
COG25V
01005ROOM=B2B_WIDE_RCAM
18
18
18
18
18
ROOM=B2B_WIDE_RCAM
AA26DK-S026VA1F-ST-SM
FERR-33OHM-25%-1.5A
0201ROOM=B2B_WIDE_RCAM
0201
2.2UF
X5R-CERM6.3V20%
ROOM=B2B_WIDE_RCAM
2.2UF
0201
6.3VX5R-CERM
ROOM=B2B_TELE_RCAM
20%
FERR-33OHM-25%-1.5A
0201ROOM=B2B_TELE_CAM
ROOM=B2B_WIDE_RCAM01005
6.3V0.1UF
X5R-CERM20%
01005-1
10-OHM-750MA
ROOM=B2B_WIDE_RCAM
01005ROOM=B2B_WIDE_RCAM
220PF
COG25V5%
25V
ROOM=B2B_WIDE_RCAM01005COG
220PF5%
ROOM=B2B_WIDE_RCAM
220PF
01005
25VCOG
5%
ROOM=B2B_WIDE_RCAM01005
5%220PF25VCOG
01005ROOM=B2B_WIDE_RCAM
COG
220PF5%25V
10
33 32 31
31 9
9
53 31
53 31
18
5%56PF25V
ROOM=B2B_WIDE_RCAM
NP0-C0G-CERM01005
01005
25V
56PF
NP0-C0G-CERM
ROOM=B2B_WIDE_RCAM
5%
20%
01005
6.3V
0.1UF
ROOM=B2B_WIDE_RCAM
X5R-CERM
01005
25VNP0-C0G-CERM
56PF
ROOM=B2B_WIDE_RCAM
5%
01005
56PF25V5%
NP0-C0G-CERM
NOSTUFFROOM=B2B_WIDE_RCAM
31
33 32 31
31
31
31
31
31
31
31
31
31
31
31
31
32 31 29
31
31 9
31
31
37 32 31 29
31 29
31
31
29
31
32 31
31
32
31
29
53 52 44 37 36 34 32 30 29 20 19 17 6
31
31 29
37 32 31 29
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
OUT
OUT
BI
OUT
IN
IN
BI
IN
OUT
VIETMOBILE.VN
IO Filters
ISP I2C
Power FilteringRcpt: 516S00313 <-- This one on MLB
LPDP
Plug: 516S00314
Tele Camera Connector
Lives Here For synccing purposes
32 OF 60
GND_VOID
GND_VOID
I2C1_ISP_SCL 32 53
I2C1_ISP_SDA 32 53
GND_VOID
GND_VOID
MAKE_BASE=TRUE
PP2V85_CAM_TELE_AVDD29
PP_CAM_TELE_ADC29
PP1V1_CAM_TELE_DVDD29
GND_VOID
GND_VOID
I2C1_ISP_SCL
I2C1_ISP_SDA
7.0.0
40 OF 85
051-02545
21
R4005
2
1 C4095
2
1 C3722
2
1 C3717
2
1 C4026
21
R4006
32
31
3029
2827
2625242322212019181716151413121110987654321
J4000
21
FL4003
2
1 C4025
2
1 C401721
FL4001
2
1 C40902
1 C4091
2
1 C4092
2
1 C4093
2
1 C4094
2
1 C4096
21
C4050
21
C4051
21
C4060
2
1 C4061
2
1 C4001
2
1 C4000
21
C4041
21
C4040
21
C4031
21
C4030
2
1 C4006
2
1 C4008
2
1 C4010
2
1 C4007
PP_CAM_VCM_PVDD_CONN
90_LPDP_TELE_TO_AP_D1_CONN_P90_LPDP_TELE_TO_AP_D1_CONN_N
PP1V8_CAM_TELE_VDDIO_CONN
WIDE_TO_TELE_SYNC
MAKE_BASE=TRUE
PP1V1_CAM_TELE_DVDD
PP_CAM_TELE_ADC
PP_CAM_VCM_PVDD_CONN
PP2V85_CAM_TELE_AVDD_CONN
PP1V8_CAM_TELE_VDDIO_CONN
LPDP_TELE_BI_AP_AUX_CONN
90_LPDP_TELE_TO_AP_D0_CONN_P
90_LPDP_TELE_TO_AP_D0_CONN_N
90_LPDP_TELE_TO_AP_D1_CONN_P
90_LPDP_TELE_TO_AP_D2_CONN_P
90_LPDP_TELE_TO_AP_D2_CONN_N
90_LPDP_TELE_TO_AP_D1_P
90_LPDP_TELE_TO_AP_D2_N
LPDP_TELE_BI_AP_AUX
ISP_TO_TELE_SHUTDOWN_L
90_LPDP_TELE_TO_AP_D1_N
WIDE_AND_TELE_TO_STROBE_DRIVER_EN
90_LPDP_TELE_TO_AP_D2_P
90_LPDP_TELE_TO_AP_D1_CONN_N
90_LPDP_TELE_TO_AP_D0_N
WIDE_TO_TELE_SYNC
PP3V3_ROMEO_WIDE_TELE_SVDD
PP1V8_IO
PP1V1_CAM_TELE_DVDD_CONN
AP_TO_TELE_CLK_CONN
90_LPDP_TELE_TO_AP_D0_CONN_P90_LPDP_TELE_TO_AP_D0_CONN_N
PP2V85_CAM_TELE_AVDD
90_LPDP_TELE_TO_AP_D0_P
PP_CAM_VCM_PVDD_CONNMAKE_BASE=TRUEPP_CAM_TELE_ADC
PP3V3_ROMEO_WIDE_TELE_SVDD
PP2V85_CAM_TELE_AVDD_CONNPP2V85_CAM_TELE_AVDD
PP1V1_CAM_TELE_DVDD_CONNPP1V1_CAM_TELE_DVDD
LPDP_TELE_BI_AP_AUX_CONNWIDE_AND_TELE_TO_STROBE_DRIVER_EN
90_LPDP_TELE_TO_AP_D2_CONN_N90_LPDP_TELE_TO_AP_D2_CONN_P
ISP_TO_TELE_SHUTDOWN_L
AP_TO_TELE_CLK AP_TO_TELE_CLK_CONN
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
CAMERA: B2B Tele [MT]
49.9
ROOM=B2B_TELE_RCAM01005
1/32W1%
MF
18UF
CER-X5R
ROOM=CAM_PMU
0402-0.1MM
6.3V20%
CERM-X5R
ROOM=CAM_PMU
20%6.3V
4UF
0201
4UF
ROOM=CAM_PMU
CERM-X5R6.3V20%
0201
33 32 31
6.3V20%2.2UF
X5R-CERM
ROOM=B2B_TELE_RCAM0201
ROOM=B2B_TELE_RCAM
0.00
01005
0%
MF1/32W
18
18
AA26DK-S026VA1F-ST-SM
ROOM=B2B_TELE_RCAM
ROOM=B2B_TELE_CAM0201
FERR-33OHM-25%-1.5A
6.3V
ROOM=B2B_TELE_RCAM
20%2.2UF
X5R-CERM0201
ROOM=B2B_TELE_RCAM
0.1UF20%6.3VX5R-CERM01005
10-OHM-750MA
01005-1ROOM=B2B_TELE_RCAM
220PF5%25V
01005ROOM=B2B_TELE_RCAM
COG COG01005
220PF25V5%
ROOM=B2B_TELE_RCAM
ROOM=B2B_TELE_RCAM
220PF5%25VCOG01005
ROOM=B2B_TELE_RCAM
25VCOG01005
220PF5%
5%
01005
25V
ROOM=B2B_TELE_RCAM
COG
220PF
ROOM=B2B_TELE_RCAM01005
25VCOG
220PF5%
10
18
18
18
18
32 31
32 9
17
53 32
53 32
ROOM=B2B_TELE_RCAM
01005
6.3VX5R-CERM
GND_VOID20%
0.1UF
0.1UF
01005
GND_VOID
X5R-CERM6.3V
ROOM=B2B_TELE_RCAM 20%
ROOM=B2B_TELE_RCAM
6.3V20%
X5R-CERM
0.1UF
01005
NP0-C0G-CERM25V
ROOM=B2B_TELE_RCAM01005
5%56PF
56PF
ROOM=B2B_TELE_RCAM
25V5%
01005NP0-C0G-CERM
25V5%56PF
01005NP0-C0G-CERM
ROOM=B2B_TELE_RCAM
GND_VOIDROOM=B2B_TELE_RCAM
0.1UF
20%6.3V
X5R-CERM01005
GND_VOID
0.1UF
ROOM=B2B_TELE_RCAM
01005
6.3V20%
X5R-CERM
20%
X5R-CERM6.3V
GND_VOID
0.1UF
ROOM=B2B_TELE_RCAM
01005
ROOM=B2B_TELE_RCAM
6.3V
0.1UF
01005
20%
X5R-CERM
GND_VOID
NP0-C0G-CERM
5%56PF25V
01005
NOSTUFFROOM=B2B_TELE_RCAM
25V
01005ROOM=B2B_TELE_RCAM
COG
220PF5%
ROOM=B2B_TELE_RCAM
25VCOG01005
220PF5%
25V
220PF5%
COG01005
ROOM=B2B_TELE_RCAM
32 31
32
32
32
32 31
32
32
32 31
32
32
32
32
32
32
32
32
32 9
32
37 32 31 29
53 52 44 37 36 34 31 30 29 20 19 17 6
32
32
32
32
32
32 31
32
37 32 31 29
32 32
32 32
32
33 32 31
32
32
32
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
BI
IN
VIETMOBILE.VN
I2C Address (7-bit): 0x67APN:353S00868
INT 300K PD
INT 300K PD
INT 300K PD
INT 300K PD
INT 300K PD
INT 300K PD
LED STROBE DRIVERS (NEON)
APN:353S00558I2C Address (7-bit): 0x63
33 OF 60
I2C3_ISP_SDA
I2C3_ISP_SDAI2C3_ISP_SCL
I2C3_ISP_SCL
7.0.0
41 OF 85
051-02545
2
1 C4126
2
1 C4106
2
1C4196
2
1C41912
1 C4193
D2
C3
B1
B2
A3B3
C1
D1
D3
A2
C2
A1
U4120
D2
C3
B1
B2
A3B3
C1
D1
D3
A2
C2
A1
U4100
2
1
L4120
2
1 C4105
2
1
L4100
2
1 C41212
1 C4122
2
1 C41012
1 C4102
2
1 C4125
LED_DRIVER1_LX
STROBE_MODULE_NTC
WIDE_AND_TELE_TO_STROBE_DRIVER_EN
BB_TO_MANY_GSM_BURST_IND
PP_STROBE_DRIVER1_COOL_LED
PP_STROBE_DRIVER1_WARM_LEDWIDE_AND_TELE_TO_STROBE_DRIVER_EN
BB_TO_MANY_GSM_BURST_IND
CAMPMU_TO_STROBE_DRIVER_HWEN
STROBE_MODULE_NTC
CAMPMU_TO_STROBE_DRIVER_HWEN
PP_LED2_BOOST_OUT
PP_STROBE_DRIVER2_COOL_LED
PP_STROBE_DRIVER2_WARM_LED
PP_LED1_BOOST_OUT
PP_VDD_MAIN
LED_DRIVER2_LX
SYNC_MASTER=test_mlb SYNC_DATE=03/22/2017
CAMERA: Strobe Drivers
5%
01005COG25V
ROOM=STROBE
220PFCRITICAL
ROOM=STROBE
1UH-20%-3.6A-0.062OHMPIWE20160H-SM
5%220PF
01005COG25V
ROOM=STROBE2
5%220PF
01005COG25V
ROOM=STROBE2
01005COG25V5%220PF
ROOM=STROBEROOM=STROBE
5%220PF
01005COG25V
5%25V
ROOM=STROBE201005
220PF
COG
20%15UF
CERM6.3V
0402-0.1MMROOM=STROBE
20%15UF
CERM6.3V
0402-0.1MMROOM=STROBE
20%15UF
CERM6.3V
0402-0.1MMROOM=STROBE
20%15UF
CERM6.3V
0402-0.1MMROOM=STROBE
220PF25VCOG01005
5%
ROOM=B2B_FCAM
ROOM=STROBE
CRITICAL
LM3566DSBGA
CRITICALROOM=STROBE2
DSBGALM35662
CRITICAL
ROOM=STROBE2PIWE20160H-SM1UH-20%-3.6A-0.062OHM
35 33
35 33
33 30
33 32 31
57 38 33
53
53
53
53
57 38 33
33 32 31
33 30
35
35
35
35
59 47 45 44 43 42 41 36 29 26 24 22 17
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TORCH/TEMPSDASCL
TX
HWEN
STROBE
GND
LED2
LED1
OUTIN
SW
TORCH/TEMPSDASCL
TX
HWEN
STROBE
GND
LED2
LED1
OUTIN
SW
IN
IN
IN
IN
IN
BI
IN
IN
BI
IN
IN
IN
VIETMOBILE.VN
FCAM I/O
<-- This one on MLB
ISP I2C2
FCAM ConnectorLONG ISLAND POWER
NOTE: SAME I2C as FCAM
Plug: 516S00245Rcpt: 516S00244
LPDP FILTERS
34 OF 60
I2C2_ISP_SDA34 53
I2C2_ISP_SDA
I2C2_ISP_SCL34 53
I2C2_ISP_SCL
7.0.0
42 OF 85
051-02545
21
R4210
2
1 C3705
2
1 C4210
2
1 C423521
C4234
21
C4233
21
C4232
21
C4230
21
C4231
2
1 C4212
24
23
2221
2019
181716151413121110987654321
J4200
2
1 C4220
2
1 C4221
21
FL4204
2
1 C4205
2
1 C4203
2
1 C4201
21
FL4202
2
1 C4211
2
1 C4204
2
1 C4200
2
1 C4202
21
FL4200
PP2V85_FCAM_AVDD_CONN
90_LPDP_FCAM_TO_AP_D0_P
90_LPDP_FCAM_TO_AP_D1_CONN_N
90_LPDP_FCAM_TO_AP_D1_N
90_LPDP_FCAM_TO_AP_D0_N
90_LPDP_FCAM_TO_AP_D1_CONN_N
PP2V85_FCAM_AVDD
PP1V1_FCAM_DVDD
PP1V8_IO
LPDP_FCAM_BI_AP_AUX_CONN
90_LPDP_FCAM_TO_AP_D0_CONN_P
90_LPDP_FCAM_TO_AP_D0_CONN_N
90_LPDP_FCAM_TO_AP_D1_CONN_P90_LPDP_FCAM_TO_AP_D1_P
PP1V8_FCAM_VDDIO_CONN
PP1V8_FCAM_VDDIO_CONN
LPDP_FCAM_BI_AP_AUX
FCAM_TO_JULIET_SYNC
PP1V1_FCAM_DVDD_CONN
90_LPDP_FCAM_TO_AP_D0_CONN_N
AP_TO_FCAM_CLK_CONNAP_TO_FCAM_CLK
ISP_TO_FCAM_SHUTDOWN_L
PP1V1_FCAM_DVDD_CONN
90_LPDP_FCAM_TO_AP_D0_CONN_P
90_LPDP_FCAM_TO_AP_D1_CONN_PLPDP_FCAM_BI_AP_AUX_CONNAP_TO_FCAM_CLK_CONNISP_TO_FCAM_SHUTDOWN_L
FCAM_TO_JULIET_SYNCPP2V85_FCAM_AVDD_CONN
SYNC_DATE=10/13/2016SYNC_MASTER=test_mlb
CAMERA: B2B Fcam
ROOM=B2B_FCAM01005MF
49.9
1%1/32W
0402-0.1MMROOM=CAM_PMU
6.3V20%18UF
CER-X5R
NOSTUFF
56PF25V
ROOM=B2B_FCAM
01005NP0-C0G-CERM5%
18
18
18
18
NP0-C0G-CERM
ROOM=B2B_FCAM
25V
56PF
01005
5%
0.1UF
20%
X5R-CERM6.3V
01005
ROOM=B2B_FCAM10
0.1UF
GND_VOID=TRUE
X5R-CERM6.3V20%
ROOM=B2B_FCAM
01005
0.1UF
GND_VOID=TRUE
6.3VX5R-CERM
20%
01005
ROOM=B2B_FCAM
6.3V20%
GND_VOID=TRUE
X5R-CERM01005
0.1UF
ROOM=B2B_FCAM
ROOM=B2B_FCAM
X5R-CERM
0.1UF
GND_VOID=TRUE
6.3V20%
01005
37 34
100PF
NP0-C0G01005ROOM=B2B_FCAM
5%16V
53 34
53 34
34 9
17
ROOM=B2B_FCAM
BB35K-RA18-3AF-ST-SM
NOSTUFF
01005
5%25VNP0-C0G-CERM
56PF
ROOM=B2B_FCAM
NOSTUFF
5%25V56PF
NP0-C0G-CERM01005ROOM=B2B_FCAM
ROOM=B2B_FCAM
01005-1
10-OHM-750MA
220PF25VCOG01005ROOM=B2B_FCAM
5%
220PF5%25VCOG
ROOM=B2B_FCAM01005
25VCOG01005
220PF5%
ROOM=B2B_FCAM
10-OHM-750MA
01005-1ROOM=B2B_FCAM
5%COG25V
ROOM=B2B_FCAM
01005
220PF
ROOM=B2B_FCAM
X5R-CERM6.3V20%
01005
0.1UF
01005ROOM=B2B_FCAM
0.1UF20%6.3VX5R-CERM
01005
20%6.3V0.1UF
X5R-CERMROOM=B2B_FCAM
01005-1
10-OHM-750MA
ROOM=B2B_FCAM
34
34
34
29
29
53 52 44 37 36 32 31 30 29 20 19 17 6
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34 9
37 34
34
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
OUT
BI
OUT
BI
IN
IN
IN
VIETMOBILE.VN
PENROSE
Power Key Button
MIC2 (ANC REF)
Strobe Filtering
Rcpt: 516S00381Plug: 516S00382
Strobe Connector<-- This one on MLB
35 OF 60
I2C1_AP_SDA
I2C1_AP_SCL
GND
I2C1_AP_SCL35 52
I2C1_AP_SDA35 52
MAKE_BASE=TRUE
7.0.0
43 OF 85
051-02545
21
XW4301
21
XW4300
2019
1817
1615
1413
121110987654321
J4300
21
FL4331
2
1 C4332
2
1C4326
2
1C4324
2
1C4322
2
1C4320
2
1 C4330
21
FL4330
2
1R4330
2 1
FL4307
2 1
FL4306
21
FL4303
2 1
FL4305
2
1 C43032
1 C4304
2
1 C4307
2
1 C4306
2
1 C4305
21
FL4301
2
1 C4302
2
1 C4309
2
1 C4308
2
1C431021
R4310
2
1
DZ4310
PP_STROBE_DRIVER2_COOL_LED
PP_STROBE_DRIVER1_COOL_LED
BUTTON_POWER_KEY_L BUTTON_POWER_KEY_CONN_L
PP_STROBE_DRIVER2_WARM_LED
PP_STROBE_DRIVER1_COOL_LED
PP_STROBE_DRIVER1_WARM_LED
REARMIC2_TO_CODEC_AIN2_N REARMIC2_TO_CODEC_AIN2_CONN_N
STROBE_MODULE_NTC_CONNSTROBE_MODULE_NTC
PP3V0_PENROSE_CONNPP3V0_PENROSE
PP_CODEC_TO_REARMIC2_BIAS PP_CODEC_TO_REARMIC2_BIAS_CONN
REARMIC2_TO_CODEC_AIN2_P REARMIC2_TO_CODEC_AIN2_CONN_P
PENROSE_IR_TO_CODEC_AIN5_CONN_P
REARMIC2_TO_CODEC_BIAS_FILT_RET
PP_STROBE_DRIVER2_COOL_LED
BUTTON_POWER_KEY_CONN_L
PP_STROBE_DRIVER1_WARM_LED
PP3V0_PENROSE_CONN
PENROSE_IR_TO_CODEC_AIN5_CONN_N
REARMIC2_TO_CODEC_AIN2_CONN_P
PENROSE_VIS_TO_CODEC_AIN7_CONN_N
PENROSE_VIS_TO_CODEC_AIN7_P PENROSE_VIS_TO_CODEC_AIN7_CONN_P
REARMIC2_TO_CODEC_AIN2_CONN_N
PP_CODEC_TO_REARMIC2_BIAS_CONN
PP_STROBE_DRIVER2_WARM_LEDPENROSE_IR_TO_CODEC_AIN5_P
STROBE_MODULE_NTC_CONN
PENROSE_VIS_TO_CODEC_AIN7_CONN_PPENROSE_IR_TO_CODEC_AIN5_CONN_P
CAMERA: B2B Strobe + Hold ButtonSYNC_DATE=03/22/2017SYNC_MASTER=test_mlb
F-ST-SMAA36D-S012VA1
ROOM=B2B_STROBE
39
01005
FERR-150OHM-25%-200MA
ROOM=B2B_STROBE
01005NP0-C0G-CERM
5%
ROOM=B2B_STROBE
25V
56PF
33
23 01005
5%220PF
25VCOG
ROOM=B2B_STROBE
01005
220PF
COG
5%25V
ROOM=B2B_STROBE
01005
25V
ROOM=B2B_STROBE
5%
COG
220PF
01005ROOM=B2B_STROBE
25VCOG
5%220PF
01005ROOM=B2B_STROBE
25VCOG
220PF5%
FERR-150OHM-25%-200MA
01005
ROOM=B2B_STROBE
01005ROOM=B2B_STROBE
MF1/32W0.5%27K
39
39
39
FERR-150OHM-25%-200MA
01005
ROOM=B2B_STROBE
FERR-150OHM-25%-200MA
01005ROOM=B2B_STROBE
FERR-150OHM-25%-200MA
01005ROOM=B2B_STROBE
FERR-150OHM-25%-200MA
01005ROOM=B2B_STROBE
2.2UF
ROOM=B2B_STROBE
20%
X5R-CERM0201
6.3V
01005
5%
COG25V
220PF
ROOM=B2B_STROBE
01005
5%25V
ROOM=B2B_STROBE
56PF
NP0-C0G-CERM
01005NP0-C0G-CERM25V5%
ROOM=B2B_STROBE
56PF
01005
5%
COG25V
220PF
ROOM=B2B_STROBE
FERR-150OHM-25%-200MA
01005ROOM=B2B_STROBE
0201ROOM=B2B_STROBE
5.5V-6.2PF
01005NP0-C0G-CERM25V
ROOM=B2B_STROBE
56PF5%
52 35
52 35
01005ROOM=B2B_STROBE
56PF25V5%NP0-C0G-CERM
01005ROOM=B2B_STROBE
NP0-C0G-CERM
56PF25V5%
ROOM=B2B_STROBE
6.3V
27PF
NP0-C0G0201
5%
SHORT-10L-0.05MM-SM
SHORT-10L-0.05MM-SM
01005
5%
MF1/32W
ROOM=B2B_STROBE
100
35 33
35 33
35
35 33
35 33
35 33
35
35
35 22
40 35
35
35
40
35 33
35
35 33
35
39
35
39
35
35
35
35 33
35
35
35
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
OUT
OUT
OUT
BI
IN
VIETMOBILE.VN
Rigel ALTs
Rigel Driver
Test Mode Debugging Terminate @ Cap via on VDD_MAIN plane.
36 OF 60
I2C3_ISP_SDAI2C3_ISP_SCL
7.0.0
44 OF 85
051-02545
2
1C4498
2
1C4497
2 1
L4401
2 1
L4400
C8C7
E1D2D1
E10D9
D10 K8K7K6K5K4
H5A3A2A1A9A8A10
F2F1E2F9F10
E9 F5 H8C5
B2B1
B9B10
G9
G2
J3J2J1
K10J10H10
H4
B8
B5
B7
B6
D4
A4
A6A5
J8J7J6J5J4C2C1C9C10
G6G5
C4
G4
A7
H7
G10
G1
K3K2K1
H3H2H1
J9K9H9
B4
G7E6F8E5F3D7D6D5C3 C6 G8
G3H6F6
B3
D3
D8
E3
E8
U4400
2
1C4411
2
1C4410
2
1C4405
2
1C4400
2 1
R4400
2
1R4491
2
1C4412
2
1C4401
21
XW4400
2
1C4421
2
1C4420
2
1 C4494
2
1 C4493
2
1 C4492
2
1 C4491
2
1 C4490
2
1C44962
1C4495
2
1 C4422
PP_VDD_MAIN
PP_RIGEL_VINCORE
PP_VDD_BOOST
YOGI_TO_RIGEL_STATUSMAMA_BEAR_BI_RIGEL_STATUS
RIGEL_VLXA
RIGEL_TESTMODE
JULIET_PMU_TO_RIGEL_STROBE
CAMPMU_TO_RIGEL_ENABLE
RIGEL_TESTMODE
RIGEL_VCXB
PP_ROMEO_A_ANODE
RIGEL_BOOSTSDB
RIGEL_VCXA
RIGEL_BULKSDB
RIGEL_BULKSDARIGEL_BOOSTSDA
PP_ROSALINE_ANODE
PP_ROMEO_SPARSE_ANODE
PP_ROMEO_DENSE_ANODE
I2C3_RIGEL_SDA_R
RIGEL_TO_ISP_INT
AP_TO_RIGEL_CLK
PP_ROMEO_B_ANODE
PP_RIGEL_BUCK_BOOST_A
RIGEL_VLXB
PP_RIGEL_BUCK_BOOST_B
ROMEO_TO_RIGEL_VCSEL_NTC
RIGEL_LSCP
PP_VANA
PP_ROMEO_CATHODE
PP1V8_IO
PEARL: Power
RIGEL Inductors152S00640152S00720 L4400,L4401ALT_PARTS
ROOM=RIGEL01005
MF1/32W
5%10K
220PF25VCOG
5%
ROOM=RIGEL01005
01005
25VCOG
5%220PF
ROOM=RIGEL
ROOM=RIGEL
SHORT-20L-0.05MM-SM
OMIT
53
53
23 9 5
17
37
30 5
37
0.01UF
01005ROOM=RIGEL
X5R
10%6.3V
01005X5R
ROOM=RIGEL
10%0.01UF
6.3V
4UF
ROOM=RIGEL
CERM-X5R6.3V
0201
20%
ROOM=RIGEL
CERM-X5R
4UF6.3V20%
0201
4UF
ROOM=RIGEL
CERM-X5R6.3V
0201
20%
CERM-X5R
ROOM=RIGEL
4UF6.3V
0201
20%
20%1.0UF10VX5R-CERM0201-1ROOM=RIGEL
10V
1.0UF20%
0201-1ROOM=RIGEL
X5R-CERM0201-1
20%10V
1.0UF
ROOM=RIGEL
X5R-CERM
0.01UF
ROOM=RIGEL
10%
01005X5R6.3V
0201
20%2.2UF
ROOM=RIGEL
6.3VX5R-CERM
ROOM=RIGEL
20%15UF
0402-0.1MMCERM6.3V
0.47UH-20%-4A-0.048OHM
PIWA20120H-SM
0.47UH-20%-4A-0.048OHM
PIWA20120H-SMWLCSP
STB601A0
ROOM=RIGELCRITICAL
0402ROOM=RIGEL
X5R
20%25V
4.7UF
ROOM=RIGEL0402
4.7UF20%25VX5R
4.7UF
ROOM=RIGEL
X5R25V
0402
20%
ROOM=RIGEL
X5R25V20%
4.7UF
0402
37 30
38 30
ROOM=RIGEL
01005MF
1/32W1%
33.2
59 47 45 44 43 42 41 33 29 26 24 22 17
59 47 46 40 29 24 22 17
36
36
37
38
37
37 5
37
37 5
53 52 44 37 34 32 31 30 29 20 19 17 6
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
BI
IN
OUT
IN
IN
IN
IN
LSCP
PD1PD0
SCLSDA
INT
MCLK
TEST
TESTMODE2
VINS
UB
IOUT2
IOUT3
IOUT4
IOUT2
IOUT1IOUT1IOUT1
IOUT2
VBBOUTBVBBOUTBVBBOUTB
IOUT0IOUT0IOUT0
VLXBVLXB
VLXB
BOOSTSDA
BOOSTSDBBULKSDB
VCXBVCXB
VCXAVCXA
BULKSDA
VBBOUTA
VBBOUTA
VLXA
VLXAVLXA
PGND
B
PGND
APG
NDA
GND
S
GND
SG
NDS
PGND
B
GND
S
GND
S
GND
SG
NDS
GND
S
GND
S
GND
CORE
2
GND
CORE
GND
D
GND
CORE
3
PGND
K
PGND
KPG
NDK
GND
CORE
4
PGND
KPG
NDK
TESTMODE
STROBETHROT
XEF0
ENA
OTPHV
TAMP
XEF1
NTC
VKVKVKVK
VINS
DAVI
NSDA
VINS
DA
VINS
UAVI
NSUA
VINS
UA
VINS
DB
VINS
DB
VANA
VINV
CORE
2
VDDI
O
VCC4
VCC3
VIN_
LVT
VINS
UBVI
NSUB
VINS
DB
VINC
ORE
VKVBBOUTA
BI
BI
VIETMOBILE.VN
NOTE: SAME I2C as FCAMJuliet Power and I/O
ISP I2C3
Romeo Power Filtering <-- This one on MLBPlug: 516S00268Rcpt: 516S00267
Romeo I/O
<-- This one on MLB
Juliet Connector
Romeo Connector
Plug: 516S00245Rcpt: 516S00244
37 OF 60
I2C2_ISP_SDA37 53
I2C2_ISP_SCL37 53
I2C3_ISP_SCL37 53
I2C3_ISP_SDA37 53
I2C3_ISP_SDA
I2C3_ISP_SCL
I2C2_ISP_SDA37 53
I2C2_ISP_SCL37 53
7.0.0
45 OF 85
051-02545
2
1C4562
2
1C4581
2
1C4580
2
1 C45972
1 C4596
2
1 C4570
2
1 C457221
FL4572
2
1 C4554
2
1 C45742
1 C457521
FL4574
2
1 C4564
2
1 C4563
2
1 C4560
2
1 C4556
2
1 C4555
2
1 C4571
2
1 C4573
2
1 C45932
1 C45942
1 C45952
1 C4592
2
1 C4552
2
1 C4553
1817
1615
1413
1211
10987654321
J4500
24
23
2221
2019
181716151413121110987654321
J4530
PP2V85_CAM_JULIET_AVDD PP2V85_JULIET_AVDD_CONN
PP_ROMEO_DENSE_ANODE
PP_ROMEO_B_ANODE
PP1V8_IO PP1V8_JULIET_VDDIO_CONN
PP_ROMEO_SPARSE_ANODE PP_ROMEO_DENSE_ANODE
PP_ROMEO_B_ANODE
PP_ROMEO_CATHODE
JULIET_PMU_TO_RIGEL_STROBE
FCAM_TO_JULIET_SYNC
PP3V3_ROMEO_WIDE_TELE_SVDD PP_ROMEO_CATHODE
90_MIPI_JULIET_TO_AP_DATA0_N
PP_ROMEO_SPARSE_ANODE
PP1V1_CAM_JULIET_DVDD
90_MIPI_JULIET_TO_AP_DATA1_P90_MIPI_JULIET_TO_AP_DATA1_N
90_MIPI_JULIET_TO_AP_DATA0_P
PP_ROMEO_CATHODE
PP_ROMEO_A_ANODE
PP_ROMEO_DENSE_ANODE
PP1V8_JULIET_VDDIO_CONN
ROMEO_TO_RIGEL_VCSEL_NTC
ROMEO_TO_AOP_B2B_DETECT
PP_ROMEO_A_ANODE
PP_ROMEO_CATHODE
ROMEO_TO_RIGEL_VCSEL_NTCROMEO_TO_AOP_B2B_DETECT
PP3V3_ROMEO_WIDE_TELE_SVDD
MAMA_BEAR_BI_RIGEL_STATUS
PP_ROMEO_SPARSE_ANODE
PP_ROMEO_CATHODE
MAMA_BEAR_BI_RIGEL_STATUS
JULIET_PMU_TO_RIGEL_STROBE
ISP_TO_JULIET_SHUTDOWN_L
AP_TO_JULIET_CLK
PP1V1_CAM_JULIET_DVDD
FCAM_TO_JULIET_SYNCPP2V85_JULIET_AVDD_CONN
ISP_TO_JULIET_SHUTDOWN_L
AP_TO_JULIET_CLK
90_MIPI_JULIET_TO_AP_CLK_N90_MIPI_JULIET_TO_AP_CLK_P
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
PEARL: B2B Romeo + Juliet
220PF5%
01005COG25V
ROOM=B2B_PEARL
5%
01005ROOM=B2B_PEARL
NP0-C0G-CERM
56PF25V
5%
01005NP0-C0G-CERM
56PF25V
ROOM=B2B_PEARL
AA36D-S010VA1
ROOM=B2B_PEARL
F-ST-SM
ROOM=B2B_PEARL
BB35K-RA18-3AF-ST-SM
56PF
ROOM=B2B_PEARL
25V
01005
5%
NP0-C0G-CERM
NP0-C0G-CERM
5%
01005
25V
ROOM=B2B_PEARL
56PF
56PF
NP0-C0G-CERM
ROOM=B2B_PEARL
25V
01005
5%
5%220PF
01005
25V
ROOM=B2B_PEARL
COG
ROOM=B2B_PEARL01005
5%220PF
COG25V
6.3V
ROOM=B2B_PEARL
0.1UF
01005X5R-CERM20%
ROOM=B2B_PEARL
01005
6.3VX5R-CERM
0.1UF20%
10-OHM-750MA
01005-1ROOM=B2B_PEARL
56 37
ROOM=B2B_PEARL01005COG25V
220PF5%
01005ROOM=B2B_PEARL
X5R-CERM20%6.3V0.1UF
5%220PF
01005COG25V
ROOM=B2B_PEARL
01005-1ROOM=B2B_PEARL
10-OHM-750MA
37 34
5%220PF
01005COG25V
ROOM=B2B_PEARL
37 36
37 17
37 9
5%220PF
01005ROOM=B2B_PEARL
COG25V
01005ROOM=B2B_PEARL
5%220PF
COG25V
37 36 30
37 36
53 37
53 37
COG25V
ROOM=B2B_PEARL01005
5%220PF
25V5%
ROOM=B2B_PEARL01005COG
220PF
5%220PF
01005COG25V
ROOM=B2B_PEARL
5%220PF25V
ROOM=B2B_PEARL01005COG
ROOM=B2B_PEARL
5%220PF
01005COG25V
ROOM=B2B_PEARL
5%220PF
COG25V
01005ROOM=B2B_PEARL
5%
01005
25V
220PF
COG
29 37
37 36 5
37 36
53 52 44 36 34 32 31 30 29 20 19 17 6 37
37 36 37 36 5
37 36
37 36 5
37 36
37 32 31 29 37 36 5
9
37 36
37 17
9
9
9
37 36 5
37 36
37 36 5
37
37 36
37 36 5
37 36
56 37
37 32 31 29
37 36
37 36 5
37 36 30
37 17
37 34
37
37 9
37 17
9
9
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
PWR
SIGNAL
PWR
OUT
IN
OUT
IN
IN
IN
OUT
BI
IN
VIETMOBILE.VN
Yogi Signals
PROX/ALS/YOGI I/O
PROX & HALL POWER
MIC3
Rosaline + Sensor Connector<-- This one on MLBRcpt: 516S00325
Plug: 516S00326
AOP I2C
HALL I/Os
SPEAKER2
38 OF 60
I2C0_AOP_SDA
I2C0_AOP_SCL
I2C0_AOP_SCL38 54 I2C0_AOP_SDA 38 54
7.0.0
46 OF 85
051-02545
2
1 C4660
2
1 C4680
2
1 DZ4691
2
1 DZ4690
2 1
FL4691
2 1
FL4690
21
R4612
2
1 C4602
2
1 C4633
2
1 C4631
21
R4619
21
R4633
21
R4634
2
1 C4619
34
33
3231
3029
28272625242322212019181716151413121110987654321
J4600
21
XW4600
2
1C4634
2
1C4635
2
1 C4632
2
1 C4630
2
1 C4650
2
1 C4601
2
1 C4600
2
1 C4618
2
1 C4617
21
R4611
2
1 C46132
1 C4614
2
1 DZ46422 1
FL4642
21
FL4641
2
1 DZ4641
21
FL4640
2
1 DZ4640
COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONNCOIL_TO_SPKRAMP_TOP_VSENSE_NEG
COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONNCOIL_TO_SPKRAMP_TOP_VSENSE_POS
SPKRAMP_TOP_TO_COIL_OUT_NEG
SPKRAMP_TOP_TO_COIL_OUT_POS
CODEC_AOUT_TO_HAC_POS_CONN
PP_CODEC_TO_FRONTMIC3_BIAS_CONN
CODEC_AOUT_TO_HAC_NEG
FRONTMIC3_TO_CODEC_AIN3_P
CODEC_AOUT_TO_HAC_POS
PP3V0_YOGI_PROX_ALS_CONNPP3V0_S2
BB_TO_MANY_GSM_BURST_IND_CONNBB_TO_MANY_GSM_BURST_IND
FRONTMIC3_TO_CODEC_BIAS_FILT_RET
PP3V0_YOGI_PROX_ALS_CONN
HALL_FLAP_TO_AOP_IRQ_L
FRONTMIC3_TO_CODEC_AIN3_N
YOGI_TO_RIGEL_STATUS YOGI_TO_RIGEL_STATUS
SPKRAMP_TOP_TO_COIL_OUT_POS
CODEC_AOUT_TO_HAC_NEG_CONN
YOGI_TO_RIGEL_STATUS
PP_ROSALINE_ANODE
PROX_BI_AOP_INT_L
PP1V8_S2_HALL_CONN
FRONTMIC3_TO_CODEC_AIN3_CONN_NFRONTMIC3_TO_CODEC_AIN3_CONN_PPP_CODEC_TO_FRONTMIC3_BIAS_CONN
PROX_BI_AOP_INT_L
PP1V8_S2 PP1V8_S2_HALL_CONN
ALS_TO_AOP_INT_L ALS_TO_AOP_INT_L
PP_CODEC_TO_FRONTMIC3_BIAS
SPKRAMP_TOP_TO_COIL_OUT_NEG
COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONN
PP_ROSALINE_ANODE
ALS_TO_AOP_INT_L
CODEC_AOUT_TO_HAC_POS_CONNCOIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONN
HALL_FLAP_TO_AOP_IRQ_LBB_TO_MANY_GSM_BURST_IND_CONN
CODEC_AOUT_TO_HAC_NEG_CONN
FRONTMIC3_TO_CODEC_AIN3_CONN_P
FRONTMIC3_TO_CODEC_AIN3_CONN_N
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
PEARL: B2B Rosaline + Sensor25V
ROOM=B2B_PEARL
COG
5%
01005
220PF
38 36 30
38
36 30
42 38
42 38
42
42
39
39
56 38 56 38
56 38
54 38
54 38
25V5%
NP0-C0G-CERM
56PF
01005ROOM=B2B_PEARL
25V5%56PF
ROOM=B2B_PEARL
NP0-C0G-CERM01005
220PF
01005ROOM=B2B_PEARL
5%25VCOG
ROOM=B2B_PEARL01005
5%220PF
COG25V
MF1/32W
ROOM=B2B_PEARL01005
0%
0.00
2.2UF
X5R-CERM6.3V
0201ROOM=B2B_PEARL
20%
ROOM=B2B_PEARL
220PF25VCOG
5%
01005
01005ROOM=B2B_PEARL
6.8V-100PFROOM=B2B_PEARL
01005
FERR-150OHM-25%-200MA
ROOM=B2B_PEARL
FERR-150OHM-25%-200MA
01005
010056.8V-100PFROOM=B2B_PEARL
ROOM=B2B_PEARL01005
FERR-150OHM-25%-200MA
ROOM=B2B_PEARL010056.8V-100PF
56 38
5%
COG25V
01005
220PF
ROOM=B2B_PEARL
220PF25V5%
COG
ROOM=B2B_PEARL01005
010056.8V-100PFROOM=B2B_PEARL
01005ROOM=B2B_PEARL
6.8V-100PF
ROOM=B2B_PEARL
01005
FERR-150OHM-25%-200MA
ROOM=B2B_PEARL
01005
FERR-150OHM-25%-200MA
0%
MF
ROOM=B2B_PEARL
1/32W
0.00
01005
01005COG
5%25V
ROOM=B2B_PEARL
220PF
0201ROOM=B2B_PEARL
X5R
10%1000PF25V
ROOM=B2B_PEARL0201X5R
1000PF25V10%
ROOM=B2B_PEARL
01005MF
1/32W0%
0.00
MF1/32W5%
100
01005ROOM=B2B_PEARL
5%
ROOM=B2B_PEARL01005MF
1/32W
100
57 33
220PF25VCOG
5%
ROOM=B2B_PEARL01005
ROOM=B2B_PEARL
AA26DK-S028VA1F-ST-SM
OMITROOM=B2B_PEARL
SHORT-20L-0.05MM-SM
COG
5%
01005
25V
220PF
ROOM=B2B_PEARL
5%
01005
220PF
ROOM=B2B_PEARL
25VCOG
01005ROOM=B2B_PEARL
25VCOG
5%220PF
01005ROOM=B2B_PEARL
5%220PF
COG25V
38
38
38
38
39
39
38 58
49 48 22
38
40
38
42 38
38
38 36 30
38 36
38
38
38 38
56 38
59
54 50 49 48 42 41 40 25 20 17 38
40
42 38
38
38 36
56 38
38
38
56 38
38
38
38
38
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
BI
IN
IN
OUT
OUT
OUT
OUT
OUT
BI
BI
IN
OUT
IN
VIETMOBILE.VN
CALLAN AUDIO CODEC (ANALOG INPUTS & OUTPUTS)
||V
||
Place Near B2B
^
39 OF 60
7.0.0
47 OF 85
051-02545
2 1
C4301
2 1
C4300
2
1 R4710
F9F10
B9A10
B10B11
G1
E1F1
F8E9
D9D10
E10E11
D8B8
K8L8
C2D3
F4E3
F3G4
G3G2
K5L5
K6L6
K4L4
K3L3
U4700
21
C4701
21
R4701
21
R4700
21
C4700
90_MIKEYBUS_DATA_N
LOWERMIC1_TO_CODEC_AIN1_PLOWERMIC1_TO_CODEC_AIN1_N
REARMIC2_TO_CODEC_AIN2_N
PENROSE_IR_TO_CODEC_AIN5_P
LOWERMIC4_TO_CODEC_AIN4_P
CODEC_AOUT_TO_HAC_POSCODEC_AOUT_TO_HAC_NEG
PENROSE_VIS_TO_CODEC_AIN7_CONN_N
90_MIKEYBUS_DATA_P
PENROSE_IR_TO_CODEC_AIN5_CONN_N
90_MIKEYBUS_CODEC_DATA_N90_MIKEYBUS_CODEC_DATA_P
MIKEYBUS_REFERENCE
PENROSE_VIS_TO_CODEC_AIN7_P
HALOGEN_VSTIMSTIM_NEG_C
REARMIC2_TO_CODEC_AIN2_P
FRONTMIC3_TO_CODEC_AIN3_PFRONTMIC3_TO_CODEC_AIN3_N
LOWERMIC4_TO_CODEC_AIN4_N
PENROSE_IR_TO_CODEC_AIN5_N
HALOGEN_TIA_IOUT
PDM_CODEC_TO_SPKAMP_TOP_CLK
TIA_NEG_C
PENROSE_VIS_TO_CODEC_AIN7_N
CODEC_TO_HALOGEN_AMP_PDM_OUT
PDM_CODEC_TO_SPKAMP_TOP_DATA
SYNC_DATE=10/13/2016SYNC_MASTER=test_mlb
AUDIO: CODEC (1/2)
ROOM=CODEC
NP0-C0G16V5%
01005
100PF
20.0
5%
MF1/32W
01005ROOM=CODEC
01005ROOM=CODEC
5%
MF1/32W
20.0
100PF
NP0-C0G16V5%
01005ROOM=CODEC
46
46
46
35
35
35
ROOM=B2B_STROBE
01005CER-X5R6.3V
0.22UF
10%
CER-X5R
ROOM=B2B_STROBE
01005
10%
0.22UF
6.3V
46
46
50 49
49
42
42
35
50
50
38
38
35
35
50
50
1005%1/32WMF01005ROOM=CODEC
WLCSPCS42L75
ROOM=CODECCRITICAL 38
38
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
NCNC
NC
IN
IN
IN
IN
IN
IN
IN
NCNC
INBI
BI
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
SYM 1 OF 3
AOUT-AOUT+
AIN3+
MBUS_REF
DNDP
AIN1+AIN1-
AIN2+AIN2-
AIN3-
AIN4+
AIN5+AIN5-
AIN6+AIN6-
AIN7+AIN7-
AIN8+AIN8-
DMIC1_CLKDMIC1_DATA
DMIC3_DATA
DMIC2_CLK
DMIC3_CLK
DMIC2_DATA
DMIC4_CLKDMIC4_DATA
PDMOUT1_CLKPDMOUT1_DATA
PDMOUT2_CLKPDMOUT2_DATA
PDMOUT3_CLKPDMOUT3_DATA
AIN4-
NCNC
NCNC
NCNC
VIETMOBILE.VN
Additional input cap remvoed per rdar 35537162Future designs should re-add
CALLAN AUDIO CODEC (POWER & I/O)
40 OF 60
7.0.0
48 OF 85
051-02545
21
R4832
2
1R4800
21
R4830
2
1 C4822
2
1 C48232
1 C4824
2
1 C4825
2 1
XW4802
2
1 C4821
E4
H3
J5J3G10
B2B3
C3A3
J4
C8B7
A5B4A4
E7
F7E8D7
D4
E5E6
J8J7J6H7H6H2H1G7G6G5F5H4
H5
C7
F6
A7
D11C10
C11C9
C5D6
C4D5
B6B5
A6C6
U4700
G11
B1 F2L9A2 A9C1 K2J2J1G9G8
H10H11
H8H9
J9K9
J10J11
K10K11
D1D2
L11
L10L7L1K7F11E2A11A8A1
K1L2
U4700
2
1 C4805
2
1 C4809
2
1 C48122
1 C4814
21
C4802
2
1 C48152
1 C4813
2
1 C4820
2
1 C4811
21
C4801
21
C4804
21
C4803
2
1 C4808
SPI_AP_TO_CODEC_CS_L
SPI_AP_TO_CODEC_MOSISPI_CODEC_TO_AP_MISO
CODEC_TO_PMU_WAKE_L
AOP_TO_CODEC_GPIO1
I2S_AP_TO_CODEC_ASP3_LRCLK
AOP_TO_CODEC_CLP_EN
CODEC_FILTP
I2S_AP_TO_CODEC_ASP3_DOUT
I2S_AOP_TO_CODEC_MCLK2
I2S_AOP_TO_CODEC_ASP2_DOUT
I2S_AOP_TO_CODEC_ASP2_BCLK
I2S_AP_TO_CODEC_ASP3_BCLK
FRONTMIC3_BIAS_FILT_IN
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
I2S_AOP_TO_CODEC_ASP2_LRCLK
I2S_CODEC_ASP2_TO_AOP_DIN
I2S_AP_TO_CODEC_MCLK1
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLKI2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
CODEC_TO_SPKRAMP_BOT_ARC_MCLK_RCODEC_TO_SPKRAMP_BOT_ARC_MCLK
CODEC_LP_FILTNCODEC_LP_FILTP
CODEC_TO_AOP_GPIO2
CODEC_AGND
SPI_AP_TO_CODEC_SCLK
I2S_CODEC_ASP3_TO_AP_DIN
PP_CODEC_TO_LOWERMIC4_BIAS
PP_VDD_BOOST
AOP_TO_CODEC_RESET_L
PP1V8_S2
PP_CODEC_TO_FRONTMIC3_BIAS
REARMIC2_BIAS_FILT_IN
PP1V2_CODEC_S2
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_R
PP1V8_S2
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT
LOWERMIC1_TO_CODEC_BIAS_FILT_RET
PP1V8_AUDIO_VA_S2
LOWERMIC4_BIAS_FILT_IN
FRONTMIC3_TO_CODEC_BIAS_FILT_RET
LOWERMIC4_TO_CODEC_BIAS_FILT_RET
CODEC_TO_AP_INT_L
CODEC_AGND
PP_CODEC_TO_REARMIC2_BIASREARMIC2_TO_CODEC_BIAS_FILT_RET
LOWERMIC1_BIAS_FILT_INPP_CODEC_TO_LOWERMIC1_BIAS
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
AUDIO: CODEC (2/2)
20%6.3VX5R-CERM
ROOM=CODEC
2.2UF
0201
20%6.3V
ROOM=CODEC
2.2UF
X5R-CERM0201
20%6.3V0.1UF
01005X5R-CERM
ROOM=CODEC
20%6.3V
01005ROOM=CODEC
0.1UF
X5R-CERM
20%6.3V
402-1.0MMROOM=CODEC
X5R-CERM1
4.7UF
20%6.3V0.1UF
01005X5R-CERM
ROOM=CODEC
20%6.3V
ROOM=CODEC
0.1UF
X5R-CERM01005
20%6.3V0.1UF
ROOM=CODEC01005X5R-CERM
20%6.3VCERM-X5R
10UF
0402-0.1MMROOM=CODEC
20%6.3V
ROOM=CODEC
4.7UF
402-1.0MMX5R-CERM1
20%6.3V
X5R-CERM1402-1.0MMROOM=CODEC
4.7UF
20%6.3V
ROOM=CODEC
4.7UF
402-1.0MMX5R-CERM1
20%6.3V10UF
ROOM=CODEC
CERM-X5R0402-0.1MM
50 43 13
01005
1%1/32W
49.9
MF
ROOM=CODEC
13
ROOM=CODEC01005
MF1/32W
5%100K
56
1%
ROOM=CODEC01005
1/32WMF
33.243 41
13
56
13
50 43 42 41 13 5
50 43 42 41 13
13
13
13
11
11
11
11 5
11
55
11
13
43 42 41 13
11
11 5
11
11
50
38
35
50
20%
ROOM=CODEC
10VX5R-CERM0201-1
1.0UF
20%
ROOM=CODEC
10VX5R-CERM0201-1
1.0UF20%
ROOM=CODEC
10VX5R-CERM0201-1
1.0UF
20%
ROOM=CODEC
10VX5R-CERM0201-1
1.0UF
SHORT-10L-0.1MM-SM
ROOM=CODEC
20%1.0UF
0201-1X5R-CERM10V
ROOM=CODEC
CRITICAL
CS42L75
ROOM=CODEC
WLCSP
CRITICAL
WLCSP
ROOM=CODEC
CS42L75
40
50
59 47 46 36 29 24 22 17
59 54 50 49 48 42 41 40 38 25 20 17
38
59 54 50 49 48 42 41 40 38 25 20 17
22
40
35
50
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
IN
IN
OUT
OUT
NCNC
NCNC
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
NCNC
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
NCNC
SYM 3 OF 3
GNDAGNDAGNDA
TSTITSTI
GNDAGNDA
GNDAGNDA
GNDAGNDA
GNDA
GNDAGNDA
RESET*
ASP2_SDOUT
ASP3_SDOUT
GPIO2GPIO1
JTAG_TDIJTAG_TDO
CLP_EN
SW2_CLKSW2_SD
SW1_SDSW1_CLK
DIGLDO_PULLDNDIGLDO_EN
ASP3_SDIN
ASP3_SCLK
CCLKCS*
INT*
WAKE*
JTAG_TCKJTAG_TMS
ASP3_LRCK/FSYNC
ASP2_SDINASP2_LRCK/FSYNCASP2_SCLK
ASP1_SDOUT
ASP1_LRCK/FSYNCASP1_SDIN
MCLK_OUT
ASP1_SCLK
MOSI
TSTIMCLK2_IN
MISO
MCLK1_IN
SYM 2 OF 3
FILT-FILT+
LP_FILT-LP_FILT+
VP_M
BUSVAVAVAVP
VD_F
ILT
VD_F
ILT VLVD
VL_S
W
MIC2_BIAS
MIC1_BIAS_FILT
GNDD
MIC2_BIAS_FILT
MIC5_BIASMIC5_BIAS_FILT
MIC4_BIASMIC4_BIAS_FILT
MIC6_BIAS_FILTMIC6_BIAS
MIC3_BIASMIC3_BIAS_FILT
MIC1_BIAS
GNDP
NCNCNCNC
VIETMOBILE.VN
Place off of allston GND pin
----->
AP I2C2
AOP I2C1
AMP AD0 AD1 I2C_ADR
1 TBD2
TBD1
TBD1
00
0 0
0
TOP
BOT
ARC
41 OF 60
I2C1_AOP_SCLI2C1_AOP_SDA
7.0.0
49 OF 85
051-02545
21
XW4900
G6G7
C3
F7
C7C6C5A2A1H3H6H2
F4
E5
F6F5
F3
B2B1A3
B4A4
B5A5
B7A7
E1D1
F2F1
H7
C2C1
E7
H5
E4
D6
D4D5
H4
E2D2
E6
G4
E3D3G5C4B6B3A6G1
D7
H1
G2G3
U4902
2
1 C4925
2
1 C4909
2
1 C4900
2
1R4900
2
1 C4907
2
1 C4910
2
1 C4906
2
1 C4908
2
1 C4903
2
1 C49022
1 C4901
2
1 C4911
2
1 C49242
1 C4923
2
1 C49222
1 C49212
1 C4920
BOT_SPK_AGND
BOT_SPK_AGND
PP1V8_S2
BOT_SPK_FILT
BOT_SPK_VA
COIL_TO_SPKRAMP_BOT_VSENSE_NEG
BOT_SPK_FLY_CAP2_NEG
BOT_SPK_FLY_CAP1_NEG
PP_VDD_MAIN
PP1V8_S2
PP1V2_CODEC_S2
COIL_TO_SPKRAMP_BOT_VSENSE_POS
SPKRAMP_BOT_TO_COIL_OUT_NEG
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_DINI2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
CODEC_TO_SPKRAMP_BOT_ARC_MCLK
BOT_SPK_FLY_CAP1_POS
PP_SPKAMP_BOT_VBOOST
SPKRAMP_BOT_TO_COIL_OUT_POS
BOT_SPK_FLY_CAP2_POS
SPKAMP_BOT_ARC_TO_AOP_INT_LSPKAMP_TO_OTHERS_SYNC
AOP_TO_SPKAMP_BOT_RESET_L
BOT_SPK_AGND
AUDIO: SOUTH SPKAMPSYNC_DATE=04/05/2017
ROOM=BOT_SPK
SM
OMIT
ROOM=BOT_SPKCRITICAL
CS35L27WLCSP
20%
CER-X5R16V
0201ROOM=BOT_SPK
1UF
20%6.3V
1UF
X6S-CERM
ROOM=BOT_SPK0201
50 43 42 40 13
43 42 40 13
20%
CER-X5R
18UF
0402-0.1MM
6.3V
ROOM=BOT_SPK
100K5%
1/32WMF
01005
ROOM=BOT_SPK
43 42 5
56 43 5
50 43 42 40 13 5
54
54
43 40
56
CER-X5R
10%6.3V
01005ROOM=BOT_SPK
0.22UF
20%
CER-X5R
18UF
0402-0.1MM
6.3V
ROOM=BOT_SPK
CER-X5R
10%6.3V
01005ROOM=BOT_SPK
0.22UF
CER-X5R
10%6.3V
01005
0.22UF
ROOM=BOT_SPK
CER-X5R
10%6.3V
01005
0.22UF
ROOM=BOT_SPK
20%
CER-X5R
18UF
0402-0.1MM
6.3V
ROOM=BOT_SPK
20%
CER-X5R
18UF
0402-0.1MM
6.3V
ROOM=BOT_SPK
20%
CER-X5R
18UF
0402-0.1MM
6.3V
ROOM=BOT_SPK
10%
X5R-CERM16V
2200PF
01005ROOM=BOT_SPK
25V
01005
220PF5%
ROOM=BOT_SPK
COG10%4.2UF
0402-0.1MMX5R-CERM16V
ROOM=BOT_SPK
10%4.2UF
0402-0.1MMX5R-CERM16V
ROOM=BOT_SPK
10%4.2UF
0402-0.1MMX5R-CERM16V
ROOM=BOT_SPK
41
41
59 54 50 49 48 42 41 40 38 25 20 17
50
59 47 45 44 43 42 36 33 29 26 24 22 17
59 54 50 49 48 42 41 40 38 25 20 17
42 40 22
50
50
50
41
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
MCLKSCLK
VSWIREVASP
FILT+
CF2+
CF1-
VA
CF2+
VSNS+VSNS-
CF2-
VBSTVBST
CF2-
CF2+
CF1-
VPB
CF1+CF1+
VPVD_FILTVL
GNDA GNDB GNDD GNDP
SWIRE_SD2
PDM2_DATA
SCLSDA
FSYNCSDOUT
SDIN
INT*SYNC
RESET*
AD1AD0/GPI
VD_FILT_SELOUT-OUT+
VSPKVSPK
PDM2_CLK
PDM1_DATA/SWIRE_SD1PDM1_CLK/SWIRE_CLK
IN
IN
OUT
OUT
IN
IN
BI
IN
IN
NC
VIETMOBILE.VN
-----> AP I2C2
AOP I2C1
TBD1
I2C_ADR
TBD1
TBD2
AD1
0
0
AD0
0
0
10
AMP
TOP
BOT
ARC
42 OF 60
I2C2_AP_SDAI2C2_AP_SCL
7.0.0
50 OF 85
051-02545
21
XW5000
G6G7
C3
F7
C7C6C5A2A1H3H6H2
F4
E5
F6F5
F3
B2B1A3
B4A4
B5A5
B7A7
E1D1
F2F1
H7
C2C1
E7
H5
E4
D6
D4D5
H4
E2D2
E6
G4
E3D3G5C4B6B3A6G1
D7
H1
G2G3
U5002
2
1 C5025
2
1 C5009
2
1 C5000
2
1 R5000
2
1 C5007
2
1 C50242
1 C50232
1 C50222
1 C50212
1 C5020
2
1 C5003
2
1 C5010
2
1 C50022
1 C5001
2
1 C5011
2
1 C5008
2
1 C5006
TOP_SPK_AGND
TOP_SPK_AGND
PP1V8_S2
TOP_SPK_FILT
COIL_TO_SPKRAMP_TOP_VSENSE_POSCOIL_TO_SPKRAMP_TOP_VSENSE_NEG
TOP_SPK_FLY_CAP2_NEG
TOP_SPK_FLY_CAP2_POS
TOP_SPK_FLY_CAP1_NEG
TOP_SPK_FLY_CAP1_POS
PP_VDD_MAIN
PP1V2_CODEC_S2
PP1V8_S2
SPKAMP_TO_OTHERS_SYNC
SPKRAMP_TOP_TO_COIL_OUT_NEG
SPKRAMP_TOP_TO_COIL_OUT_POS
PP_SPKAMP_TOP_VBOOST
TOP_SPK_VA
PDM_CODEC_TO_SPKAMP_TOP_DATAPDM_CODEC_TO_SPKAMP_TOP_CLK
AP_TO_SPKRAMP_TOP_RESET_LSPKRAMP_TOP_TO_AP_INT_L
I2S_AP_TO_SPKAMP_TOP_MCLKI2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLKI2S_CODEC_ASP1_TO_AOP_AMPS_DIN
TOP_SPK_AGND
SYNC_DATE=04/05/2017
AUDIO: NORTH SPKAMP
10%4.2UF
0402-0.1MMX5R-CERM16V
ROOM=TOP_SPK
10%4.2UF
0402-0.1MMX5R-CERM16V
ROOM=TOP_SPK
10%4.2UF
0402-0.1MMX5R-CERM16V
ROOM=TOP_SPK
CER-X5R
10%6.3V
0.22UF
ROOM=TOP_SPK01005
20%
CER-X5R
18UF
0402-0.1MM
6.3V
ROOM=TOP_SPK
20%
CER-X5R
18UF
0402-0.1MM
6.3V
ROOM=TOP_SPK
20%
CER-X5R
18UF
0402-0.1MM
6.3V
ROOM=TOP_SPK
20%
CER-X5R
18UF
0402-0.1MM
6.3V
ROOM=TOP_SPK
CER-X5R
10%6.3V
01005ROOM=TOP_SPK
0.22UF
CER-X5R
10%6.3V
0.22UF
01005ROOM=TOP_SPK
ROOM=TOP_SPK
OMIT
SM
WLCSP
ROOM=TOP_SPKCRITICAL
CS35L27
20%
CER-X5R16V
0201
1UF
ROOM=TOP_SPK
20%6.3V
1UF
X6S-CERM
ROOM=TOP_SPK0201
50 43 41 40 13
43 41 40 13
20%
CER-X5R
18UF
0402-0.1MM
6.3V
ROOM=TOP_SPK
ROOM=TOP_SPK
100K5%1/32WMF01005
39
39
52
52
50 43 41 40 13 5
11
55
43 41 5
55
CER-X5R
10%6.3V
0.22UF
01005ROOM=TOP_SPK
10%
X5R-CERM16V
01005ROOM=TOP_SPK
2200PF25V
220PF
01005COG
5%
ROOM=TOP_SPK
42
42
59 54 50 49 48 42 41 40 38 25 20 17
38
38
59 47 45 44 43 41 36 33 29 26 24 22 17
41 40 22
59 54 50 49 48 42 41 40 38 25 20 17
38
38
42
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
MCLKSCLK
VSWIREVASP
FILT+
CF2+
CF1-
VA
CF2+
VSNS+VSNS-
CF2-
VBSTVBST
CF2-
CF2+
CF1-
VPB
CF1+CF1+
VPVD_FILTVL
GNDA GNDB GNDD GNDP
SWIRE_SD2
PDM2_DATA
SCLSDA
FSYNCSDOUT
SDIN
INT*SYNC
RESET*
AD1AD0/GPI
VD_FILT_SELOUT-OUT+
VSPKVSPK
PDM2_CLK
PDM1_DATA/SWIRE_SD1PDM1_CLK/SWIRE_CLK
IN
IN
IN
IN
IN
BI
IN
IN
IN
OUT
OUT
VIETMOBILE.VN
Place off of allston GND pin
TBD1
----->
AP I2C2
AOP I2C1
AMP
TBD2
TOP 0
ARC
I2C_ADR
TBD1
AD1
0
AD0
0
10
BOT
0
43 OF 60
I2C1_AOP_SDAI2C1_AOP_SCL
7.0.0
51 OF 85
051-02545
21
XW5100
2
1 R5101
21
R5111
2
1 R5100
21
R5112
G6G7
C3
F7
C7C6C5A2A1H3H6H2
F4
E5
F6F5
F3
B2B1A3
B4A4
B5A5
B7A7
E1D1
F2F1
H7
C2C1
E7
H5
E4
D6
D4D5
H4
E2D2
E6
G4
E3D3G5C4B6B3A6G1
D7
H1
G2G3
U5102
2
1 C5125
2
1 C5109
2
1 C5100
2
1 C5107
2
1 C51242
1 C51232
1 C51222
1 C51212
1 C5120
2
1 C51032
1 C51022
1 C5101
2
1 C5110
2
1 C5111
2
1 C5108
2
1 C5106
PP_VDD_MAIN
ARC_FLY_CAP1_POS
ARC_FLY_CAP2_POS
ARC_FLY_CAP1_NEG
PMU_NFC_TO_ARC_RESET_L
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLKCODEC_TO_SPKRAMP_BOT_ARC_MCLK
NFC_TO_ARC_TRIG
PP1V8_ARC_VA_INTERNAL
ARC_AGND
PP1V2_ARC_VD_FILT
ARC_AGND
ARC_FLY_CAP2_NEG
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT
NFC_TO_ARC_RESET_L
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
ARC_FILT
SOLENOID_TO_ARC_VSENSE_POSSOLENOID_TO_ARC_VSENSE_NEG
ARC_TO_SOLENOID_OUT_NEGARC_TO_SOLENOID_OUT_POS
PP_ARC_VBOOST
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
SPKAMP_BOT_ARC_TO_AOP_INT_L
PMU_MASK_NFC_TO_ARC_TRIG
SPKAMP_TO_OTHERS_SYNC
ARC_AGND
PP1V8_ARC_VA_INTERNAL
ARC: AMPSYNC_DATE=04/05/2017
CER-X5R
10%
ROOM=ARC01005
0.22UF6.3V
SM
OMIT
ROOM=ARC
200K
MF01005
1/32W1%
55
57 5
55
57 5
1/32W1%
MF01005
61.9K
200K1%1/32WMF01005
MF
1%1/32W
61.9K
01005
ROOM=ARCCRITICAL
WLCSPCS35L27
20%
CER-X5R16V
1UF
ROOM=ARC0201
20%
ROOM=ARC
1UF
0201X6S-CERM6.3V
20%
CER-X5R
ROOM=ARC
6.3V
0402-0.1MM
18UF
54
54
41 40
50 42 41 40 13 5
42 41 40 13
50 40 13
50 42 41 40 13
42 41 5
56 41 5
CER-X5R
10%
01005ROOM=ARC
0.22UF6.3V
10%
X5R-CERM16V
01005ROOM=ARC
2200PF25V
01005
5%
COG
220PF
ROOM=ARC0402-0.1MM
10%4.2UF
X5R-CERM16V
ROOM=ARC
4.2UF10%16VX5R-CERM0402-0.1MM
ROOM=ARCROOM=ARC
10%4.2UF
0402-0.1MMX5R-CERM16V
CER-X5R
10%
01005ROOM=ARC
0.22UF6.3V
20%
CER-X5R
ROOM=ARC
6.3V
0402-0.1MM
18UF20%
CER-X5R
ROOM=ARC
6.3V
0402-0.1MM
18UF
20%
CER-X5R
ROOM=ARC
6.3V
18UF
0402-0.1MM
20%
CER-X5R
ROOM=ARC
6.3V
18UF
0402-0.1MM
CER-X5R
10%
ROOM=ARC
0.22UF
01005
6.3V
59 47 45 44 42 41 36 33 29 26 24 22 17
43
43
43
50
50
50
50
43
43
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
IN
IN
IN
IN
NC
MCLKSCLK
VSWIREVASP
FILT+
CF2+
CF1-
VA
CF2+
VSNS+VSNS-
CF2-
VBSTVBST
CF2-
CF2+
CF1-
VPB
CF1+CF1+
VPVD_FILTVL
GNDA GNDB GNDD GNDP
SWIRE_SD2
PDM2_DATA
SCLSDA
FSYNCSDOUT
SDIN
INT*SYNC
RESET*
AD1AD0/GPI
VD_FILT_SELOUT-OUT+
VSPKVSPK
PDM2_CLK
PDM1_DATA/SWIRE_SD1PDM1_CLK/SWIRE_CLK
IN
BI
IN
IN
IN
OUT
IN
OUT
OUT
VIETMOBILE.VN
Display Control Signalsrdar: #29872369
Once normal panel is available switch to 1.1V
1.2V LDO is for LGC test chip
Display MIPI
Here for syncccing purposes
Display 1V0 LDO for D33 second display vendor
Plug: 516S00211
Display Flex Connector<-- This one on MLBRcpt: 516S00210
Display Power
Display MIPI
44 OF 60
VOLTAGE=1.1V
PP1V0_DISPLAY_DVDD22
PP3V0_DISPLAY22
7.0.0
57 OF 85
051-02545
21
FL5782
2
1C5705
21
R5705
2
1 C5706
A2A1
B2
B1
U57012 1
FL5781
2
1C5721
2
1 C5786
2
1R5720
2
1 C2910
2
1 C2914
2
1R5700
21
R5704
21
R5702
4
32
1
L5740
4
32
1
L5730
4
32
1
L5720
4
32
1
L5710
4
32
1
L5700
21
XW5785
21
XW5784
21
FL5783
2
1 C5785
2
1 C5702
2
1 C57032 1
FL5703
2
1 C5704
2
1 C5784
2
1 C5783
2
1 C5782
2 1
FL5780
2
1 C5781
2 1
FL5700
2
1 C5701
2
1 C5700
21
R5701
3837
3635
34333231302928272625242322212019181716151413121110987654321
J5700
PP1V1_DISPLAY_VDD
90_MIPI_AP_TO_DISPLAY_CLK_N
90_MIPI_AP_TO_DISPLAY_DATA3_N
PMU_TO_DISPLAY_PANICB
PMU_TO_DISPLAY_RESET_L
PMU_TO_DISPLAY_PANICB_CONN
PP1V0_DISPLAY_VDD_CONNPP1V0_DISPLAY_DVDD
DISPLAY_TO_PMU_AMUX_CONN
PP1V0_DISPLAY_DVDD
MAKE_BASE=TRUE
PP1V26_S2
PMU_TO_DISPLAY_LDO_EN
DISPLAY_TO_AP_PANEL_ID
90_MIPI_AP_TO_DISPLAY_DATA0_P
DISPLAY_TO_AP_BSYNC_WATCHDOG_CONNDISPLAY_TO_AP_BSYNC_WATCHDOG 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P
MAKE_BASE=TRUE
PP3V0_DISPLAY
90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P
PP3V0_DISPLAY
PP1V8_IO
PP_VDD_MAIN PP_VDD_MAIN_DISPLAY_CONN
PP3V0_DISPLAY_VCI_CONN
PP1V8_DISPLAY_DVDD_CONN
NC_SPI_DISPLAY_FLASH_TO_AP_MISO
90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N
DISPLAY_TO_PMU_AMUX
90_MIPI_AP_TO_DISPLAY_DATA1_N
PP_VDD_MAIN_DISPLAY_CONN
PP3V0_DISPLAY_VCI_CONN
PP1V0_DISPLAY_VDD_CONNNC_SPI_AP_TO_DISPLAY_FLASH_SCLK
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P
90_MIPI_AP_TO_DISPLAY_CLK_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA2_N
90_MIPI_AP_TO_DISPLAY_DATA2_P
90_MIPI_AP_TO_DISPLAY_DATA1_P
90_MIPI_AP_TO_DISPLAY_DATA3_P
PP1V1_DISPLAY_VDD_CONN
DISPLAY_TO_PMU_AMUX_CONNPP1V8_DISPLAY_DVDD_CONN
90_MIPI_AP_TO_DISPLAY_CLK_P
DISPLAY_TO_AP_PANEL_ID_R
PP1V1_DISPLAY_VDD_CONN
90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N
DISPLAY_TO_AP_PANEL_ID_R
PP_VDD_MAIN_DISPLAY_CONN
ISP_TO_DISPLAY_FLASH_INT_CONN
90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P
PMU_TO_DISPLAY_RESET_CONN_L
PMU_TO_DISPLAY_PANICB_CONN
NC_PP_VPPNC_SPI_AP_TO_DISPLAY_FLASH_MOSI
NC_SPI_DISPLAY_FLASH_CS_L
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N
90_MIPI_AP_TO_DISPLAY_CLK_CONN_P90_MIPI_AP_TO_DISPLAY_CLK_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N
ISP_TO_DISPLAY_FLASH_INT_CONNISP_TO_DISPLAY_FLASH_INT
90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA0_N
DISPLAY_TO_AP_BSYNC_WATCHDOG_CONN
PMU_TO_DISPLAY_RESET_CONN_L
90_MIPI_AP_TO_DISPLAY_CLK_CONN_P
SYNC_DATE=10/13/2016SYNC_MASTER=test_mlb
CG: B2B Display
0201ROOM=B2B_DISPLAY
FERR-33OHM-25%-1.5A
01005
5%220PF
COG25V
ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY
01005
FERR-150OHM-25%-200MA
ROOM=B2B_DISPLAY
25V5%220PF
COG01005
5%
COG25V
220PF
ROOM=B2B_DISPLAY01005
MF1/32W5%
01005
10
ROOM=B2B_DISPLAY
F-ST-SMROOM=B2B_DISPLAY
BM28P0.6-34DS/2-0.35V
1/20W5%
0
MF0201
6.3V
0201ROOM=B2B_DISPLAY
X5R-CERM
20%2.2UF
ROOM=B2B_DISPLAY
1/32WMF
5%
1.00K
01005
COG25V5%220PF
ROOM=B2B_DISPLAY01005
SCY99224-1.15V
ROOM=B2B_DISPLAY
WLCSPCRITICAL
ROOM=B2B_DISPLAY
0201
FERR-33OHM-25%-1.5A
6.3VX5R
01005ROOM=B2B_DISPLAY
20%0.47UF
01005
220PF
ROOM=B2B_DISPLAY
25VCOG
5%
100K
ROOM=B2B_DISPLAY
5%1/32W
MF01005
NOSTUFF
2.2UF
ROOM=PMU
6.3VX5R-CERM0201
20%
X5R-CERM
2.2UF6.3V20%
ROOM=PMU0201
100K5%
1/32WMF
01005NOSTUFF
0%
0.00
MF1/32W
01005ROOM=B2B_DISPLAY
0.00
1/32W
ROOM=B2B_DISPLAY
0%
MF01005
ROOM=B2B_DISPLAY
GND_VOID
TAM0403S-SM35OHM-7GHZ-0.05MA-3OHM
TAM0403S-SM
ROOM=B2B_DISPLAY
GND_VOID
35OHM-7GHZ-0.05MA-3OHM
GND_VOID
ROOM=B2B_DISPLAY
35OHM-7GHZ-0.05MA-3OHMTAM0403S-SM
ROOM=B2B_DISPLAY
GND_VOID
35OHM-7GHZ-0.05MA-3OHMTAM0403S-SM
35OHM-7GHZ-0.05MA-3OHM
GND_VOID
ROOM=B2B_DISPLAY
TAM0403S-SM
9
9
SHORT-0201
ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY
SHORT-0201
01005ROOM=B2B_DISPLAY
FERR-70OHM-25%-0.300A
01005
5%
COG25V
220PF
ROOM=B2B_DISPLAY
9
ROOM=B2B_DISPLAY
NP0-C0G-CERM
56PF5%25V
01005
23
56PF25V5%
01005ROOM=B2B_DISPLAY
NP0-C0G-CERM
01005
FERR-150OHM-25%-200MA
ROOM=B2B_DISPLAY
9
ROOM=B2B_DISPLAY
220PF5%COG25V
01005
55
55
9
9
9
9
9
9
9
9
01005
25VCOG
5%220PF
ROOM=B2B_DISPLAY
220PF25V5%
ROOM=B2B_DISPLAY01005COG
01005
220PF
COG25V5%
ROOM=B2B_DISPLAY
44
44 44
44
44
29 22 20 17
55
55
44 44
44
44
44
44
53 52 37 36 34 32 31 30 29 20 19 17 6
59 47 45 43 42 41 36 33 29 26 24 22 17 44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
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1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SIG
PWR
PWR
IN OUT
GND
EN
NC
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
VIETMOBILE.VN
VDD_MAIN OV CUT-OFF CIRCUIT
Place near Hydra
45 OF 60
VOLTAGE=4.3V
7.0.0
59 OF 85
051-02545
A1
B2
A2
B1
U5900
21
XW5900PP_HYDRA_ACC1PP_VDD_MAIN
PMU_TO_IKTARA_RESET_L
PP_HYDRA_ACC1_OV_COMP
CDS_LIB=apple
I/O: Overvoltage Cut-Off Circuit
ALT_PARTS353S01398353S01375 ON SEMIU5900
BGA
CRITICAL
ROOM=OV_COMP
TPS3720-S
ROOM=SOC
NO_XNET_CONNECTION
SHORT-20L-0.05MM-SM
OMIT
50 49 59 47 44
43 42 41 36 33 29 26 24 22 17
58 23
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
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1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
VDD
OUTB
OUTA
GND
VIETMOBILE.VN
Input filters live hereto support page synccing
LDCM
AIN8
R6130 Value Quartered due to: 33165127
AIN6
PDM attenuation
DC Bias
Codec
60 OF 85
46 OF 60
051-02545
7.0.0
2
1 R6060
21
C6012
21
C6013
21
R6021
21
R6020
21
C6011
21
C6010
2
1 R6033
21
C6030
21
C6021
21
R6030
2
1R6031
2
1C6036
21
R60342
1 R6032
21
C6032
21
R6035
2
1 C6031
21
C6022
C2A2
C3A3B3
B2
U6020
2
1 C6020
C2A2
C1A1B1
B2
U6020
X5R01005
ROOM=CODEC
AOP_TO_HALOGEN_AFE_EN
HALOGEN_TIA_IOUT_C
ROOM=HALOGEN
ROOM=HALOGEN
HALOGEN_VSTIM_IN
5%100PF
01005NP0-C0G16V
ROOM=HALOGEN
01005
187K
1%
MF1/32W
16VCER-X7R01005
10%
330PF
ROOM=HALOGEN01005MF1/32W1%22.1K
01005
1/32W1%
MF
42.2K
X5R-CERM01005
6.3V20%
0.1UF
ROOM=HALOGEN01005
MF1/32W
1%499
1%1/32WMF
ROOM=HALOGEN01005
2.0K39
10UF
20%
0201
2.2UF
CER-X5R6.3V
ROOM=HALOGEN22.1K1%1/32WMF01005
ROOM=HALOGEN
MF01005
1%1/32W
ROOM=HALOGEN
MF1/32W1%
01005
CRITICAL
SCY9920175WLCSP
ROOM=HALOGEN
X5R-CERM6.3V0.1UF20%
01005ROOM=HALOGEN
SCY9920175WLCSP
01005NP0-C0G16V
+/-0.1PF
5PF
I/O: LDCMSYNC_MASTER=test_mlb SYNC_DATE=06/06/2017
AOP_TO_HALOGEN_AFE_EN
CODEC_TO_HALOGEN_AMP_PDM_OUT HALOGEN_AMP_ATN
PP_VDD_BOOST
HALOGEN_VSTIM_C
HALOGEN_VSTIM_FB HALOGEN_VSTIM_C
PP_VDD_BOOST
HALOGEN_TIA_IN
ROOM=HALOGEN
ROOM=HALOGEN
HALOGEN_VSTIM_DECOUPLED
ROOM=HALOGEN
AOP_TO_HALOGEN_AFE_EN
ROOM=HALOGEN0402-0.1MMCERM-X5R
6.3V20%
ROOM=HALOGEN
HALOGEN_VSTIM
HALOGEN_TIA_IOUT0.01UF
X5R6.3V10%
ROOM=CODEC01005
10%6.3V
0.01UFTIA_NEG_C
ROOM=CODEC
0.01UF
01005X5R6.3V10%
ROOM=CODEC
0.01UF
01005X5R6.3V10%
STIM_NEG_C
200K
4.99K
3.01M1%1/32WTK01005ROOM=CODEC
ROOM=HALOGEN
HYDRA_TO_PMU_USB_BRICK_ID_TIA
40
23 49
46 56
46 56
17 22 24 29 36 40 46
46
46 56
46
17 22 24 29 36 46 47 59
39
39
47 59
39
39
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
-+
-+IN
VIETMOBILE.VN
IND Alternate
Gecko
GECKO Reset Pull Down
I2C ADDRESS: 0X52
47 OF 60
I2C0_AP_SDAI2C0_AP_SCL
7.0.0
61 OF 85
051-02545
C2B3
C4C3
D4D3A3
A2B2
C1
B4
D1A1
A4
B1
D2
U6150
21
L6150
2
1 R6100
2
1 C61522
1 C61512
1 C6150
2
1C61622
1C6161
AOP_TO_GECKO_RESET_L
GECKO_TO_AOP_IRQ_L
AOP_TO_GECKO_RESET_L
ACORN_GECKO_ANSEL_TO_PMU_ADC GECKO_LX
PP_ACC_VAR
PP_VDD_BOOSTPP_VDD_MAIN
IND,PWR,0.47UH,20%,2.8A,CYL6150ALT_PARTS152S00854 152S00853
IND,PWR,0.47UH,20%,2.7A,MurataALT_PARTS L6150152S00855 152S00853
SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
I/O: Gecko
25V
ROOM=GECKO
5%COG01005
220PF
20%
0201CERM-X5R
ROOM=GECKO
6.3V
4UF
CERM-X5R0201
4UF6.3V20%
ROOM=GECKO
CSP
CRITICALROOM=GECKO
FAN53740UCA1X
60 30 23 17
0.47UH-20%-2.7A-0.071OHM
MCFE1210-SM
56 47
56 5
52
52
100K5%1/32WMF01005
ROOM=GECKO
6.3V
ROOM=GECKO
0.1UF
01005X5R-CERM
20%
CER-X5R0402-0.1MM
18UF
ROOM=GECKO
20%6.3V
56 47
49
59 46 40 36 29 24 22 17 59 45 44
43 42 41 36 33 29 26 24 22 17
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
AGND
NC
IRQ*
RESET*
PGND
SDASCL
AMUX
VDD_
BUCK
LX
VOUT
VDD_
BYPA
SS
VDD_
LDO
OUT
IN
OUT
BI
IN
VIETMOBILE.VN
USB-PD
48 OF 60
I2C0_SMC_SDAI2C0_SMC_SCL
7.0.0
62 OF 85
051-02545
B1
D4 C1E1E3 C4 E4A1
E2D1
B3
A2A3
D3
D2
C3
C2
B2
A4B4
U6200
2
1 C6210
2
1 R6211
2
1 R6210
2
1 C6200
2
1 C62902
1 C6291
2
1 C6292
PP5V0_USB_RVP_R
PMU_TO_CCG2_RESET_L
CCG2_BI_HYDRA_CC
AP_TO_CCG2_SWCLKAP_BI_CCG2_SWDIO
CCG2_TO_SMC_INT_L
PP3V0_S2PP1V8_S2
PP1V8_VCCD_CCG2
PP_VAR_USB_RVP
I/O: USB PDSYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
CSP
CRITICAL
CG8740AAT
ROOM=USB_PD
11 5
54
11 5
54
20%6.3VX5R-CERM
22NF
ROOM=USB_PD01005
50K1%1/32WMF01005
ROOM=USB_PD
499K1%1/20WMF201
ROOM=USB_PD
55
49
25V5%220PF
COG
ROOM=USB_PD01005
11 5
20%1.0UF
0201-1X5R-CERM10V
ROOM=USB_PD
20%
X5R-CERM10V
1.0UF
ROOM=USB_PD0201-1
20%1.0UF
0201-1X5R-CERM10V
ROOM=USB_PD
58 49 38 22
59 54 50 49 42 41 40 38 25 20 17
49 26
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NCNC
VSS
XRES
VDDI
O
VDDD
VCCD
VCO
NN2
VCO
NN1
GPIO_C3GPIO_D3GPIO_C2GPIO_D2GPIO_B2
I2C_0_SCLI2C_0_SDA
SWD_IOSWD_CLK
VSS
RD1
CC2CC1
IN
IN
BI
BI
NC
IN
NCBIOUT
NC
NC
VIETMOBILE.VN
No stuffed and 0 ohmed for P1
From Yangtze
R was previosuly a 6.34K
I2C Address: 0011010X
Hydra
49 OF 60
I2C1_SMC_SCLI2C1_SMC_SDA
GNDMAKE_BASE=TRUE
7.0.0
63 OF 85
051-02545
21
R6300
2
1 C6300
H5H4
D3D4
B3B4
B1A1
F2E2
D1C1
E4
G5G4
H3
G6
F1E1
F7
F6
H2
G2
H7H6H1G7E3 F4
A3
C3
G1
A4
C4
C2D2
G3
A2B2
F5
F3
E6D6C6B6A6
E7D7C7B7A7E5D5C5B5A5
U6300
2
1 C63122
1 C6311
21
L6301
21
L6300
2
1 C63912
1 C6390
2
1 C6330
2
1 C6395
90_USB_AP_DATA_N
HYDRA_TO_YANGTZE_VBUS1_VALID_L
90_USB_DBG_DATA_P
PP_VAR_USB_RVP
PP_HYDRA_ACC2
90_HYDRA_DP2_CONN_N
HYDRA_CON_DETECT_L
HYDRA_BYPASS
90_USB_AP_DATA_P
PP_ACC_VAR
90_MIKEYBUS_DATA_P
PP3V0_S2
HYDRA_TO_NUB_INT
UART_AP_TO_ACCESSORY_TXDUART_ACCESSORY_TO_AP_RXD
UART_AP_DEBUG_TXDUART_AP_DEBUG_RXD
PP1V8_S2
PP_HYDRA_ACC1
SWD_DOCK_TO_AP_SWCLK
90_HYDRA_DP1_CONN_N
HYDRA_TO_PMU_USB_BRICK_ID_TIA_R
90_USB_DBG_DATA_N
HYDRA_TO_PMU_USB_BRICK_ID_TIA
HYDRA_TO_PMU_HOST_RESETPMU_TO_AP_HYDRA_ACTIVE_READY
90_HYDRA_DP1_CONN_P
90_HYDRA_DP2_CONN_P
90_MIKEYBUS_DATA_N
CCG2_BI_HYDRA_CC
HYDRA_TO_NUB_DOCK_CONNECT
90_USB_AP_DATA_L_N90_USB_AP_DATA_L_P
SWD_DOCK_BI_AP_SWDIO
HYDRA_TO_AP_FORCE_DFU
I/O: HydraSYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
20%1.0UF
0201-1X5R-CERM10V
ROOM=HYDRA
ROOM=HYDRA01005X5R
0.01UF10%6.3V
0.00
0%
MFROOM=HYDRA
1/32W
01005
01005ROOM=HYDRANOSTUFF
0.01UF10%6.3VX5R
CBTL1612A1WLCSP
ROOM=HYDRA
CRITICAL20%
0201CER-X5R
0.47UF25V
ROOM=HYDRA
48
39
39
13
20%
0201CER-X5R25V
ROOM=HYDRA
0.47UF
57 12
54
23 7 5
13
23
26 5
50
54
50
50
50
50
7
7
12
12
12
12 5
7
7
7
7
46 23
0201
15NH-250MA
ROOM=HYDRA
GND_VOID
0201
15NH-250MA
GND_VOID
ROOM=HYDRA
X5R-CERM
20%6.3V
01005
0.1UF
ROOM=HYDRA
20%
X5R-CERM
1.0UF
0201-1
10V
ROOM=HYDRA
48 26
50
47 58 48 38 22
59 54 50 48 42 41 40 38 25 20 17
50 45
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VDD1V8ACC_PWR
DVSS1
VDD3V0
UART1_TXUART1_RX
ACC2ACC2
POW_GATE_EN*
CC0
DIG_DPDIG_DN
USB1_DP
BRICK_ID
USB1_DN
USB0_DNUSB0_DP
UART0_RXUART0_TX
UART2_TXUART2_RX
JTAG_CLKJTAG_DIO
EXT_SW_EN
FORCE_DFU
DOCK_CONNECT
CC1
DVSS
P_INACC1
ACC1ACC1
ACC1ACC1
ACC2
ACC2ACC2
DN1DP1
DN2DP2
CON_DET_L
SWITCH_ENHOST_RESET
SCLSDA
INTBYPASS
BI
NC
BI
BI
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
BI
BI
BI
BI
BI
BI
BI
IN
OUT
IN
OUT
OUT
BI
BI
BI
OUT
NC
VIETMOBILE.VN
ARC
LOWER MIC1
POTASSIUM
PHALANX
MIC4
Hydra
SOUTH SPEAKER
DOCK FLEX CONNECTOR<-- This one on MLBRcpt: 516S00423
Plug: 516S00424
50 OF 60
I2C0_AP_SCL50 52
I2C1_AOP_SCL50 54
I2C0_AP_SDA50 52
I2C0_AP_SCL
I2C0_AP_SDA
I2C1_AOP_SCLCKPLUS_WAIVE=I2C_PULLUP
I2C1_AOP_SDACKPLUS_WAIVE=I2C_PULLUP
7.0.0
64 OF 85
051-02545
2
1 R6440
2
1 C6466
2
1 C6465
2
1 C6432
21
R6432
4847
4645
4443424140393837363534333231302928272625242322212019181716151413121110987654321
J6400
2
1 C6421
2
1 C6413
2
1 C6411
21
R6421
21
R6420
21
R6419
2
1 C643321
R6433
2
1 C6431
2
1 C64302 1
FL6430
2
1C64952
1C64962
1C6497
2
1 C6474
2
1 C6475
21
R6491
21
R6490
21
R6482
21
R6480
2
1 C6482
2
1 C6480
2
1 C64732
1 C6472
2
1 C6487
2
1 C6486
2
1 C6420
2
1 C6419
2
1 C6418
2
1 C6416
2
1C6492
2
1 C6483
2
1 C6485
2
1C64702
1C6471
2
1C64942
1C64932
1C64912
1C6490
2
1 C64002 1
FL6400
2
1 C6450
2
1 C6452
2 1
FL6450
2 1
FL6452
2 1
FL6454
2
1 C6454
2
1 C6460
2
1 C6462
2 1
FL6460
2 1
FL6462
2 1
FL6464
2
1 C6464
2
1 C6410
21
FL6411
2 1
R6410
21
FL6413
LOWERMIC1_TO_CODEC_AIN1_CONN_N
LOWERMIC1_TO_CODEC_AIN1_CONN_P
LOWERMIC1_TO_CODEC_AIN1_N
PP_CODEC_TO_LOWERMIC1_BIAS_CONNARC_TO_SOLENOID_OUT_NEG
SPKRAMP_BOT_TO_COIL_OUT_POS
SPKRAMP_BOT_TO_COIL_OUT_NEG
ARC_TO_SOLENOID_OUT_POS
COIL_TO_SPKRAMP_BOT_VSENSE_NEG COIL_TO_SPKRAMP_BOT_VSENSE_NEG_CONN
COIL_TO_SPKRAMP_BOT_VSENSE_POS COIL_TO_SPKRAMP_BOT_VSENSE_POS_CONN
LOWERMIC4_TO_CODEC_AIN4_CONN_N
PP_CODEC_TO_LOWERMIC4_BIAS_CONN
LOWERMIC4_TO_CODEC_AIN4_CONN_P
PP_CODEC_TO_LOWERMIC4_BIAS
LOWERMIC4_TO_CODEC_AIN4_N
LOWERMIC4_TO_CODEC_AIN4_P
HYDRA_CON_DETECT_CONN_L
PP_HYDRA_ACC1_CONN
PP_HYDRA_ACC2_CONN
HYDRA_CON_DETECT_L
PMU_TO_PHALANX1
PMU_TO_PHALANX2
PP_CODEC_TO_LOWERMIC1_BIAS
LOWERMIC1_TO_CODEC_AIN1_P
PP1V8_IMU_S2 PP1V8_IMU_POTASSIUM_S2_CONN
POTASSIUM_TO_AOP_INT_CONN
SPKRAMP_BOT_TO_COIL_OUT_NEG
ARC_TO_SOLENOID_OUT_POS
PP_HYDRA_ACC2_CONNARC_TO_SOLENOID_OUT_NEG
PP_VBUS1_E75
PP1V8_IMU_POTASSIUM_S2_CONNI2C1_AOP_BI_POTASSIUM_SDA_CONN
PMU_TO_PHALANX2LOWERMIC4_TO_CODEC_AIN4_CONN_P
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONNHYDRA_CON_DETECT_CONN_L
PP_CODEC_TO_LOWERMIC1_BIAS_CONN
SOLENOID_TO_ARC_VSENSE_POS_CONN
90_HYDRA_DP1_CONN_N90_HYDRA_DP1_CONN_P
90_HYDRA_DP2_CONN_P
LOWERMIC1_TO_CODEC_BIAS_FILT_RET
MIKEYBUS_REFERENCELOWERMIC1_TO_CODEC_AIN1_CONN_P
PP_CODEC_TO_LOWERMIC4_BIAS_CONNLOWERMIC4_TO_CODEC_AIN4_CONN_N
COIL_TO_SPKRAMP_BOT_VSENSE_NEG_CONN
90_HYDRA_DP2_CONN_N
POTASSIUM_TO_AOP_INT_CONN
PMU_TO_PHALANX1
LOWERMIC1_TO_CODEC_AIN1_CONN_N
PP1V8_S2_SAKONNET_CONN
PP_HYDRA_ACC1_CONN
SOLENOID_TO_ARC_VSENSE_NEG_CONN
SOLENOID_TO_ARC_VSENSE_POS_CONN
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN
PP1V8_S2
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
SOLENOID_TO_ARC_VSENSE_POS
SOLENOID_TO_ARC_VSENSE_NEG_CONN
PP1V8_S2_SAKONNET_CONN
SPKRAMP_BOT_TO_COIL_OUT_POS
COIL_TO_SPKRAMP_BOT_VSENSE_POS_CONN
LOWERMIC4_TO_CODEC_BIAS_FILT_RET
PP_HYDRA_ACC1
PP_HYDRA_ACC2
I2C1_AOP_BI_POTASSIUM_SDA_CONN
POTASSIUM_TO_AOP_INT
PP1V8_IMU_S2
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN
SOLENOID_TO_ARC_VSENSE_NEG
I/O: B2B DockSYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
5%
ROOM=B2B_DOCK
220PF
01005COG25V
ROOM=B2B_DOCK
220PF25V5%
COG01005
0.1UF10%
X5R25V
ROOM=B2B_DOCK
0201X5R25V10%
0201
0.1UF
ROOM=B2B_DOCK
5%
ROOM=B2B_DOCK
25VCOG
220PF
01005
FERR-150OHM-25%-200MA
ROOM=B2B_DOCK01005
NP0-C0G-CERM25V
01005
5%56PF
ROOM=B2B_DOCK
01005
5%
ROOM=B2B_DOCK
56PF25VNP0-C0G-CERM
ROOM=B2B_DOCK
FERR-150OHM-25%-200MA
01005
FERR-150OHM-25%-200MA
01005ROOM=B2B_DOCK
FERR-150OHM-25%-200MA
ROOM=B2B_DOCK01005
01005
5%25V
220PF
ROOM=B2B_DOCK
COG
01005
5%
ROOM=B2B_DOCK
56PF25VNP0-C0G-CERM
NP0-C0G-CERM
5%56PF
ROOM=B2B_DOCK
25V
01005
FERR-150OHM-25%-200MA
01005ROOM=B2B_DOCK
FERR-150OHM-25%-200MA
ROOM=B2B_DOCK01005
01005ROOM=B2B_DOCK
FERR-150OHM-25%-200MA
5%
ROOM=B2B_DOCK
220PF
COG25V
01005
01005
10-OHM-1.1A
ROOM=B2B_DOCK
10K5%1/32W
01005MF
01005
330PF10%
CER-X7R
ROOM=B2B_DOCK
16V
ROOM=B2B_DOCK
16V10%330PF
CER-X7R01005
5%56PF25V
ROOM=B2B_DOCK01005NP0-C0G-CERM
1/32W0%
MF
0.00
ROOM=B2B_PEARL
01005
F-ST-SM
ROOM=B2B_DOCK
BM28PS-44DS-2-0.35V
NP0-C0G-CERM
5%25V
ROOM=B2B_DOCK01005
56PF
01005ROOM=B2B_DOCK
16VNP0-C0G
5%100PF
100PF
01005
16VNP0-C0G
5%
ROOM=B2B_DOCK
ROOM=B2B_DOCK
1%
MF1/32W
01005
49.9
MF
1%1/32W
49.9
01005ROOM=B2B_DOCK
1%
MF01005
1/32W
49.9
ROOM=B2B_DOCK
01005ROOM=B2B_BUTTON
220PF25V5%
COG
0%
MF
0.00
ROOM=B2B_BUTTON01005
1/32W
56
54
54 50
ROOM=B2B_DOCK
NP0-C0G-CERM
56PF5%25V
01005
220PF
COG01005ROOM=B2B_DOCK
25V5%
FERR-150OHM-25%-200MA
01005ROOM=B2B_DOCK
ROOM=B2B_DOCK
X5R
10%25V
0.1UF
0201X5R25V
0.1UF
ROOM=B2B_DOCK
10%
0201
10%25V
0.1UF
X5R
ROOM=B2B_DOCK
0201
5%
COG
220PF
01005ROOM=B2B_DOCK
25V
5%220PF25VCOG
ROOM=B2B_DOCK01005
01005MF
100
1/32W5%
ROOM=B2B_DOCK
ROOM=B2B_DOCK01005
100
MF1/32W5%
5%
ROOM=B2B_DOCK
MF
100
1/32W
01005
5%
ROOM=B2B_DOCK
MF1/32W
100
01005
220PF5%25V
ROOM=B2B_DOCK
COG01005
ROOM=B2B_DOCK
5%25VCOG
220PF
01005
25V10%1000PF
X5R0201
25V10%1000PF
X5R0201
ROOM=B2B_DOCK
10%1000PF25VX5R0201
X5R
10%25V
ROOM=B2B_DOCK
1000PF
0201
01005
100
ROOM=B2B_DOCK
MF1/32W5%
39
39
39
52 50
52 50
49
39
55 50
55 50
41
41
50 41
50 41
5%25VNP0-C0G-CERM
ROOM=B2B_DOCK01005
56PF
5%25VNP0-C0G-CERM01005
ROOM=B2B_DOCK
56PF
43 40 13
43 42 41 40 13 5
43 42 41 40 13
5%56PF
ROOM=B2B_DOCK
25VNP0-C0G-CERM01005
5%
NP0-C0G-CERM01005ROOM=B2B_DOCK
56PF25V
ROOM=B2B_DOCK01005
16V
27PF
NP0-C0G
5%
0.1UF
X5R25V10%
ROOM=B2B_DOCK
0201
ROOM=B2B_DOCK01005
220PF5%25VCOG
5%220PF25VCOG
ROOM=B2B_DOCK01005
5%220PF
COG25V
ROOM=B2B_DOCK01005
5%
ROOM=B2B_DOCK
220PF25VCOG
01005
0201
22-OHM-25%-1800MA
ROOM=B2B_DOCK
50
50
50
50 43
50 43
50
50
50
50
50
40
50
50
50
40
54 50 28 27 20 50
50
50 41
50 43
50 50 43
58 26
50
50
55 50
50
50
50
50
50
50
50
49
49
49
40
39
50
50
50
50
49
50
55 50
50
50
50
50
50
50
50
59 54 49 48 42 41 40 38 25 20 17
43
50
50
50 41
50
40
49 45
49
50
54 50 28 27 20
50
43
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
BI
IN
OUT
OUT
OUT
IN
BI
OUT
OUT
IN
BI
OUT
OUT
IN
IN
BI
IN
IN
VIETMOBILE.VN
Bot Board Interposer APN:998-12514 Top Board Interposer APN:998-12513 <--- STUFFED
51 OF 60
GND57
GND57
GND57
BB_TO_AP_COEX57
AP_TO_BB_COEX57
GND57
GND57
GND57
GND57
GND57
GND57
PP1V8_S257
PP1V8_S257
GND57
HYDRA_TO_AP_FORCE_DFU57
GND57
GNSS_TO_AP_LOW_PWR_IND57
GND57
AP_TO_WLAN_TIME_SYNC57
GND57
AP_TO_RACER_RESET_L57
GND57
PCIE_AP_TO_WLAN_PERST_L57
GND57
UART_AP_TO_GNSS_RTS_L57
GND57
UART_GNSS_TO_AP_CTS_L57
GND57
SWD_AOP_BI_BB_SWDIO57
GND57
AP_TO_BB_RESET_L57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
NFC_TO_ARC_TRIG57
GND57
NFC_TO_ARC_RESET_L57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND57
PP1V8_ALWAYS57
GND57
I2S_BB_TO_AP_LRCLK57
GND57
I2S_AP_TO_BB_DOUT57
GND57
I2S_BB_TO_AP_DIN57
GND57
I2S_BB_TO_AP_BCLK57
GND57
AP_TO_TOUCH_SCAN_CLK57
GND57
HALL_CASE_TO_AOP_NORTH_L57
GND57
BB_TO_MANY_GSM_BURST_IND57
GND57
AP_TO_CAMPMU_RESET_L57
GND57
GND57
GND57
GND57
GND57
AP_TO_NFC_DEV_WAKE 57
PMU_TO_NFC_VDD_MAIN_EN 57
UART_AP_TO_NFC_TXD 57
GND 57
UART_NFC_TO_AP_RXD 57
AP_TO_GNSS_TIME_MARK 57
BOARD_ID2 57
AP_TO_BB_PEAK_POWER_INDICATOR 57
NC_INTERPOSER_109 57
AP_TO_BBPMU_RADIO_ON_L 57
PP_VDD_MAIN 57
PP_VDD_MAIN 57
PP_VDD_MAIN 57
90_PCIE_BB_TO_AP_RXD_N 57
GND 57
90_PCIE_AP_TO_BB_TXD_N 57
GND 57
90_PCIE_BB_TO_AP_RXD_P 57
GND 57
90_PCIE_AP_TO_BB_TXD_P 57
GND 57
90_PCIE_AP_TO_BB_REFCLK_N 57
90_PCIE_AP_TO_BB_REFCLK_P 57
UART_GNSS_TO_AP_RXD 57
UART_BB_TO_AOP_RXD 57
GND 57
UART_NFC_TO_AP_CTS_L 57
PCIE_AP_TO_BB_PERST_L 57
PMU_AMUX_BY 57
UART_AP_TO_NFC_RTS_L 57
PCIE_BB_BI_AP_CLKREQ_L 57
GND 57
PMU_AMUX_AY 57
BB_TO_AP_PEAK_POWER_INDICATOR 57
NC_INT_135 57
GND 57
PP_VDD_MAIN 57
PP_VDD_MAIN 57
GND 57
GND 57
PP_VDD_MAIN 57
GND 57
GND 57
GND 58
GND 58
GND 58
GND 58
GND 58
GND 58
GND 58
GND 58
PP_VDD_MAIN 58
GND 58
PP_VDD_MAIN 58
GND 58
PP_VDD_MAIN 58
PP_VDD_MAIN 58
GND 58
PMU_TO_NFC_EN 58
PMU_TO_BBPMU_RESET_L 58
GND 58
GND 58
PMU_TO_TOUCH_CLK32K 58
GND 58
PCIE_WLAN_BI_AP_CLKREQ_L 58
GND 58
GND 58
BB_TO_PMU_PCIE_HOST_WAKE_L 58
GND 58
WLAN_TO_PMU_HOST_WAKE 58
GND 58
GND 58
PMU_TO_WLAN_CLK32K 58
GND 58
GND 58
NFC_TO_AOP_HOST_WAKE 58
TOUCH_TO_MANY_FORCE_PWM 58
UART_AP_TO_BT_TXD 58
GND 58
GND 58
GND 58
GND 58
GND 58
GND 58
GND 58
GND 58
UART_AP_TO_BT_RTS_L 58
BB_TO_AP_RESET_DETECT_L 57
AP_TO_BB_COREDUMP_TRIG 57
GND 57
UART_AP_TO_GNSS_TXD 57
UART_AOP_TO_BB_TXD 57
IKTARA_TO_SMC_INT 60
GND 60
PMU_TO_IKTARA_EN_EXT_1V8 60
GND 60
GND 60
HALL_CASE_TO_AOP_SOUTH_L 60
GND 60
GND 60
RACER_TO_AOP_INT_L 60
ACORN_GECKO_ANSEL_TO_PMU_ADC 60
GND 60
GND 58
GND 58
GND 58
GND 58
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
AP_CANARY1 60
GND 60
GND 60
NC_INTERPOSER_311 60
GND 60
GND 60
NC_INTERPOSER_309 60
IKTARA_COIL1 60
IKTARA_COIL1 60
IKTARA_COIL1 60
IKTARA_COIL1 60
IKTARA_COIL2 60
IKTARA_COIL2 60
IKTARA_COIL2 60
I2C0_SMC_SCL 60
GND 60
I2C0_SMC_SDA 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND 60
GND58
GND58
AP_CANARY258
GND58
GND58
PP1V8_NFC_S258
PMU_TO_GNSS_EN58
PMU_TO_BT_REG_ON58
GND58
90_PCIE_AP_TO_WLAN_REFCLK_N58
90_PCIE_AP_TO_WLAN_REFCLK_P58
GND58
90_PCIE_AP_TO_WLAN_TXD_P58
GND58
90_PCIE_WLAN_TO_AP_RXD_P58
GND58
PP3V0_S258
PP1V8_TOUCH_RACER_S258
PMU_TO_WLAN_REG_ON58
RADIO_PA_NTC58
BT_TO_AP_TIME_SYNC58
UART_BT_TO_AP_RXD58
GND58
GND58
UART_BT_TO_AP_CTS_L58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
PP_VBUS1_E7558
GND58
PP_GPU_LVCC58
GND58
PP_CPU_PCORE_LVCC58
GND58
PP_BATT_VCC58
PP_BATT_VCC58
GND58
AP_TO_BT_DEVICE_WAKE58
AOP_TO_WLAN_CONTEXT_A58
UART_AOP_TO_RACER_TXD58
SWD_AOP_TO_MANY_SWCLK58
SPI_AP_TO_RACER_MOSI58
SPI_AP_TO_RACER_SCLK58
PP1V1_RACER_S258
PP1V1_RACER_S258
PP1V1_RACER_S258
AP_TO_RACER_REF_CLK58
GND58
AOP_TO_BBPMU_COEX58
PP_VBUS2_IKTARA58
PP_VBUS2_IKTARA58
PP_VBUS2_IKTARA58
PP_VBUS2_IKTARA58
GND58
AOP_TO_WLAN_CONTEXT_B58
GND58
UART_RACER_TO_AOP_RXD58
GND58
SPI_RACER_TO_AP_MISO58
GND58
SPI_AP_TO_RACER_CS_L58
GND58
PMU_TO_IKTARA_RESET_L58
GND58
SWD_AOP_BI_RACER_SWDIO58
GND58
I2C3_AP_SDA58
GND58
I2C3_AP_SCL58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
GND58
GND 60
GND58
PP1V8_TOUCH_RACER_S258
90_PCIE_WLAN_TO_AP_RXD_N58
IKTARA_COIL2 60
90_PCIE_AP_TO_WLAN_TXD_N58
PMU_TO_SYSTEM_COLD_RESET_L57
GND 57
AP_TO_NFC_FW_DWLD_REQ 57
7.0.0
65 OF 85
051-02545
358357356355354353352351350349348347346345344343342341340339338337336335334333332331330329328327326325324323322321320319318317316315314313312311310309308307306305304303302301300299298297296295294293292291290289288287286285284283282
281280279278277276275274273272271270269268267266265264263262261260259258257256255254253252251250249248247246245244243242241240239238237236235234233232231230229228227226225224223222221220219218217216215214213212211210209208207206205204203202201200199198197196195194193192191190189
J_INT_BOT
1881871861851841831821811801791781771761751741731721711701691681671661651641631621611601591581571561551541531521511501491481471461451441431421411401391381371361351341331321311301291281271261251241231221211201191181171161151141131121111101091081071061051041031021011009998979695
94939291908988878685848382818079787776757473727170696867666564636261605958575655545352515049484746454443424140393837363534333231302928272625242322212019181716151413121110
987654321
J_INT_BOT
INTERPOSER_PIN_90
SYNC_DATE=08/30/2017
B2B: Interposer Bot
INTE
RPOS
ER-M
LB-B
OT-V
3-D3
2
SMT-PAD
INTE
RPOS
ER-M
LB-B
OT-V
3-D3
2
SMT-PAD
57
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 2 OF 2
IO295IO296
IO293IO294
IO292IO291IO290
IO288IO289
IO287IO286IO285IO284
IO282IO283
IO321IO320
IO318IO319
IO315IO316IO317
IO313IO314
IO310IO311IO312
IO308IO309
IO305IO306IO307
IO304IO303IO302
IO300IO301
IO297
IO299IO298
IO346
IO343
IO345IO344
IO341IO342
IO338
IO340IO339
IO336IO337
IO334IO335
IO333IO332IO331
IO329IO330
IO328IO327IO326IO325
IO323IO324
IO322
IO356IO357IO358
IO354IO355
IO351IO352IO353
IO350IO349IO348IO347
IO189
IO192IO193IO194IO195IO196IO197IO198IO199IO200IO201IO202IO203IO204IO205IO206IO207IO208IO209IO210IO211IO212IO213IO214IO215IO216IO217IO218IO219IO220IO221IO222IO223IO224IO225IO226IO227IO228IO229IO230IO231IO232IO233IO234IO235IO236IO237IO238IO239IO240IO241IO242IO243IO244IO245IO246IO247IO248IO249IO250IO251IO252IO253IO254IO255IO256IO257IO258IO259IO260IO261IO262IO263IO264IO265IO266IO267IO268IO269IO270IO271IO272IO273IO274IO275IO276IO277IO278IO279IO280IO281
IO190IO191
SYM 1 OF 2
IO1IO2
IO94IO93IO92IO91IO90IO89IO88IO87IO86IO85IO84IO83IO82IO81IO80IO79IO78IO77IO76IO75IO74IO73IO72IO71IO70IO69IO68IO67IO66IO65IO64IO63IO62IO61IO60IO59IO58IO57IO56IO55IO54IO53IO52IO51IO50IO49IO48IO47IO46IO45IO44IO43IO42IO41IO40IO39IO38IO37IO36IO35IO34IO33IO32IO31IO30IO29IO28IO27IO26IO25IO24IO23IO22IO21IO20IO19IO18IO17IO16IO15IO14IO13IO12IO11IO10IO9IO8IO7IO6IO5IO4IO3
IO95IO96
IO98IO97
IO101IO100
IO99
IO103IO102
IO106IO105IO104
IO108IO107
IO110IO109
IO111
IO113IO112
IO114
IO116IO115
IO119IO118IO117
IO121IO120
IO124IO123IO122
IO126IO125
IO129IO128IO127
IO131IO130
IO134IO133IO132
IO136IO135
IO137
IO139IO138
IO142IO141IO140
IO144IO143
IO147IO146IO145
IO149IO148
IO152IO151IO150
IO154IO153
IO157IO156IO155
IO158IO159IO160
IO162IO161
IO165IO164IO163
IO166IO167
IO170IO169IO168
IO172IO171
IO175IO174IO173
IO177IO176
IO178
IO180IO179
IO183
IO185
IO188IO187IO186
IO184
IO181IO182
VIETMOBILE.VN
AP I2C3
AP I2C1
0x56
1 MHz
8-Bit Addr.
Top Speaker Amp
PP1V8_IO
Touch Flex
Bot MLB
Binary
AP I2C4
AP I2C1
Bus Name
100 kHz
8-Bit Addr.
-
Min Speed
1 MHz
Max Speed Location
Strobe Flex
Bus Voltage
Top MLB
Location
1 MHz
Min Speed
-
8-Bit Addr.
0x80, 0x81
Binary
1000 000X0x40
7-Bit Addr.DeviceBus Name
AP I2C2
Max SpeedBus Speed
MIC2
Device
Bus Name
AP I2C3 PP1V8_IO
Bus Voltage
400 kHz
Bus Speed Device
TOUCH EEPROM
ACORN
0x51
0x54, 0x55
-
Min Speed
-
Max Speed
1 MHz
1 MHz
Location
Location
Top MLB
Device
LYNX
400 kHz
Bus SpeedBus VoltageBus Name
AP I2C4
PP1V8_IO
Bus Voltage
PP1V8_IO
AP I2CBus Name
AP I2C0 PP1V8_IO
Bus Speed Device
GECKO
SAKONNET
BOOST
ARC EEPROM
7-Bit Addr.
0x75
0x08
0x52
0x50
1010 010X
0001 000X
Binary
1110 101X
1010 000X
0xEA, 0xEB
0x10, 0x11
0xA0, 0xA1
0xA4, 0xA5
8-Bit Addr.
-
-
-
-
Min Speed Max Speed
400 KHz
400 KHz
1 MHz
1 MHz
TOP MLB
TOP MLB
Location
Dock Flex
Dock Flex
400 kHz
Bus Voltage
Bus Speed
0xA8, 0xA9
7-Bit Addr.
1010 100X
0X2A
7-Bit Addr. Binary
0101 010X
1010 001X 0xA2, 0xA3
7-Bit Addr.
0X71
AP I2C2
Acorn and Touch EEPROM Live on Bottom Board
AP I2C0
52 OF 60
I2C4_AP_SCL
I2C2_AP_SCLI2C2_AP_SDA
I2C4_AP_SDA
I2C0_AP_SDAI2C0_AP_SCL
I2C1_AP_SDAI2C1_AP_SCL
I2C0_AP_SCLI2C0_AP_SDA
I2C0_AP_SDAI2C0_AP_SCL
7.0.0
66 OF 85
051-025452
1R6671
2
1R6670
2
1R6621
2
1R6620
2
1R6601
2
1R6600
2
1R6611
2
1R6610
2
1R6631
2
1R6630
PP1V8_IO
I2C3_AP_SCL MAKE_BASE=TRUEI2C3_AP_SDA MAKE_BASE=TRUE
I2C0_AP_SCL MAKE_BASE=TRUEI2C0_AP_SDA MAKE_BASE=TRUE
PP1V8_IO
I2C1_AP_SCL MAKE_BASE=TRUEI2C1_AP_SDA MAKE_BASE=TRUE
PP1V8_IO
I2C2_AP_SCL MAKE_BASE=TRUEI2C2_AP_SDA MAKE_BASE=TRUE
PP1V8_IO
I2C4_AP_SCL MAKE_BASE=TRUEI2C4_AP_SDA MAKE_BASE=TRUE
PP1V8_IO
SYSTEM: AP I2C
5%2.2K
01005
1/32WMF
ROOM=SOC
5%2.2K
01005
1/32WMF
ROOM=SOC
ROOM=SOC
MF1/32W
5%4.7K
0100501005
4.7K5%
1/32WMF
ROOM=SOC
ROOM=SOC01005
5%1/32W
MF
4.7K4.7K5%
1/32WMF
ROOM=SOC01005
47
24
24
11
11
42
42
35
35
50
50
47
5%2.2K
01005
1/32WMF
ROOM=SOC
5%2.2K
01005
1/32WMF
ROOM=SOC
2.2K5%
01005
1/32WMF
ROOM=SOC
2.2K5%
01005
1/32WMF
ROOM=SOC
53 52 44 37 36 34 32 31 30 29 20 19 17 6
58 11
58 11
11
11
53 52 44 37 36 34 32 31 30 29 20 19 17 6
11
11
53 52 44 37 36 34 32 31 30 29 20 19 17 6
11
11
53 52 44 37 36 34 32 31 30 29 20 19 17 6
11
11
53 52 44 37 36 34 32 31 30 29 20 19 17 6
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
BI
VIETMOBILE.VN
1 MHz
0x80, 0x81
0xC6, 0xC7
0xCE, 0xCF
Bus Name
7-Bit Addr.
0x40
Binary
0xAA, 0xAB1100 011X
1100 111X
1100 011X
1000 000X
0x55
0x67
0x63
ISP I2C1 PP1V8_IO 1 MHz
ISP I2C0
ISP I2C1
ISP I2C3
ISP I2C2
ISP I2C0 PP1V8_IO
Bus Voltage
1 MHz
Bus Speed
Raman
Austin
Device 7-Bit Addr. 8-Bit Addr.
-
-
Min Speed
1 MHz
1 MHz
Max Speed Location
Wide Cam
Wide Cam
Bus Name Bus Voltage Bus Speed
Grunberg+
Billings
Device
0x1C
Binary
0011 100X
8-Bit Addr. Min Speed
-
- 1 MHz
Max Speed Location
Tele Cam
ISP I2C2
Bus Voltage
PP1V8_IO
Bus Speed
Yonkers
Flatiron
Savage
0x70
0x18
Min Speed
-
-
-
Max Speed
1 MHz
1 MHz Juliet Flex
Fcam
Fcam
LocationMin Speed
-
1 MHz
Bus SpeedBus Voltage
ISP I2C3
Ansel
8-Bit Addr.
1 MHz Top Board
- Top Board
Top Board
- 1 MHz Top Board
1 MHz- Romeo Flex
Device Binary 8-Bit Addr.
Max Speed
1 MHz
1 MHz-
Bus Name
ISP I2C0X10
0X3C
Binary
0x40, 0x41
0010 000X
0111 100X
0x20, 0x21
0x78, 0x79
7-Bit Addr.
0x20 0100 000X
0x38, 0x39
1 MHz Tele Cam
7-Bit Addr.
0x10
1110 000X
1 MHz
Location
0011 000X
0010 000X
0x30, 0x31
0xE0, 0xE1
0x20, 0x21
Device
Neon
Neon
Rigel
Mama Bear 0x50 1010 000X 0xA0, 0xA1
PP1V8_IO
Bus Name
53 OF 60
I2C3_ISP_SCLI2C3_ISP_SDA
I2C3_ISP_SDA
I2C3_ISP_SDA
I2C3_ISP_SDA
I2C0_ISP_SDA
I2C3_ISP_SCL
I2C3_ISP_SCL
I2C3_ISP_SCL
I2C1_ISP_SCLI2C1_ISP_SDA
I2C0_ISP_SCL
I2C2_ISP_SDA
I2C2_ISP_SCL
I2C2_ISP_SCL
I2C2_ISP_SDA
I2C3_ISP_SCLI2C3_ISP_SDA
7.0.0
67 OF 85
051-02545
2
1 R6701
2
1 R6702
2
1 R6712
2
1 R6711
2
1 R6722
2
1 R6721
2
1 R6732
2
1 R6731
MAKE_BASE=TRUEI2C1_ISP_SCL
I2C3_ISP_SCL MAKE_BASE=TRUE
PP1V8_IO
I2C2_ISP_SCL MAKE_BASE=TRUE
PP1V8_IO
MAKE_BASE=TRUEI2C1_ISP_SDA
PP1V8_IO
MAKE_BASE=TRUEI2C0_ISP_SCLMAKE_BASE=TRUEI2C0_ISP_SDA
PP1V8_IO
I2C2_ISP_SDA MAKE_BASE=TRUE
MAKE_BASE=TRUEI2C3_ISP_SDA
SYSTEM: ISP I2C
ROOM=SOC01005MF1/32W5%1.00K
ROOM=SOC01005MF1/32W5%1.00K
ROOM=SOC01005MF1/32W5%1.00K
37
37
37
37
36
ROOM=SOC01005MF1/32W5%1.00K
36
33
33
33
33
30
30
34
34
32
ROOM=SOC01005MF1/32W5%1.00K
32
31
31
ROOM=SOC01005MF1/32W5%1.00K
ROOM=SOC01005MF1/32W5%1.00K
ROOM=SOC01005MF1/32W5%1.00K
9
9
53 52 44 37 36 34 32 31 30 29 20 19 17 6
9
53 52 44 37 36 34 32 31 30 29 20 19 17 6
9
53 52 44 37 36 34 32 31 30 29 20 19 17 6
9
9
53 52 44 37 36 34 32 31 30 29 20 19 17 6
9
9
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
VIETMOBILE.VN
0x76
AOP I2C1
1110 110X 0xEC, 0xED
0x0E
0x40
0x42
0001 110X
1000 000X 1 MHz
Button Cyclone
Max Speed
1 MHz
Binary
Bus Voltage
1 MHz
Sensor Flex
Sensor Flex
Sensor Flex
8-Bit Addr.
0x82, 0x83
Location
1 MHz
1 MHz
1 MHz
Max SpeedMin Speed
-
-
-
0x66, 0x67
0x52, 0x53
0xB0, 0xB1
8-Bit Addr.
0110 011X
0101 001X
1011 000X
Binary
0x29
0x58
7-Bit Addr.
Yogi
Doppler
DeviceBus Speed
PP1V8_S2
Bus Name
AOP I2C0
0x20, 0x210x10
Bus Voltage
PP1V8_S2
Bus Name
SMC I2C1
SMC I2C1
-
Gas Guage
0010 010X
0x72, 0x73
Min Speed
-
LocationBus Name
Yangtze
0x24, 0x25
0111 001X
1110 001X
Bot Board
Top Board
Roswell
SMC I2C0
Bus Name
400 kHz
Bus Speed Min Speed
400 KHz
400 KHz0xE8, 0xE91110 100X0x74Denali
Top Board0x34, 0x350011 010X0x1A
7-Bit Addr. Location
Hydra
400 kHz
Device Binary 8-Bit Addr.
-
-
Max Speed
Top Board
BMU Flex
BMU Flex
Location
Top Board
400 KHz
400 KHz
Max Speed
-
-
8-Bit Addr.
0xE2, 0xE3
Binary
0x39
0x71
400 KHz
1 MHz
1 MHz -
-
0xAA, 0xAB
0100 000X
0010 010X
0x12
0x55
7-Bit Addr.Device
Iktara
CCG2PP1V8_S2
Min Speed
-
-
1 MHz
Top Board
Top Board
-
Bus Voltage
AOP I2C0
Lives on bottom board
Bus Speed
Bus Voltage
750 kHz
AOP/SMC I2C
0x33
Blackbird
Device
Arc
Moly
Bus Speed
Bottom Speaker
Dock Flex
SMC I2C0
AOP I2C1
Potassium
PP1V8_IMU_S2 0x1C, 0x1D
0x80, 0x81
1000 001X
7-Bit Addr.
400 kHz
I2C0_AOP_SCL
I2C0_SMC_SDA
I2C0_SMC_SCLI2C0_SMC_SDA
I2C0_SMC_SCLI2C0_SMC_SDA
I2C1_SMC_SCLI2C1_SMC_SDA
I2C1_SMC_SCLI2C1_SMC_SDA
I2C0_SMC_SCL
I2C0_SMC_SCL
I2C0_SMC_SDA
I2C1_AOP_SCLI2C1_AOP_SDA
I2C1_AOP_SDAI2C1_AOP_SCL
I2C1_AOP_SDAI2C1_AOP_SCL
I2C1_AOP_SCLI2C1_AOP_SDA
I2C0_AOP_SDA
2
1 R6821
2
1 R6820
2
1 R6823
2
1 R6822
21
R6824
2
1R6841
2
1R6851
2
1R6840
2
1R6850
I2C1_SMC_SCL MAKE_BASE=TRUEI2C1_SMC_SDA MAKE_BASE=TRUE
PP1V8_S2
I2C0_SMC_SDA MAKE_BASE=TRUE
PP1V8_S2
I2C1_AOP_SCL MAKE_BASE=TRUE
I2C0_SMC_SCL MAKE_BASE=TRUE
I2C1_AOP_SDA MAKE_BASE=TRUE
I2C1_AOP_SCL_SOC
I2C0_AOP_SCL MAKE_BASE=TRUE
PP1V8_S2
PP1V8_IMU_S2
I2C0_AOP_SDA MAKE_BASE=TRUE
1.00K5%
MF
ROOM=SOC
1/32W
01005
1.00K5%1/32W
ROOM=SOC
MF01005
1.00K5%
MF01005ROOM=SOC
1/32W
1.00K1/32W
ROOM=SOC
MF01005
5%
01005
0.00
0%1/32WMF
ROOM=B2B_PEARL
23
23
49
49
50
50
48
48
26
26
25
25
27
27
41
41
43
5%2.2K
01005
1/32WMF
ROOM=SOC
43
38
38
ROOM=SOC
MF1/32W
01005
2.2K5%
ROOM=SOC
MF1/32W
01005
2.2K5%
ROOM=SOC
MF1/32W
01005
2.2K5%
11
11
59 54
50 49 48 42 41 40 38 25 20 17
60 11
59 54
50 49 48 42 41 40 38 25 20 17
60 11
13
13
13
59 54
50 49 48 42 41 40 38 25 20 17
50 28 27 20
13
1245678
B
D
8 7 6 5 4 3
C
B
A
C
A
D
2 1
3
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
VIETMOBILE.VN
GPIO_4
GPIO_14
GPIO_5
PMUGPIO_15
GPIO_6
GPIO_7
AP/PMU GPIOs
GPIO_17
GPIO_18
GPIO_16
Held Through 1 Reset
GPIO_9
GPIO_23
GPIO_4
GPIO_5
GPIO_6
GPIO_8
GPIO_24
GPIO_13
GPIO_12
GPIO_1
GPIO_2
GPIO_3
GPIO_22
GPIO_7
Sequenced GPIOs
GPIO_9
GPIO_0
GPIO_25
GPIO_1
GPIO_10
GPIO_28
GPIO_30
GPIO_29
GPIO_20
GPIO_2
GPIO_3
GPIO_27
GPIO_17
GPIO_21
GPIO_26
GPIO_18
GPIO_25
GPIO_8
GPIO_19
IRQ GPIO_16
GPIO_11
GPIO_23
GPIO16 is the only PIN capable of nIRQ
GPIO_14
GPIO_24
SOCGPIO_15
GPIO_12
GPIO_13
GPIO_21
GPIO_22
GPIO_11
GPIO_19
GPIO_20
GPIO_10
55 OF 60
AP_TO_NFC_DEV_WAKE12
CODEC_TO_PMU_WAKE_L23
PMU_TO_NFC_EN23
NC_PMU_GPIO2123
PMU_TO_WLAN_REG_ON23
PMU_TO_NAND_LOW_BATT_BOOT_L23
PMU_TO_IKTARA_EN_EXT_1V823
PMU_TO_PHALANX123
PMU_TO_PHALANX223
PMU_MASK_NFC_TO_ARC_TRIG23
PMU_TO_NFC_VDD_MAIN_EN23
PMU_TO_BOOST_EN23
PMU_TO_GNSS_EN23
PMU_NFC_TO_ARC_RESET_L23
PMU_TO_DISPLAY_PANICB23
PMU_TO_DISPLAY_LDO_EN23
PMU_TO_AP_BUTTON_VOL_UP_L12
AP_TO_SPKRAMP_TOP_RESET_L12
SPKRAMP_TOP_TO_AP_INT_L12
AP_TO_BB_PEAK_POWER_INDICATOR12
BOARD_REV112
YANGTZE_TO_PMU_INT_L23
AP_TO_BBPMU_RADIO_ON_L12
AP_TO_NFC_FW_DWLD_REQ12
AP_TO_BT_DEVICE_WAKE12
BOARD_REV212
AP_TO_GNSS_TIME_MARK12
BOARD_REV312
PMU_TO_AP_THROTTLE_GPU1_L23
CAMPMU_TO_AP_IRQ_L12
NC_AP_GPIO2812
AP_TO_RACER_RESET_L12
PMU_TO_CCG2_RESET_L23
BB_TO_AP_RESET_DETECT_L12
BB_TO_AP_PEAK_POWER_INDICATOR12
AP_TO_BB_COEX12
DISPLAY_TO_AP_PANEL_ID12
AP_TO_CAMPMU_RESET_L12
AP_TO_BB_COREDUMP_TRIG12
PMU_TO_WLAN_CLK32K23
BB_TO_PMU_PCIE_HOST_WAKE_L23
BT_TO_AP_TIME_SYNC12
AP_TO_BB_RESET_L12
WLAN_TO_PMU_HOST_WAKE23
BOARD_REV012
GNSS_TO_AP_LOW_PWR_IND12
AP_CANARY212
NC_AP_GPIO2712
PMU_TO_BT_REG_ON23
AP_CANARY112
NC_AP_GPIO812
BB_TO_AP_COEX12
PMU_TO_BBPMU_RESET_R_L23
PMU_TO_DISPLAY_RESET_L23
AP_TO_PMU_AMUX_SYNC12
NC_BT_TO_PMU_HOST_WAKE23
MAKE_BASE=TRUE
7.0.0
70 OF 85
051-02545
21R3070
MAKE_BASE=TRUECAMPMU_TO_AP_IRQ_L
BT_TO_AP_TIME_SYNCMAKE_BASE=TRUE
AP_TO_BB_RESET_LMAKE_BASE=TRUE
BB_TO_AP_PEAK_POWER_INDICATORMAKE_BASE=TRUE
AP_TO_BB_COREDUMP_TRIGMAKE_BASE=TRUE
SPKRAMP_TOP_TO_AP_INT_LMAKE_BASE=TRUE
BB_TO_AP_COEXMAKE_BASE=TRUE
AP_TO_RACER_RESET_LMAKE_BASE=TRUE
NC_AP_GPIO28MAKE_BASE=TRUE
MAKE_BASE=TRUEPMU_TO_BOOST_EN
PMU_TO_NFC_ENMAKE_BASE=TRUE
MAKE_BASE=TRUEAP_CANARY2
DISPLAY_TO_AP_PANEL_IDMAKE_BASE=TRUE
GNSS_TO_AP_LOW_PWR_INDMAKE_BASE=TRUE
MAKE_BASE=TRUEPMU_TO_GNSS_EN
PMU_NFC_TO_ARC_RESET_LMAKE_BASE=TRUE
PMU_TO_AP_THROTTLE_GPU1_LMAKE_BASE=TRUE
YANGTZE_TO_PMU_INT_LMAKE_BASE=TRUE
CODEC_TO_PMU_WAKE_LMAKE_BASE=TRUE
MAKE_BASE=TRUEPMU_MASK_NFC_TO_ARC_TRIG
PMU_TO_BT_REG_ONMAKE_BASE=TRUE
PMU_TO_DISPLAY_LDO_ENMAKE_BASE=TRUE
NC_PMU_GPIO21MAKE_BASE=TRUE
BB_TO_PMU_PCIE_HOST_WAKE_LMAKE_BASE=TRUE
NC_BT_TO_PMU_HOST_WAKEMAKE_BASE=TRUE
WLAN_TO_PMU_HOST_WAKEMAKE_BASE=TRUE
PMU_TO_PHALANX2MAKE_BASE=TRUE
PMU_TO_CCG2_RESET_LMAKE_BASE=TRUE
BOARD_REV3MAKE_BASE=TRUE
MAKE_BASE=TRUEBOARD_REV2
MAKE_BASE=TRUEAP_TO_BT_DEVICE_WAKE
MAKE_BASE=TRUEBOARD_REV0
MAKE_BASE=TRUEAP_TO_NFC_FW_DWLD_REQ
MAKE_BASE=TRUEAP_TO_NFC_DEV_WAKE
AP_TO_GNSS_TIME_MARKMAKE_BASE=TRUE
MAKE_BASE=TRUEAP_TO_BB_PEAK_POWER_INDICATOR
AP_TO_BBPMU_RADIO_ON_LMAKE_BASE=TRUE
MAKE_BASE=TRUEPMU_TO_AP_BUTTON_VOL_UP_L
AP_CANARY1MAKE_BASE=TRUE
MAKE_BASE=TRUEAP_TO_SPKRAMP_TOP_RESET_L
BB_TO_AP_RESET_DETECT_LMAKE_BASE=TRUE
AP_TO_CAMPMU_RESET_LMAKE_BASE=TRUE
AP_TO_BB_COEXMAKE_BASE=TRUE
NC_AP_GPIO8MAKE_BASE=TRUE
AP_TO_PMU_AMUX_SYNCMAKE_BASE=TRUE
NC_AP_GPIO27MAKE_BASE=TRUE
PMU_TO_BBPMU_RESET_L
PMU_TO_WLAN_CLK32KMAKE_BASE=TRUE
PMU_TO_DISPLAY_PANICBMAKE_BASE=TRUE
MAKE_BASE=TRUEBOARD_REV1
PMU_TO_BBPMU_RESET_R_LMAKE_BASE=TRUE
PMU_TO_IKTARA_EN_EXT_1V8MAKE_BASE=TRUE
PMU_TO_DISPLAY_RESET_L
PMU_TO_PHALANX1MAKE_BASE=TRUE
PMU_TO_NAND_LOW_BATT_BOOT_LMAKE_BASE=TRUE
PMU_TO_WLAN_REG_ONMAKE_BASE=TRUE
PMU_TO_NFC_VDD_MAIN_ENMAKE_BASE=TRUE
SYSTEM: SOC/PMU GPIOsSYNC_DATE=05/09/2017
CDS_LIB=apple
57
57
57
58
6
58
19
57
58
6
50
43
40
43
50
44
42
60
6
23
57
57
57
58
44
57 30
57
57
30
6
23
42
1.00K
5%1/32WMF
01005ROOM=PMU
58
60
24
44
44
58
57
26
58
58 23
58
58
57
7
48
57
57
57
58
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
OUT
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
OUT
IN
OUT
IN
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
VIETMOBILE.VN
AOP_FUNC_3
AOP_FUNC_9
A0P GPIOs
AOP_FUNC_13
AOP_FUNC_14
AOP_FUNC_15
SCM_I2CM0 TRIGGER --->
AOP_FUNC_18
AOP_FUNC_19
AOP_FUNC_20
AOP_FUNC_21
AOP_FUNC_22
AOP_FUNC_17
AOP_FUNC_10
AOP_FUNC_0
AOP_FUNC_1
AOP_FUNC_2
AOP_FUNC_6
AOP
AOP_FUNC_11
AOP_FUNC_7
SCM_I2CM1 TRIGGER >
SCM_SPI TRIGGER & CS >
AOP_FUNC_12
AOP_FUNC_16
AOP_FUNC_5
AOP_FUNC_4
AOP_FUNC_8
56 OF 60
HALL_CASE_TO_AOP_SOUTH_L13
NC_AOP_FUNC813
PROX_BI_AOP_INT_L13
NC_AOP_FUNC1213
SPI_AOP_TO_IMU_CS_L13
HALL_FLAP_TO_AOP_IRQ_L13
NC_AOP_FUNC1113
AOP_TO_CODEC_CLP_EN13
AOP_TO_BBPMU_COEX13
SPI_AOP_TO_PHOSPHORUS_CS_L13
PHOSPHORUS_TO_AOP_INT13
AOP_TO_GECKO_RESET_L13
POTASSIUM_TO_AOP_INT13
ROMEO_TO_AOP_B2B_DETECT13
IMU_TO_AOP_INT13
COMPASS_TO_AOP_INT13
NFC_TO_AOP_HOST_WAKE13
AOP_TO_SPKAMP_BOT_RESET_L13
IMU_TO_AOP_DATARDY13
ALS_TO_AOP_INT_L13
SPKAMP_BOT_ARC_TO_AOP_INT_L13
AOP_TO_HALOGEN_AFE_EN13
HALL_CASE_TO_AOP_NORTH_L13
GECKO_TO_AOP_IRQ_L13
AOP_TO_CODEC_RESET_L13
RACER_TO_AOP_INT_L13
NC_AOP_FUNC1013
7.0.0
71 OF 85
051-02545
MAKE_BASE=TRUESPI_AOP_TO_PHOSPHORUS_CS_L
AOP_TO_SPKAMP_BOT_RESET_LMAKE_BASE=TRUE
MAKE_BASE=TRUESPI_AOP_TO_IMU_CS_L
IMU_TO_AOP_DATARDYMAKE_BASE=TRUE
ROMEO_TO_AOP_B2B_DETECTMAKE_BASE=TRUE
MAKE_BASE=TRUEAOP_TO_CODEC_RESET_L
MAKE_BASE=TRUEPHOSPHORUS_TO_AOP_INT
RACER_TO_AOP_INT_LMAKE_BASE=TRUE
MAKE_BASE=TRUEPROX_BI_AOP_INT_L
MAKE_BASE=TRUECOMPASS_TO_AOP_INT
MAKE_BASE=TRUEAOP_TO_HALOGEN_AFE_EN
NC_AOP_FUNC10MAKE_BASE=TRUE
MAKE_BASE=TRUENFC_TO_AOP_HOST_WAKE
MAKE_BASE=TRUEPOTASSIUM_TO_AOP_INT
MAKE_BASE=TRUEALS_TO_AOP_INT_L
HALL_CASE_TO_AOP_SOUTH_LMAKE_BASE=TRUE
HALL_CASE_TO_AOP_NORTH_LMAKE_BASE=TRUE
AOP_TO_GECKO_RESET_LMAKE_BASE=TRUE
GECKO_TO_AOP_IRQ_LMAKE_BASE=TRUE
MAKE_BASE=TRUESPKAMP_BOT_ARC_TO_AOP_INT_L
MAKE_BASE=TRUEHALL_FLAP_TO_AOP_IRQ_L
NC_AOP_FUNC8MAKE_BASE=TRUE
AOP_TO_BBPMU_COEXMAKE_BASE=TRUE
MAKE_BASE=TRUEAOP_TO_CODEC_CLP_EN
NC_AOP_FUNC12MAKE_BASE=TRUE
MAKE_BASE=TRUEIMU_TO_AOP_INT
MAKE_BASE=TRUENC_AOP_FUNC11
SYNC_DATE=05/09/2017
CDS_LIB=apple
SYSTEM: AOP GPIOs
47 5
57
58
58
28
60
50
41
43 41 5
38
27 5
38
38
40
40
60
37
28 5
28
28
28 5
46
47
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
OUT
OUT
IN
OUT
IN
VIETMOBILE.VN
THIS SIDE HAS ATTRIBUTE
MAKE_BASE=TRUEMAKE_BASE=TRUETHIS SIDE HAS ATTRIBUTE
Interposer Aliases: Pins 1-144
57 OF 60
GNSS_TO_AP_LOW_PWR_IND51
AP_TO_RACER_RESET_L51
GND51
AP_TO_CAMPMU_RESET_L51
GND51
GND51
GND51
GND51
AP_TO_WLAN_TIME_SYNC51
GND51
AP_TO_BB_COEX51
90_PCIE_AP_TO_BB_TXD_P51
90_PCIE_AP_TO_BB_TXD_N51
90_PCIE_BB_TO_AP_RXD_N51
90_PCIE_BB_TO_AP_RXD_P51
AP_TO_GNSS_TIME_MARK51
PP_VDD_MAIN51
GND51
PMU_TO_SYSTEM_COLD_RESET_L51
PP1V8_ALWAYS51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
I2S_BB_TO_AP_BCLK51
I2S_BB_TO_AP_LRCLK51
GND 57 58 59 60 MAKE_BASE=TRUE
GND51
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND51
GND51
NFC_TO_ARC_RESET_L51
GND 57 59 MAKE_BASE=TRUE
GND51
GND51
GND 57 58 59 60 MAKE_BASE=TRUE
AP_TO_BB_RESET_L51
GND51
GND51
GND 57 59 MAKE_BASE=TRUE
GND51
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
HYDRA_TO_AP_FORCE_DFU51
GND51
PP1V8_S251
GND 57 59 MAKE_BASE=TRUE
GND51
PP1V8_S251
GND51
GND51
GND 57 59 MAKE_BASE=TRUE
GND51
GND51 GND 57 58 59 MAKE_BASE=TRUE
PP_VDD_MAIN51
GND 57 58 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUEGND51
GND51
GND 57 59 MAKE_BASE=TRUE
UART_GNSS_TO_AP_CTS_L51
GND51
SWD_AOP_BI_BB_SWDIO51
GND 57 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND51
UART_AP_TO_GNSS_RTS_L51
GND51
GND 57 58 59 MAKE_BASE=TRUE
PP_VDD_MAIN51
UART_AP_TO_NFC_TXD51
AP_TO_BB_COREDUMP_TRIG51
PMU_TO_NFC_VDD_MAIN_EN51
GND51
BOARD_ID251
PP_VDD_MAIN51
UART_AP_TO_NFC_RTS_L51
GND51
UART_NFC_TO_AP_CTS_L51
GND 57 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND51
GND51
GND51
GND 57 59 MAKE_BASE=TRUE
GND51
AP_TO_TOUCH_SCAN_CLK51
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND51
GND 57 58 59 MAKE_BASE=TRUE
GND51
GND51
GND51
GND51
PCIE_AP_TO_BB_PERST_L51
UART_GNSS_TO_AP_RXD51
90_PCIE_AP_TO_BB_REFCLK_N51
GND51
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
UART_NFC_TO_AP_RXD51
GND51
PCIE_AP_TO_WLAN_PERST_L51
GND51
GND51
GND51
GND51
GND51
GND51
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
90_PCIE_AP_TO_BB_REFCLK_P51
GND51
AP_TO_BBPMU_RADIO_ON_L51
AP_TO_BB_PEAK_POWER_INDICATOR51
GND51
GND 57 59 MAKE_BASE=TRUE
GND51
AP_TO_NFC_FW_DWLD_REQ51
AP_TO_NFC_DEV_WAKE51
GND51
UART_BB_TO_AOP_RXD51
GND 57 58 59 60 MAKE_BASE=TRUE
UART_AP_TO_GNSS_TXD51
UART_AOP_TO_BB_TXD51
BB_TO_AP_RESET_DETECT_L51
GND 59 MAKE_BASE=TRUE
GND51
I2S_AP_TO_BB_DOUT51
GND51
GND51
GND 57 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND51
GND51
GND 57 58 59 60 MAKE_BASE=TRUE
HALL_CASE_TO_AOP_NORTH_L51
GND51
GND 57 59 MAKE_BASE=TRUE
GND51
GND51
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND51
GND 57 58 59 60 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND 57 59 MAKE_BASE=TRUE
GND51
GND51
GND 57 59 MAKE_BASE=TRUE
GND51
I2S_BB_TO_AP_DIN51
NFC_TO_ARC_TRIG51
GND 59 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUEGND51
BB_TO_MANY_GSM_BURST_IND51
GND51
PP_VDD_MAIN51
PP_VDD_MAIN 59 PP_VDD_MAIN51
PP_VDD_MAIN 59
PP_VDD_MAIN 59
PP_VDD_MAIN 59
GND 57 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
PP1V8_S2 59
PP1V8_S2 59
GND 57 58 59 60 MAKE_BASE=TRUE
BB_TO_AP_COEX51
GND 59 MAKE_BASE=TRUE
INTERPOSER_PIN_90
GND51
GND51 GND 57 58 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUEGND51
BB_TO_AP_PEAK_POWER_INDICATOR51
PMU_AMUX_BY51
PMU_AMUX_AY51
GND51
PCIE_BB_BI_AP_CLKREQ_L51
GND 57 59 MAKE_BASE=TRUE
PP_VDD_MAIN 59
PP_VDD_MAIN 59
NC_INT_13551
NC_INTERPOSER_10951
GND 59 MAKE_BASE=TRUE
7.0.0
81 OF 85
051-02545
PCIE_AP_TO_WLAN_PERST_LMAKE_BASE=TRUE
AP_TO_RACER_RESET_LMAKE_BASE=TRUE
INTERPOSER_PIN_90
90_PCIE_BB_TO_AP_RXD_PMAKE_BASE=TRUE
MAKE_BASE=TRUE UART_AP_TO_GNSS_RTS_L
MAKE_BASE=TRUE UART_AP_TO_NFC_RTS_L
90_PCIE_BB_TO_AP_RXD_NMAKE_BASE=TRUE
PMU_TO_SYSTEM_COLD_RESET_LMAKE_BASE=TRUE
PMU_AMUX_BYMAKE_BASE=TRUE
90_PCIE_AP_TO_BB_REFCLK_NMAKE_BASE=TRUE
90_PCIE_AP_TO_BB_TXD_PMAKE_BASE=TRUE
90_PCIE_AP_TO_BB_TXD_NMAKE_BASE=TRUE
AP_TO_WLAN_TIME_SYNCMAKE_BASE=TRUE
GNSS_TO_AP_LOW_PWR_INDMAKE_BASE=TRUE
MAKE_BASE=TRUE HYDRA_TO_AP_FORCE_DFU
MAKE_BASE=TRUE UART_NFC_TO_AP_CTS_L
PCIE_AP_TO_BB_PERST_LMAKE_BASE=TRUE
UART_BB_TO_AOP_RXDMAKE_BASE=TRUE
90_PCIE_AP_TO_BB_REFCLK_PMAKE_BASE=TRUE
MAKE_BASE=TRUE UART_GNSS_TO_AP_RXD
MAKE_BASE=TRUE BB_TO_AP_RESET_DETECT_L
UART_NFC_TO_AP_RXDMAKE_BASE=TRUE
MAKE_BASE=TRUE UART_AP_TO_NFC_TXD
MAKE_BASE=TRUE AP_TO_NFC_FW_DWLD_REQMAKE_BASE=TRUE AP_TO_NFC_DEV_WAKE
MAKE_BASE=TRUE SWD_AOP_BI_BB_SWDIO
MAKE_BASE=TRUE UART_GNSS_TO_AP_CTS_L
AP_TO_BB_RESET_LMAKE_BASE=TRUE
NFC_TO_ARC_TRIGMAKE_BASE=TRUE
NFC_TO_ARC_RESET_LMAKE_BASE=TRUE
MAKE_BASE=TRUE I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_DINMAKE_BASE=TRUE
MAKE_BASE=TRUE AP_TO_TOUCH_SCAN_CLK
HALL_CASE_TO_AOP_NORTH_LMAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE AP_TO_BB_PEAK_POWER_INDICATOR
MAKE_BASE=TRUE AP_TO_BBPMU_RADIO_ON_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCIE_BB_BI_AP_CLKREQ_LMAKE_BASE=TRUE
UART_AOP_TO_BB_TXDMAKE_BASE=TRUE
UART_AP_TO_GNSS_TXDMAKE_BASE=TRUE
PP1V8_ALWAYSMAKE_BASE=TRUE
MAKE_BASE=TRUE I2S_BB_TO_AP_LRCLK
I2S_AP_TO_BB_DOUTMAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
BB_TO_MANY_GSM_BURST_INDMAKE_BASE=TRUE
MAKE_BASE=TRUE AP_TO_CAMPMU_RESET_L
MAKE_BASE=TRUE AP_TO_BB_COEX
MAKE_BASE=TRUE BB_TO_AP_COEX
PMU_AMUX_AYMAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
BB_TO_AP_PEAK_POWER_INDICATORMAKE_BASE=TRUE
NC_INT_135MAKE_BASE=TRUE
NC_INTERPOSER_109MAKE_BASE=TRUE
AP_TO_GNSS_TIME_MARKMAKE_BASE=TRUE
BOARD_ID2MAKE_BASE=TRUE
AP_TO_BB_COREDUMP_TRIGMAKE_BASE=TRUE
PMU_TO_NFC_VDD_MAIN_ENMAKE_BASE=TRUE
SYNC_DATE=08/29/2017
Interposer: Pins 1-144
8
55
51
17
12
12
17
23 15 7
23
8
17
17
12
55
49 12
12
8
13
8
12
55
12
12
55
55
13
12
55
43 5
43 5
11
11
9
56
55
55
8
13
12
26 23 22 17
11
11
38 33
55 30
55
55
23
55
55
12 6
55
55
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VIETMOBILE.VN
MAKE_BASE=TRUETHIS SIDE HAS ATTRIBUTE
MAKE_BASE=TRUE
Interposer Aliases: Pins 145-285
THIS SIDE HAS ATTRIBUTE
58 OF 60
GND51
I2C3_AP_SDA51
CKPLUS_WAIVE=I2C_PULLUP
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
PP1V1_RACER_S2 59
PP_BATT_VCC51
90_PCIE_AP_TO_WLAN_TXD_N51
90_PCIE_WLAN_TO_AP_RXD_N51
GND51
PP1V8_TOUCH_RACER_S251
GND51
GND 58 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
90_PCIE_AP_TO_WLAN_REFCLK_P51
GND51
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
UART_BT_TO_AP_RXD51
PP_VBUS1_E7551
GND51
GND51
GND51
GND51
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
I2C3_AP_SCL51
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND51
GND51
GND 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
PP1V8_TOUCH_RACER_S2 59
PP_BATT_VCC51
PP_VBUS2_IKTARA 59
PP_VBUS2_IKTARA 59
GND 58 59 MAKE_BASE=TRUE
PP_VDD_MAIN51
PP_VDD_MAIN51
GND51
UART_AP_TO_BT_TXD51
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND51
UART_BT_TO_AP_CTS_L51
GND51
GND 59 MAKE_BASE=TRUE
GND51
GND 57 58 59 MAKE_BASE=TRUE
GND51
GND 57 58 59 MAKE_BASE=TRUE
PP_VDD_MAIN 59
GND51
GND51
GND51
GND51
RADIO_PA_NTC51
UART_AOP_TO_RACER_TXD51
GND51
GND51
SPI_AP_TO_RACER_CS_L51
GND51
GND51
GND51
GND51
GND51
GND51
PP_VBUS2_IKTARA51
AOP_TO_WLAN_CONTEXT_B51
GND 58 59 MAKE_BASE=TRUE
AOP_TO_WLAN_CONTEXT_A51
GND51
PP_GPU_LVCC51
GND51
GND51
PP3V0_S251
PP1V8_TOUCH_RACER_S251
GND51
GND51
GND51
PP_VBUS2_IKTARA51
PP_VBUS2_IKTARA51
90_PCIE_AP_TO_WLAN_REFCLK_N51
GND51
BT_TO_AP_TIME_SYNC51
PMU_TO_WLAN_REG_ON51
UART_AP_TO_BT_RTS_L51
GND51
GND51
GND51
GND51
SPI_RACER_TO_AP_MISO51
GND51
AOP_TO_BBPMU_COEX51
PP_VBUS2_IKTARA51
PP_CPU_PCORE_LVCC51
GND51
SWD_AOP_BI_RACER_SWDIO51
GND51
GND51
GND51
PMU_TO_GNSS_EN51
PP1V8_NFC_S251
GND51
PMU_TO_BT_REG_ON51
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
PP1V1_RACER_S2 59
PP_VBUS2_IKTARA 59
GND51
GND51
GND51
GND51
GND51
UART_RACER_TO_AOP_RXD51
GND51
AP_TO_RACER_REF_CLK51
PP1V1_RACER_S251
PP1V1_RACER_S251
GND 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
PP_VBUS2_IKTARA 59
CKPLUS_WAIVE=I2C_PULLUP
GND51
90_PCIE_WLAN_TO_AP_RXD_P51
90_PCIE_AP_TO_WLAN_TXD_P51
GND51
AP_CANARY251
GND51
GND51
GND51
GND51
GND 57 58 59 MAKE_BASE=TRUE
GND51
GND51
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
TOUCH_TO_MANY_FORCE_PWM51
GND 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND51
GND51
NFC_TO_AOP_HOST_WAKE51
GND51
GND 57 58 59 MAKE_BASE=TRUEGND51
GND51
GND 57 58 59 MAKE_BASE=TRUE
GND51
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND51
GND 57 58 59 MAKE_BASE=TRUE
GND51
BB_TO_PMU_PCIE_HOST_WAKE_L51
GND51
PMU_TO_WLAN_CLK32K51
GND51
PP_VDD_MAIN51
PP_VDD_MAIN51
GND 57 58 59 MAKE_BASE=TRUE
GND51
PMU_TO_TOUCH_CLK32K51
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
PMU_TO_IKTARA_RESET_L51
GND51
GND51
GND51
GND51
GND 57 59 60 MAKE_BASE=TRUE
WLAN_TO_PMU_HOST_WAKE51
GND 57 58 59 MAKE_BASE=TRUE
PMU_TO_NFC_EN51
PMU_TO_BBPMU_RESET_L51
GND 58 59 MAKE_BASE=TRUE
PP1V8_TOUCH_RACER_S2 59
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
PCIE_WLAN_BI_AP_CLKREQ_L51
GND51
PP_VDD_MAIN 59
PP_VDD_MAIN 59
PP_VDD_MAIN 59
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
GND51
GND51
GND 57 58 59 MAKE_BASE=TRUE
GND 57 58 59 MAKE_BASE=TRUE
PP1V1_RACER_S251
GND51
GND51 GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND51
AP_TO_BT_DEVICE_WAKE51
SWD_AOP_TO_MANY_SWCLK51
SPI_AP_TO_RACER_MOSI51
SPI_AP_TO_RACER_SCLK51
PP1V1_RACER_S2 59
PP_BATT_VCC 59
PP_BATT_VCC 59
GND 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND 58 59 MAKE_BASE=TRUE
GND51
7.0.0
82 OF 85
051-02545
MAKE_BASE=TRUE I2C3_AP_SCL
PMU_TO_IKTARA_RESET_LMAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_TO_BT_DEVICE_WAKEMAKE_BASE=TRUE
MAKE_BASE=TRUE PMU_TO_WLAN_REG_ON
BT_TO_AP_TIME_SYNCMAKE_BASE=TRUE
UART_BT_TO_AP_RXDMAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_CANARY2MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE AOP_TO_WLAN_CONTEXT_B
MAKE_BASE=TRUE
AOP_TO_BBPMU_COEXMAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_TO_RACER_REF_CLKMAKE_BASE=TRUE
MAKE_BASE=TRUE
SPI_AP_TO_RACER_CS_LMAKE_BASE=TRUE
MAKE_BASE=TRUE I2C3_AP_SDA
MAKE_BASE=TRUE SWD_AOP_BI_RACER_SWDIO
MAKE_BASE=TRUE PMU_TO_TOUCH_CLK32K
UART_RACER_TO_AOP_RXDMAKE_BASE=TRUE
MAKE_BASE=TRUE SPI_RACER_TO_AP_MISO
PMU_TO_NFC_ENMAKE_BASE=TRUE
NFC_TO_AOP_HOST_WAKEMAKE_BASE=TRUE
PP1V8_NFC_S2MAKE_BASE=TRUE
MAKE_BASE=TRUE PMU_TO_GNSS_EN
RADIO_PA_NTCMAKE_BASE=TRUE
MAKE_BASE=TRUE 90_PCIE_AP_TO_WLAN_TXD_N
MAKE_BASE=TRUE 90_PCIE_AP_TO_WLAN_REFCLK_N
MAKE_BASE=TRUE PMU_TO_BT_REG_ON
MAKE_BASE=TRUE 90_PCIE_AP_TO_WLAN_TXD_P
MAKE_BASE=TRUE 90_PCIE_AP_TO_WLAN_REFCLK_P
MAKE_BASE=TRUE 90_PCIE_WLAN_TO_AP_RXD_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE PP3V0_S2
MAKE_BASE=TRUE 90_PCIE_WLAN_TO_AP_RXD_P
PMU_TO_WLAN_CLK32KMAKE_BASE=TRUE
MAKE_BASE=TRUE UART_AP_TO_BT_RTS_L
MAKE_BASE=TRUE UART_AP_TO_BT_TXD
TOUCH_TO_MANY_FORCE_PWMMAKE_BASE=TRUE
PMU_TO_BBPMU_RESET_LMAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCIE_WLAN_BI_AP_CLKREQ_LMAKE_BASE=TRUE
WLAN_TO_PMU_HOST_WAKEMAKE_BASE=TRUE
BB_TO_PMU_PCIE_HOST_WAKE_LMAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE SPI_AP_TO_RACER_SCLKMAKE_BASE=TRUE SPI_AP_TO_RACER_MOSI
SWD_AOP_TO_MANY_SWCLKMAKE_BASE=TRUE
UART_AOP_TO_RACER_TXDMAKE_BASE=TRUE
AOP_TO_WLAN_CONTEXT_AMAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE PP_CPU_PCORE_LVCC
PP_GPU_LVCCMAKE_BASE=TRUE
PP_VBUS1_E75MAKE_BASE=TRUE
UART_BT_TO_AP_CTS_LMAKE_BASE=TRUE
Interposer: Pins 145-285
SYNC_DATE=08/30/2017
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45 23
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52 11
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17
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APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VIETMOBILE.VN
Ground Aliases
Interposer Top Level Aliases
Power Aliases
59 OF 60
PP1V1_RACER_S258
GND57
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GND58
GND58
GND57
GND60
GND57
GND57
GND57
GND58
GND58
GND60
GND58
GND60
GND60
GND60
GND60
GND60
GND60
GND57
GND60
GND58
GND60
GND58
GND58
GND58
GND58
GND57
GND57
GND57
GND57
GND57
GND57
GND57
GND58
GND57
GND57
GND57 58 60
GND57
GND57 58
PP_VDD_BOOST
PP_VDD_BOOST
PP_BATT_VCC58
PP_VDD_MAIN58
PP_VDD_MAIN57
PP1V8_TOUCH_RACER_S258
PP1V8_TOUCH_RACER_S258
IKTARA_COIL160
IKTARA_COIL160
IKTARA_COIL160
IKTARA_COIL260
IKTARA_COIL260
IKTARA_COIL260
IKTARA_COIL260
PP_VDD_MAIN57
PP_VDD_MAIN58
PP_VBUS2_IKTARA58
PP_VDD_MAIN58
PP1V8_S257
IKTARA_COIL1
PP_VBUS2_IKTARA58
PP1V8_S257
PP_VDD_MAIN57
PP_VBUS2_IKTARA58
PP_VBUS2_IKTARA58
PP_VDD_MAIN58
PP_VDD_MAIN57
PP_VDD_MAIN57
PP_VDD_MAIN
PP_VDD_MAIN57
PP_BATT_VCC58
PP1V1_RACER_S258
PP1V1_RACER_S258
7.0.0
83 OF 85
051-02545
IKTARA_COIL2MAKE_BASE=TRUE
IKTARA_COIL1MAKE_BASE=TRUE
PP1V8_TOUCH_RACER_S2MAKE_BASE=TRUE
PP_VBUS2_IKTARAMAKE_BASE=TRUE
MAKE_BASE=TRUE
PP_VDD_BOOST
MAKE_BASE=TRUE
PP_BATT_VCC
MAKE_BASE=TRUE
PP1V1_RACER_S2
PP1V8_S2MAKE_BASE=TRUE
PP_VDD_MAINMAKE_BASE=TRUE
Interposer: Top Aliases
SYNC_DATE=08/17/2017
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27
20
26
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26 25
22
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I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VIETMOBILE.VN
MAKE_BASE=TRUETHIS SIDE HAS ATTRIBUTE THIS SIDE HAS ATTRIBUTE
MAKE_BASE=TRUE
60 OF 60
GND 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND51
GND 59 60 MAKE_BASE=TRUE
AP_CANARY151
GND51
GND51
GND51
GND51
GND 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND51
GND 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
IKTARA_COIL2 59
IKTARA_COIL1 59
GND 59 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUEGND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND51
GND 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
IKTARA_COIL2 59
GND 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND51
GND51
GND51
GND51
GND51
IKTARA_COIL251
I2C0_SMC_SDA51
HALL_CASE_TO_AOP_SOUTH_L51
ACORN_GECKO_ANSEL_TO_PMU_ADC51
PMU_TO_IKTARA_EN_EXT_1V851
GND 59 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUEGND51
GND51
GND 59 60 MAKE_BASE=TRUE
GND51
IKTARA_COIL151
IKTARA_COIL151
GND51
IKTARA_COIL251
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
GND51
IKTARA_COIL151
RACER_TO_AOP_INT_L51
GND51
IKTARA_TO_SMC_INT51
I2C0_SMC_SCL51
GND51
GND 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND51
GND51
GND51
GND51
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND51
GND51
GND 59 60 MAKE_BASE=TRUE
GND51
IKTARA_COIL151
NC_INTERPOSER_31151
GND 57 58 59 60 MAKE_BASE=TRUE
GND 57 58 59 60 MAKE_BASE=TRUE
GND 59 MAKE_BASE=TRUE
GND51
GND51
GND 57 58 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND51
IKTARA_COIL1 59
IKTARA_COIL1 59
IKTARA_COIL2 59
IKTARA_COIL251
IKTARA_COIL251
GND51
IKTARA_COIL2 59
GND 59 MAKE_BASE=TRUE
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
NC_INTERPOSER_30951
GND51 GND 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
GND 59 60 MAKE_BASE=TRUE
IKTARA_COIL1 59
7.0.0
85 OF 85
051-02545
MAKE_BASE=TRUE AP_CANARY1
MAKE_BASE=TRUE HALL_CASE_TO_AOP_SOUTH_L
MAKE_BASE=TRUE PMU_TO_IKTARA_EN_EXT_1V8
RACER_TO_AOP_INT_LMAKE_BASE=TRUE
ACORN_GECKO_ANSEL_TO_PMU_ADCMAKE_BASE=TRUE
MAKE_BASE=TRUE IKTARA_TO_SMC_INT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE I2C0_SMC_SDAMAKE_BASE=TRUE I2C0_SMC_SCL
MAKE_BASE=TRUE NC_INTERPOSER_311
MAKE_BASE=TRUE NC_INTERPOSER_309
MAKE_BASE=TRUE
Interposer: Pins 286-359SYNC_DATE=08/30/2017
CDS_LIB=apple
55
56
55
56
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11
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
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PAGE
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DRAWING NUMBER
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67
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APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VIETMOBILE.VN