-
IPC-7095BDesign and Assembly Process
Implementation for BGAsMarch 2008
Association Connecting Electronics Industries
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The Principles ofStandardization
In May 1995 the IPCs Technical Activities Executive Committee
(TAEC) adopted Principles ofStandardization as a guiding principle
of IPCs standardization efforts.
Standards Should: Show relationship to Design for
Manufacturability
(DFM) and Design for the Environment (DFE) Minimize time to
market Contain simple (simplified) language Just include spec
information Focus on end product performance Include a feedback
system on use and
problems for future improvement
Standards Should Not: Inhibit innovation Increase time-to-market
Keep people out Increase cycle time Tell you how to make something
Contain anything that cannot
be defended with data
Notice IPC Standards and Publications are designed to serve the
public interest through eliminating mis-understandings between
manufacturers and purchasers, facilitating interchangeability and
improve-ment of products, and assisting the purchaser in selecting
and obtaining with minimum delay theproper product for his
particular need. Existence of such Standards and Publications shall
not inany respect preclude any member or nonmember of IPC from
manufacturing or selling productsnot conforming to such Standards
and Publication, nor shall the existence of such Standards
andPublications preclude their voluntary use by those other than
IPC members, whether the standardis to be used either domestically
or internationally.
Recommended Standards and Publications are adopted by IPC
without regard to whether their adop-tion may involve patents on
articles, materials, or processes. By such action, IPC does not
assumeany liability to any patent owner, nor do they assume any
obligation whatever to parties adoptingthe Recommended Standard or
Publication. Users are also wholly responsible for protecting
them-selves against all claims of liabilities for patent
infringement.
IPC PositionStatement onSpecificationRevision Change
It is the position of IPCs Technical Activities Executive
Committee that the use and implementationof IPC publications is
voluntary and is part of a relationship entered into by customer
and supplier.When an IPC publication is updated and a new revision
is published, it is the opinion of the TAECthat the use of the new
revision as part of an existing relationship is not automatic
unless requiredby the contract. The TAEC recommends the use of the
latest revision. Adopted October 6, 1998
Why is therea charge forthis document?
Your purchase of this document contributes to the ongoing
development of new and updated industrystandards and publications.
Standards allow manufacturers, customers, and suppliers to
understandone another better. Standards allow manufacturers greater
efficiencies when they can set up theirprocesses to meet industry
standards, allowing them to offer their customers lower costs.
IPC spends hundreds of thousands of dollars annually to support
IPCs volunteers in the standardsand publications development
process. There are many rounds of drafts sent out for review andthe
committees spend hundreds of hours in review and development. IPCs
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IPCs membership dues have been kept low to allow as many
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Theprice schedule offers a 50% discount to IPC members. If your
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Thank you for your continued support.
Copyright 2008. IPC, Bannockburn, Illinois. All rights reserved
under both international and Pan-American copyright conventions.
Any copying,scanning or other reproduction of these materials
without the prior written consent of the copyright holder is
strictly prohibited and constitutesinfringement under the Copyright
Law of the United States.
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IPC-7095B
Design and
Assembly Process
Implementation
for BGAs
Developed by the Device Manufacturers InterfaceCommittee of
IPC
Users of this publication are encouraged to participate in
thedevelopment of future revisions.
Contact:
IPC3000 Lakeside Drive, Suite 309SBannockburn,
Illinois60015-1249Tel 847 615.7100Fax 847 615.7105
Supersedes:IPC-7095A - October 2004IPC-7095 - August 2000
July 3, 2008
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This Page Intentionally Left Blank
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AcknowledgmentAny document involving a complex technology draws
material from a vast number of sources. While the principal
membersof the IPC Ball Grid Array Task Group (5-21f) of the
Assembly & Joining Processes Committee (5-20) are shown
below,it is not possible to include all of those who assisted in
the evolution of this standard. To each of them, the members of
theIPC extend their gratitude.
Assembly & JoiningProcesses Committee
Ball Grid ArrayTask Group
Technical Liaisons of theIPC Board of Directors
ChairLeo P. LambertEPTAC Corporation
Vice ChairRenee J. MichalkiewiczTrace Laboratories - East
ChairRay PrasadRay Prasad Consultancy Group
Peter BigelowIMI Inc.
Sammy YiFlextronics International
Ball Grid Array Task Group
David Adams, Rockwell CollinsSyed Ahmad, NDSUDudi Amir, Intel
CorporationRaiyomand Aspandiar, Intel
CorporationDavid Brown, Lockheed Martin
AeronauticsLyle Burhenn, BAE SystemsScott Buttars, Intel
CorporationBeverley Christian, Research in
Motion Ltd.Geoffrey Dick, Lockheed MartinAllen Donaldson, Intel
CorporationDon Dupriest, Lockheed Martin
Missiles and Fire ControlWerner Engelmaier, Engelmaier
AssociatesGary Ferrari, FTG CircuitsJoe Fjelstad, SiliconPipe
Inc.Lionel Fullwood, WKK DistributionMahendra Gandhi, Northrop
Grumman Space TechnologyHue Green, Lockheed Martin Space
SystemsMike Green, Lockheed Martin Space
Systems
Constantin Hudon, VaritronTechnologies
Greg Hurst, BAE SystemsGlen Leinbach, Agilent TechnologiesPaul
Lotosky, Cookson ElectronicsHelen Lowe, CelesticaRobert Mazium,
Phoenix/X-RayKaren McConnell, Lockheed Martin
EPICenterGeorge Milad, Uyemura Inl
CorporationJim Moffit, Moffit Consulting
ServicesBarry Morris, Advanced Rework
TechnologyGeorge Oxx, Flextronics Technology
Inc.Deepak Pai, General Dynamics Adv
Info SysMel Parrish, Soldering Technology
InternationalSam Polk, Lockheed Martin Missiles
and Fire ControlRay Prasad, Ray Prasad Consultancy
GroupGuy Ramsey, R&D AssemblyTeresa Rowe, AAI
Corporation
Robert Rowland, RadiSysJim Rudig, Intel CorporationWaleed
Rusheidat, Jabil CircuitMarty Scionti, Raytheon Missile
SystemsGregory Servis, Lockheed MartinVern Solberg, Solberg
Technical
ConsultingKerry Spencer, Lockheed Martin
Missle & Fire ControlDung Tiet, Lockheed Martin Space
SystemsNeil Trelford, NortelKris Troxel, Hewlett PackardDave
Vanacek, Lockheed Martin
AeronauticsSharon Ventress, U.S. Army Aviation
& MissileRob Walls, PIEKDewey Whittaker, Honeywell
AerospaceLinda Woody, Lockheed MartinFonda Wu, Raytheon
Electronics
SystemsMichael Yuen, Microsoft Corp.Gil Zweig, Glenbrook
Technologies
March 2008 IPC-7095B
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A special note of thanks goes to the following individuals for
their dedication to bringing this project to fruition. Wewould like
to highlight those individuals who made major contributions to the
development of this standard.Dudi Amir, Intel CorporationRaiyomand
Aspandiar, Intel
CorporationScott Buttars, Intel CorporationWerner Engelmaier,
Engelmaier
Associates
Mike Green, Lockheed Martin SpaceSystems
Helen Lowe, CelesticaKaren McConnell, Lockheed Martin
EPICenterRay Prasad, Ray Prasad Consultancy
Group
Robert Rowland, RadiSysVern Solberg, Solberg Technical
ConsultingKris Troxel, Hewlett Packard
Front and back cover photos courtesy of RadiSys Corporation
IPC-7095B March 2008
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Table of Contents
1 SCOPE
......................................................................
11.1 Purpose
.................................................................
11.2 Intent
....................................................................
1
2 APPLICABLE DOCUMENTS .................................... 12.1
IPC
.......................................................................
12.2 JEDEC
..................................................................
1
3 SELECTION CRITERIA AND MANAGINGBGA IMPLEMENTATION
.......................................... 2
3.1 Description of Infrastructure
............................... 33.1.1 Land Patterns and Circuit
Board
Considerations
...................................................... 33.1.2
Technology Comparison ...................................... 53.1.3
Assembly Equipment Impact .............................. 73.1.4
Stencil Requirements ...........................................
73.1.5 Inspection Requirements
..................................... 83.1.6 Test
.......................................................................
83.2 Time-to-Market Readiness ..................................
83.3 Methodology
........................................................ 93.4
Process Step Analysis ..........................................
93.5 BGA Limitations and Issues ...............................
93.5.1 Visual Inspection
................................................. 93.5.2 Moisture
Sensitivity ............................................. 93.5.3
Thermally Unbalanced BGA Design ................ 103.5.4 Rework
...............................................................
103.5.5 Cost
....................................................................
113.5.6 Availability
......................................................... 123.5.7
Voids in BGA .....................................................
123.5.8 Standardization Issues
....................................... 123.5.9 Reliability
Concerns .......................................... 12
4 COMPONENT CONSIDERATIONS ........................ 124.1
Component Packaging Comparisons
and Drivers
......................................................... 124.1.1
Package Feature Comparisons ........................... 124.1.2 BGA
Package Drivers ....................................... 134.1.3
Cost Issues
......................................................... 134.1.4
Component Handling .........................................
134.1.5 Thermal Performance
........................................ 134.1.6 Real Estate
......................................................... 134.1.7
Electrical Performance .......................................
144.2 Die Mounting in the BGA Package .................. 144.2.1
Wire Bond
.......................................................... 144.2.2
Flip Chip
............................................................ 154.3
Standardization ...................................................
16
4.3.1 Industry Standards for BGA ..............................
164.3.2 Ball Pitch
........................................................... 174.3.3
BGA Package Outline ....................................... 184.3.4
Ball Size Relationships ......................................
194.3.5 Coplanarity
......................................................... 194.4
Component Packaging Style Considerations .... 194.4.1 Solder Ball
Alloy ............................................... 204.4.2 Ball
Attach Process ............................................ 204.4.3
Ceramic Ball Grid Array ................................... 214.4.4
Ceramic Column Grid Arrays ........................... 214.4.5 Tape
Ball Grid Arrays ....................................... 224.4.6
Multiple Die Packaging .....................................
224.4.7 System-in-Package (SiP) ...................................
234.4.8 3D Folded Package Technology ........................
234.4.9 Ball Stack, Package-on-Package .......................
234.4.10 Folded and Stacked Packaging Combination ... 244.4.11
Benefits of Multiple Die Packaging .................. 244.5 BGA
Connectors ................................................ 244.5.1
Material Considerations for BGA Connectors .. 244.5.2 Attachment
Considerations for
BGA Connectors ................................................
254.6 BGA Construction Materials .............................
254.6.1 Types of Substrate Materials .............................
254.6.2 Properties of Substrate Materials ......................
264.7 BGA Package Design Considerations ............... 274.7.1
Power and Ground Planes ................................. 274.7.2
Signal Integrity ..................................................
284.7.3 Heat Spreader Incorporation Inside
the Package
........................................................ 284.8 BGA
Package Acceptance Criteria and
Shipping Format ................................................
284.8.1 Missing Balls
..................................................... 284.8.2 Voids
in Solder Balls ......................................... 284.8.3
Solder Ball Attach Integrity .............................. 294.8.4
Package Coplanarity ..........................................
294.8.5 Moisture Sensitivity (Baking, Storage,
Handling, Rebaking) ..........................................
304.8.6 Shipping Medium (Tape and Reel,
Trays, Tubes)
..................................................... 304.8.7
Solder Ball Alloy ...............................................
31
5 PCBS AND OTHER MOUNTING STRUCTURES .. 315.1 Types of Mounting
Structures ........................... 315.1.1 Organic Resin
Systems ...................................... 315.1.2 Inorganic
Structures ........................................... 31
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5.1.3 Layering (Multilayer, Sequentialor Build-Up)
....................................................... 31
5.2 Properties of Mounting Structures ....................
315.2.1 Resin Systems
.................................................... 315.2.2
Reinforcements ..................................................
335.2.3 Laminate Material Properties ............................
335.2.4 Reliability Concerns with High Lead-Free
Soldering Temperatures .....................................
335.2.5 Thermal Expansion
............................................ 335.2.6 Glass
Transition Temperature ............................ 335.2.7
Moisture Absorption ..........................................
345.3 Surface Finishes
................................................. 345.3.1 Hot Air
Solder Leveling (HASL) ..................... 345.3.2 Organic
Surface Protection (Organic
Solderability Preservative) OSP Coatings ........ 375.3.3 Noble
Platings/Coatings .................................... 375.4 Solder
Mask .......................................................
405.4.1 Wet and Dry Film Solder Masks ......................
415.4.2 Photoimageable Solder Masks ..........................
415.4.3 Registration
........................................................ 425.4.4
Via Protection ....................................................
425.5 Thermal Spreader Structure Incorporation
(e.g., Metal Core Boards) ..................................
445.5.1 Lamination Sequences
....................................... 445.5.2 Heat Transfer
Pathway ...................................... 44
6 PRINTED CIRCUIT ASSEMBLYDESIGN CONSIDERATION
.................................... 46
6.1 Component Placement and Clearances ............. 466.1.1
Pick and Place Requirements ............................ 466.1.2
Repair/Rework Requirements ............................ 466.1.3
Global Placement ...............................................
476.1.4 Alignment Legends (Silkscreen, Copper
Features, Pin 1 Identifier) ..................................
476.2 Attachment Sites (Land Patterns and Vias) ...... 486.2.1 Big
vs. Small Land and Impact on Routing ..... 486.2.2 Solder Mask vs.
Metal Defined Land Design .. 486.2.3 Conductor Width
................................................ 506.2.4 Via Size
and Location ....................................... 506.3 Escape
and Conductor Routing Strategies ........ 516.3.1 Escape Strategies
............................................... 536.3.2 Surface
Conductor Details ................................. 546.3.3 Dog
Bone Through Via Details ........................ 546.3.4 Design
for Mechanical Strain ........................... 546.3.5 Uncapped
Via-in-Pad and Impact on
Reliability Issues
................................................ 556.3.6 Fine Pitch
BGA Microvia in Pad Strategies ..... 566.3.7 Power and Ground
Connectivity ....................... 57
6.4 Impact of Wave Solder on Top Side BGAs ..... 576.4.1 Top
Side Reflow ................................................
576.4.2 Impact of Top Side Reflow ...............................
576.4.3 Methods of Avoiding Top Side Reflow ............ 586.4.4
Top Side Reflow for Lead-Free Boards ............ 596.5 Testability
and Test Point Access ...................... 596.5.1 Component
Testing ............................................ 596.5.2 Damage
to the Solder Balls During Test
and Burn-In
........................................................ 606.5.3
Bare Board Testing ............................................
616.5.4 Assembly Testing
............................................... 616.6 Other Design
for Manufacturability Issues ....... 646.6.1 Panel/Subpanel Design
...................................... 646.6.2 In-Process/End
Product Test Coupons .............. 646.7 Thermal Management
........................................ 656.7.1 Conduction
......................................................... 656.7.2
Radiation
............................................................
666.7.3 Convection
......................................................... 676.7.4
Thermal Interface Materials .............................. 676.7.5
Heat Sink Attachment Methods for BGAs ....... 676.8 Documentation
and Electronic Data Transfer ... 696.8.1 Drawing Requirements
...................................... 696.8.2 Equipment Messaging
Protocols ....................... 706.8.3 Specifications
..................................................... 71
7 ASSEMBLY OF BGAS ON PRINTEDCIRCUIT BOARDS
.................................................. 71
7.1 SMT Assembly Processes ..................................
717.1.1 Solder Paste and Its Application .......................
717.1.2 Component Placement Impact ...........................
737.1.3 Vision Systems for Placement ...........................
737.1.4 Reflow Soldering and Profiling .........................
747.1.5 Material Issues
................................................... 787.1.6 Vapor
Phase .......................................................
787.1.7 Cleaning vs. No-Clean
...................................... 797.1.8 Package Standoff
............................................... 797.2 Post-SMT
Processes .......................................... 807.2.1
Conformal Coatings ...........................................
807.2.2 Use of Underfills and Adhesives .......................
817.2.3 Depaneling of Boards and Modules ................. 847.3
Inspection Techniques ........................................
847.3.1 X-Ray Usage
...................................................... 847.3.2
X-Ray Image Acquisition .................................. 857.3.3
Definition and Discussion of X-Ray
System Terminology ..........................................
867.3.4 Analysis of the X-Ray Image ...........................
887.3.5 Scanning Acoustic Microscopy .........................
90
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7.3.6 BGA Standoff Measurement .............................
907.3.7 Optical Inspection
.............................................. 907.3.8 Destructive
Analysis Methods ........................... 927.4 Testing and
Product Verification ....................... 937.4.1 Electrical
Testing ............................................... 937.4.2
Test Coverage ....................................................
947.4.3 Burn-In Testing
.................................................. 947.4.4 Product
Screening Tests .................................... 947.5 Assembly
Process Control Criteria for
Plastic BGAs
...................................................... 947.5.1
Voids
...................................................................
957.5.2 Solder Bridging
................................................ 1067.5.3 Opens
...............................................................
1067.5.4 Cold Solder
...................................................... 1067.5.5
Defect Correlation/Process Improvement ....... 1067.5.6
Insufficient/Uneven Heating ............................ 1077.5.7
Component Defects ......................................... 1077.6
Repair Processes ..............................................
1087.6.1 Rework/Repair Philosophy ..............................
1087.6.2 Removal of BGA
............................................. 1087.6.3 Replacement
..................................................... 109
8 RELIABILITY
......................................................... 1118.1
Accelerated Reliability Testing ........................ 1118.2
Damage Mechanisms and Failure of
Solder Attachments ..........................................
1128.2.1 Comparison of Thermal Fatigue Crack
Growth Mechanism in SAC vs. Tin/Lead BGA Solder Joints
.................................. 113
8.2.2 Mixed Alloy Soldering ....................................
1138.3 Solder Joints and Attachment Types ............... 1158.3.1
Global Expansion Mismatch ........................... 1168.3.2
Local Expansion Mismatch ............................. 1168.3.3
Internal Expansion Mismatch .......................... 1168.4
Solder Attachment Failure ............................... 1168.4.1
Solder Attachment Failure Classification ........ 1168.4.2 Failure
Signature-1: Cold Solder .................... 1178.4.3 Failure
Signature-2: Land, Nonsolderable ..... 1178.4.4 Failure
Signature-3: Ball Drop ....................... 1178.4.5 Failure
Signature-4: Missing Ball .................. 1188.4.6 Failure
Signature-5: Package Warpage ........... 1188.4.7 Failure
Signature-6: Mechanical Failure ........ 1188.4.8 Failure
Signature-7: Insufficient Reflow ......... 1198.5 Critical Factors
to Impact Reliability .............. 1198.5.1 Package Technology
........................................ 1198.5.2 Stand-off Height
............................................... 1208.5.3 PCB Design
Considerations ............................ 121
8.5.4 Reliability of Solder Attachmentsof Ceramic Grid Array
.................................... 121
8.5.5 Lead-Free Soldering of BGAs ........................
1218.6 Design for Reliability (DfR) Process .............. 1278.7
Validation and Qualification Tests .................. 1288.8
Screening Procedures .......................................
1288.8.1 Solder Joint Defects
......................................... 1288.8.2 Screening
Recommendations ........................... 128
9 DEFECT AND FAILURE ANALYSISCASE STUDIES
.................................................... 129
9.1 Solder Mask Defined BGA Conditions ........... 1299.1.1
Solder Mask Defined and Nondefined Lands . 1299.1.2 Solder Mask
Defined Land on
Product Board ..................................................
1299.1.3 Solder Mask Defined BGA Failures ............... 1309.2
Over-Collapse BGA Solder Ball Conditions .. 1309.2.1 BGA Ball Shape
without Heat Slug 500 m
Standoff Height ................................................
1309.2.2 BGA Ball Shape with Heat Slug 375 m
Standoff Height ................................................
1309.2.3 BGA Ball Shape with Heat Slug 300 m
Standoff Height ................................................
1319.2.4 Critical Solder Paste Conditions .....................
1319.2.5 Thicker Paste Deposit
...................................... 1319.2.6 Void Determination
Through X-Ray and
Cross-Section
................................................... 1319.2.7 Voids
and Uneven Solder Balls ...................... 1329.2.8 Eggshell
Void ................................................... 1329.3 BGA
Interposer Bow and Twist ...................... 1329.3.1 BGA
Interposer Warp ...................................... 1339.3.2
Solder Joint Opens Due to Interposer Warp ... 1339.4 Solder Joint
Conditions ................................... 1339.4.1 Target
Solder Condition .................................. 1349.4.2 Solder
Balls With Excessive Oxide ................ 1349.4.3 Evidence of
Dewetting .................................... 1349.4.4 Mottled
Condition ............................................ 1349.4.5
Tin/lead Solder Ball Evaluation ...................... 1359.4.6 SAC
Alloy ........................................................
1359.4.7 Cold Solder Joint
............................................. 1359.4.8 Incomplete
Joining Due to Land
Contamination ..................................................
1359.4.9 Deformed Solder Ball Contamination ............. 1369.4.10
Deformed Solder Ball ......................................
1369.4.11 Insufficient Solder and Flux for Proper
Joint Formation ................................................
1369.4.12 Reduced Termination Contact Area ................
1369.4.13 Excessive Solder Bridging ..............................
1379.4.14 Incomplete Solder Reflow ...............................
137
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9.4.15 Disturbed Solder Joint
..................................... 1379.4.16 Missing Solder
................................................. 137
10 GLOSSARY AND ACRONYMS .......................... 138
11 BIBLIOGRAPHY AND REFERENCES ............... 139
FiguresFigure 3-1 BGA package manufacturing process
.............. 2Figure 3-2 Area array I/O position comparisons
................ 4Figure 3-3 Area array I/O position patterns
....................... 5Figure 3-4 MCM type 2S-L-WB
......................................... 5Figure 3-5 Conductor
width to pitch relationship ............... 7Figure 3-6 Plastic
ball grid array, chip wire bonded .......... 8Figure 3-7 Ball grid
array, flip chip bonded ........................ 8Figure 3-8 BGA
warpage .................................................. 11Figure
4-1 Partial area under the die is used to provide
ground for the die. The rest of the area hasbeen used for signal
routing but has beencovered with solder mask to isolate it fromthe
conductive adhesive under the die. ......... 14
Figure 4-2 Use of glass die to optimize the adhesivedispensing
process for void-free controlledfill and squeeze-out. The picture
on the topshows the adhesive dispense pattern on thedie site. The
picture on the bottom showsthe placed glass die to view voids and
fillingcharacteristics. The adhesive provides full diecoverage for
attachment but partial coverageto ground through a smaller than die
groundpad, allowing a larger portion of the areaunder the die for
signal routing savingvaluable real estate and making theresulting
package smaller. .............................. 15
Figure 4-3 BOC BGA construction
................................... 15Figure 4-4 Top of molded BOC
type BGA ....................... 16Figure 4-5 Flip-chip (bumped
die) on BGA substrate ...... 16Figure 4-6 Plastic ball grid array
(BGA) package ............ 21Figure 4-7 Cross-section of a ceramic
ball grid array
(CBGA) package ............................................
21Figure 4-8 Ceramic ball grid array (CBGA) package ...... 21Figure
4-9 Cross-section of a ceramic column grid
array (CCGA) package ...................................
21Figure 4-10 Polyimide film based lead-bond BGA
package substrate furnishes close couplingbetween die pad and
ball contact .................. 22
Figure 4-11 Comparing in-package circuit routingcapability of
the single metal layer tapesubstrate to two metal layer tape
substrate ... 22
Figure 4-12 Single package die-stack BGA .......................
23Figure 4-13 Custom eight die (flip-chip and wire-bond)
SiP assembly ..................................................
23Figure 4-14 Folded multiple-die BGA package ..................
23Figure 4-15 Package-on-package FBGA ...........................
24Figure 4-16 SO-DIMM memory card assembly .................
24Figure 4-17 Folded and stacked multiple die
BGA package ..................................................
24
Figure 4-18 BGA connector
............................................... 25Figure 4-19
Example of missing balls on a BGA
component ......................................................
28Figure 4-20 Example of voids in eutectic solder balls at
incoming inspection ........................................
29Figure 4-21 Examples of solder ball/land surface
conditions
........................................................ 29Figure
4-22 Establishing BGA coplanarity requirement ..... 30Figure 4-23
Ball contact positional tolerance ..................... 30Figure
5-1 Examples of different build-up constructions . 32Figure 5-2
Expansion rate above Tg ................................ 34Figure
5-3 Hot air solder level (HASL) surface topology
comparison .....................................................
36Figure 5-4 Black pad related fracture showing crack
between Nickel & Ni-Sn intermetallic layer .... 38Figure 5-5
Crack location for a) black pad related failure
and (b) interfacial fracture when using ENIGsurface finish
.................................................. 38
Figure 5-6 Typical mud crack appearance of black padSurface
........................................................... 39
Figure 5-7 A large region of severe black pad withcorrosion
spikes protruding into nickelrich layer through phosphorus rich
layerunderneath immersion gold surface ............... 39
Figure 5-8 Graphic depiction of electroless nickel,electroless
palladium/immersion gold ............ 40
Figure 5-9 Graphic depiction of directed immersiongold
.................................................................
40
Figure 5-10 Work and turn panel layout
............................ 43Figure 5-11 Distance from tented
land clearance ............. 43Figure 5-12 Via plug methods
............................................ 45Figure 5-13 Solder
filled and tented via blow-out .............. 46Figure 5-14 Metal
core board construction examples ....... 46Figure 6-1 BGA alignment
marks ..................................... 47Figure 6-2 Solder
lands for BGA components ................. 49Figure 6-3 Metal
defined land attachment profile ............ 49Figure 6-4 Solder
mask stress concentration .................. 49Figure 6-5 Solder
joint geometry contrast ....................... 49Figure 6-6
Good/bad solder mask design ....................... 50Figure 6-7
Examples of metal-defined land ..................... 50Figure 6-8
Quadrant dog bone BGA pattern ................... 51Figure 6-9
Square array ...................................................
52Figure 6-10 Rectangular array
........................................... 52Figure 6-11
Depopulated array ..........................................
52Figure 6-12 Square array with missing balls .....................
52Figure 6-13 Interspersed array
.......................................... 53Figure 6-14 Conductor
routing strategy ............................. 53Figure 6-15 BGA
dogbone land pattern preferred
direction for conductor routing ........................
55Figure 6-16 Preferred screw and support placement ........
55Figure 6-17 Connector screw support placement ..............
55Figure 6-18 Cross section of 0.75 mm ball with via-in-
pad structure (Indent to the upper left ofthe ball is
anartifact.) ...................................... 55
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Figure 6-19 Cross section of via-in-pad design showingvia cap
and solder ball ................................... 55
Figure 6-20 Via-in-pad process descriptions
..................... 56Figure 6-21 Microvia example
............................................ 56Figure 6-22 Microvia
in pad voiding ................................... 57Figure 6-23
Ground or power BGA connection ................. 57Figure 6-24
Example of top side reflow joints ................... 57Figure 6-25
Example of wave solder temperature profile
of top-aide of mixed component assembly .... 58Figure 6-26 Heat
pathways to BGA solder joint during
wave soldering ................................................
58Figure 6-27 Methods of avoiding BGA topside solder
joint reflow
...................................................... 59Figure
6-28 An example of a side contact made with a
tweezers type contact .....................................
60Figure 6-29 Pogo-pin type electrical contact impressions
on the bottom of a solder ball ........................ 60Figure
6-30 Area array land pattern testing .......................
62Figure 6-31 Board panelization
.......................................... 65Figure 6-32 Comb
pattern examples ................................. 66Figure 6-33
Heat sink attached to a BGA with
an adhesive ....................................................
68Figure 6-34 Heat sink attached to a BGA with a clip
that hooks onto the component substrate ...... 68Figure 6-35
Heat sink attached to a BGA with a clip
that hooks into a through-hole on theprinted circuit board
........................................ 68
Figure 6-36 Heat sink attached to a BGA with a clip thathooks
onto a stake soldered in the printedcircuit board
.................................................... 69
Figure 6-37 Heat sink attached to a BGA by wavesoldering its
pins in a through-hole inthe printed circuit board
.................................. 69
Figure 7-1 Aspect and area ratios for complete pasterelease
............................................................ 72
Figure 7-2 High lead and eutectic solder ball and
jointcomparison
..................................................... 73
Figure 7-3 Example of peak reflow temperatures atvarious
locations at or near a BGA ................ 74
Figure 7-4 Schematic of reflow profile for tin/leadassemblies
...................................................... 75
Figure 7-5 An example of tin/lead profile with
multiplethermocouples
................................................ 76
Figure 7-6 Schematic of reflow profile for lead-freeassemblies
...................................................... 76
Figure 7-7 Examples of lead-free profiles with soak(top) and
ramp to peak (bottom) withmultiple thermocouples. The profileswith
soak tend to reduce voids in BGAs. ....... 76
Figure 7-8 Locations of thermocouples on a boardwith large and
small components ................... 77
Figure 7-9 Recommended locations of thermocoupleson a BGA
........................................................ 77
Figure 7-10 Effect of having solder mask relief aroundthe BGA
lands of the board ............................ 80
Figure 7-11 Flow of underfill between two parallelsurfaces
.......................................................... 82
Figure 7-12 Examples of underfill voids - small, mediumand
large; upper left, lower left and left ofsolder balls, respectively
................................ 82
Figure 7-13 Example of partial underfill - package waspulled
from the PCB and dark underfill canbe seen in the corners
................................... 82
Figure 7-14 Corner applied adhesive
................................ 83Figure 7-15 Critical dimension
for application of
prereflow corner glue ......................................
83Figure 7-16 Typical corner glue failure mode in shock
if glue area is too low - Solder mask ripsoff board and does not
protect the solderjoints
...............................................................
83
Figure 7-17 Fundamentals of X-ray technology ................
85Figure 7-18 X-ray example of missing solder balls ...........
85Figure 7-19 X-ray example of voiding in solder ball
contacts
.......................................................... 85Figure
7-20 Manual X-ray system image quality ............... 86Figure
7-21 Example of X-ray pin cushion distortion
and voltage blooming .....................................
86Figure 7-22 Transmission image (2D)
............................... 86Figure 7-23 Tomosynthesis image
(3D) ............................. 87Figure 7-24 Laminographic
cross-section image (3D) ....... 87Figure 7-25 Transmission example
.................................... 87Figure 7-26 Oblique viewing
board tilt ............................... 88Figure 7-27 Oblique
viewing detector tilt ........................... 88Figure 7-28 Top
down view of FBGA solder joints ............ 88Figure 7-29 Oblique
view of FBGA solder joints ............... 88Figure 7-30
Tomosynthesis ................................................
89Figure 7-31 Scanned beam X-ray laminography ...............
89Figure 7-32 Scanning acoustic microscopy .......................
91Figure 7-33 Endoscope example
....................................... 91Figure 7-34 Lead-free
1.27 mm pitch BGA reflowed
in nitrogen and washed between SMTpasses
............................................................ 91
Figure 7-35 Lead-free BGA reflowed in air and washedbetween SMT
passes ..................................... 92
Figure 7-36 Engineering crack evaluation technique ........
93Figure 7-37 A solder ball cross sectioned through a
void in the solder ball .....................................
93Figure 7-38 Cross-section of a crack initiation at the
ball/pad interface ............................................
93Figure 7-39 No dye penetration under the ball ..................
94Figure 7-40 Corner balls have 80-100% dye penetration
which indicate a crack ....................................
94Figure 7-41 Small voids clustered in mass at the ball-to-
land interface
.................................................. 96Figure 7-42
X-ray image of solder balls with voids at
50 kV (a) and 60 kV (b) .................................
97Figure 7-43 Typical size and location of various types
of voids in a BGA solder joint .........................
98Figure 7-44 Example of voided area at land and board
Interface
.......................................................... 98Figure
7-45 Typical flow diagram for void assessment ... 100
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Figure 7-46 Voids in BGAs with crack started atcorner lead
.................................................... 104
Figure 7-47 Examples of suggested void protocols ........
104Figure 7-48 Void diameter related to land size ................
105Figure 7-49 X-ray image showing uneven heating ..........
107Figure 7-50 X-ray image at 45 showing insufficient
heating in one corner of the BGA ................ 107Figure 7-51
X-ray image of popcorning ........................... 108Figure
7-52 X-ray image showing warpage in a BGA ..... 108Figure 7-53
BGA/assembly shielding examples .............. 109Figure 8-1 BGA
solder joint of eutectic tin/lead solder
composition exhibiting lead rich (dark)phase and tin rich
(light) phase grains ......... 113
Figure 8-2 Socket BGA solder joints of SnAgCucomposition,
showing the solder jointcomprised of 6 grains (top photo) anda
single grain (bottom photo). ....................... 113
Figure 8-3 Thermal-fatigue crack propagation ineutectic tin/lead
solder joints in a CBGAmodule
.......................................................... 114
Figure 8-4 Thermal-fatigue crack propagationin Sn-3.8Ag-0.7Cu
joints in a CBGAmodule [3]
..................................................... 114
Figure 8-5 Incomplete solder joint formation for 1%Ag ball alloy
assembled at low end oftypical process window
................................. 115
Figure 8-6 Solder joint failure due to silicon andboard CTE
mismatch .................................... 116
Figure 8-7 Grainy appearing solder joint
........................ 117Figure 8-8 Nonsolderable land (black
pad) .................... 117Figure 8-9 Land contamination (solder
mask residue) .. 117Figure 8-10 Solder ball down
........................................... 117Figure 8-11 Missing
solder ball ........................................ 118Figure 8-12
Deformed solder joint due to BGA warping .. 118Figure 8-13 Two
examples of pad cratering (located at
corner of BGA) ..............................................
118Figure 8-14 Pad crater under 1.0 mm pitch lead-free
solder ball. Crack in metal trace connectedto the land is clear;
however, the pad crateris difficult to see in bright field
microscopy. .. 119
Figure 8-15A Insufficient reflow temperature
...................... 119Figure 8-15B Cross-section photographs
illustrating
insufficient melting of solder joints duringreflow soldering.
These solder joints arelocated below the cam of a socket.
............. 120
Figure 8-16 Solder mask influence
.................................. 121Figure 8-17 Reliability test
failure due to very
large void
...................................................... 121Figure
8-18 Comparison of a lead-free (SnAgCu)
and tin/lead (SnPb) BGA reflow solderingprofiles
.......................................................... 125
Figure 8-19 Endoscope photo of a SnAgCu BGAsolder ball
..................................................... 125
Figure 8-20 Comparison of reflow soldering profiles fortin/lead,
backward compatibility and totallead-free board assemblies
.......................... 126
Figure 8-21 Micrograph of a cross-section of a BGASnAgCu solder
ball, assembled onto a boardwith tin/lead solder paste using the
standardtin/lead reflow soldering profile. The SnAgCusolder ball
does not melt; black/greyinterconnecting fingers are lead-rich
grainboundaries; rod shape particles are Ag3SnIMCs; grey particles
are Cu6Sn5 IMCs. ...... 126
Figure 8-22 Micrograph of a cross-section of a BGASnAgCu solder
ball, assembled onto a boardwith tin/lead solder paste using a
backwardcompatibility reflows soldering profile. TheSnAgCu solder
ball has melted. ................... 127
Tables
Table 3-1 Multichip module definitions
................................ 5Table 3-2 Number of escapes vs.
array size on two
layers of circuitry
................................................. 6Table 3-3
Potential plating or component termination
material properties ............................................
10Table 3-4 Semiconductor cost predictions ........................
11Table 4-1 JEDEC Standard JEP95-1/5 allowable ball
diameter variations for FBGA ............................
17Table 4-2 Ball diameter sizes for PBGAs .........................
18Table 4-3 Future ball size diameters for PBGAs ..............
18Table 4-4 Land size approximation
................................... 18Table 4-5 Future land size
approximation ......................... 18Table 4-6 Land-to-ball
calculations for current and
future BGA packages (mm) .............................. 19Table
4-7 Examples of JEDEC registered BGA
outlines
..............................................................
19Table 4-8 IPC-4101B FR-4 property summaries -
specification sheets projected to betterwithstand lead-free
assembly ........................... 26
Table 4-9 Typical properties of common dielectricmaterials for
BGA package substrates ............. 27
Table 4-10 Moisture classification level and floor life
......... 30Table 5-1 Environmental properties of common
dielectric materials
............................................ 32Table 5-2 Key
attributes for various board surface
finishes
..............................................................
35Table 5-3 Via filling/encroachment to surface finish
process evaluation ............................................
44Table 5-4 Via fill options
.................................................... 46Table 6-1
Number of conductors between solder lands
for 1.27 mm pitch BGAs ...................................
48Table 6-2 Number of conductors between solder lands
for 1.0 mm pitch BGAs .....................................
48Table 6-3 Maximum solder land to pitch relationship .......
48Table 6-4 Escape strategies for full arrays
....................... 53Table 6-5 Conductor routing - 1.27 mm
Pitch ................... 54Table 6-6 Conductor routing - 1.0 mm
Pitch ..................... 54Table 6-7 Conductor routing - 0.8 mm
Pitch ..................... 54Table 6-8 Conductor routing - 1.27 mm
Pitch ................... 54Table 6-9 Conductor routing - 1.0 mm
Pitch ..................... 54
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Table 6-10 Conductor routing - 0.8 mm Pitch
..................... 54Table 6-11 Effects of material type on
conduction ............. 66Table 6-12 Emissivity ratings for
certain materials ............. 66Table 7-1 Particle size
comparisons ................................. 72Table 7-2 Solder
paste volume requirements for
ceramic array packages ....................................
73Table 7-3 Profile comparison between SnPb and
SAC alloys
......................................................... 75Table
7-4 Inspection usage application
recommendations ..............................................
84Table 7-5 Field of view for inspection
............................... 90Table 7-6 Void classification
.............................................. 97Table 7-7
Corrective action indicator for lands used
with 1.5, 1.27 or 1.0 mm pitch ........................ 101Table
7-8 Corrective action indicator for lands used
with 0.8, 0.65 or 0.5 mm pitch ........................ 102Table
7-9 Corrective action indicator for microvia in
pad lands used with 0.5, 0.4 or 0.3 mmpitch
.................................................................
103
Table 7-10 Ball-to-void size image - comparison forvarious ball
diameters ..................................... 104
Table 7-11 C=0 sampling plan (sample size for specificindex
value*) ................................................... 106
Table 7-12 Repair process temperature profiles for tinlead
assembly .................................................. 111
Table 7-13 Repair process temperature profiles forlead-free
assemblies ........................................ 111
Table 8-1 Accelerated testing for end useenvironments
................................................... 112
Table 8-2 Tin/lead component compatibility with lead-free reflow
soldering ........................................ 114
Table 8-3 Typical stand-off heights for tin/leadballs (in mm)
................................................... 120
Table 8-4 Common solders, their melting points,advantages and
drawbacks ............................ 123
Table 8-5 Comparison of lead-free solder alloycompositions in
the Sn-Ag-Cu familyselection by various consortia
......................... 123
Table 8-6 Types of lead-free assemblies possible ..........
125
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Design and Assembly Process Implementation for BGAs
1 SCOPE
This document describes the design and assembly chal-lenges for
implementing Ball Grid Array (BGA) and FinePitch BGA (FBGA)
technology. The effect of BGA andFBGA on current technology and
component types areaddressed, as is the move to lead-free assembly
processes.The focus on the information contained herein is on
criti-cal inspection, repair, and reliability issues associated
withBGAs. Throughout this document the word BGA canmean all types
and forms of ball/column grid array pack-ages.
1.1 Purpose The target audiences for this document aremanagers,
design and process engineers, and operators andtechnicians who deal
with the electronic assembly, inspec-tion, and repair processes.
The intent is to provide usefuland practical information to those
who are using BGAs,those who are considering BGA implementation and
com-panies who are in the process of transition from the stan-dard
tin/lead reflow processes to those that use lead-freematerials in
the assembly of BGA type components.
1.2 Intent The new challenge in implementing BGAassembly
processes, along with other types of components,is the need to meet
the legislative directives that declarecertain materials as
hazardous to the environment. Therequirements to eliminate these
materials from electroniccomponents have caused component
manufacturers torethink the materials used for encapsulation, the
platingfinishes on the components and the metal alloys used in
theassembly attachment process.
This document, although not a complete recipe, identifiesmany of
the characteristics that influence the successfulimplementation of
a robust assembly process. In manyapplications, the variation
between assembly methods andmaterials is reviewed with the intent
to highlight significantdifferences that relate to the quality and
reliability of thefinal product. The accept/reject criteria for BGA
assem-blies, used in contractual agreements, is established
byJ-STD-001 and IPC-A-610.
2 APPLICABLE DOCUMENTS
2.1 IPC1
J-STD-001 Requirements for Soldered Electrical and Elec-tronic
Assemblies
J-STD-020 Handling Requirements for Moisture
SensitiveComponents
J-STD-033 Standard for Handling, Packing, Shipping andUse of
Moisture/Reflow Sensitive Surface Mount Devices
IPC-T-50 Terms and Definitions for Printed Boards andPrinted
Board Assemblies
IPC-D-279 Design Guidelines for Reliable Surface MountTechnology
Printed Board Assemblies
IPC-D-325 Documentation Requirements for PrintedBoards
IPC-D-350 Printed Board Description in Digital Form
IPC-D-356 Bare Substrate Electrical Test Information inDigital
Form
IPC-SM-785 Guidelines for Accelerated Reliability Testingof
Surface Mount Attachments
IPC-2221 Generic Standard on Printed Board Design
IPC-2511 Generic Requirements for Implementation ofProduct
Manufacturing Description Data and Transfer
IPC-2581 Generic Requirements for Printed Board Assem-bly
Products Manufacturing Description Data and TransferMethodology
IPC-7094 Design and Assembly Process Implementationfor Flip Chip
and Die Size Components
IPC-7351 Generic Requirements for Surface MountDesign and Land
Pattern Standard
IPC-7525 Stencil Design Guidelines
IPC-7711/7721 Rework, Modification and Repair of Elec-tronic
Assemblies
IPC-9701 Performance Test Methods and QualificationRequirements
for Surface Mount Solder Attachments
IPC/JEDEC-9704 Printed Wiring Board Strain Gage
TestGuideline
2.2 JEDEC2
JEP95 Section 4.5 Fine Pitch (Square) Ball Grid ArrayPackage
(FBGA)
1. www.ipc.org2. www.jedec.org
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JEP95 Section 4.6 Fine Pitch (Rectangular) Ball GridArray
Package (FRBGA)JEP95 Section 4.7 Die-Size Ball Grid Array
Package(DSBGA)JEP95 Section 4.9 Generic Matrix Tray for Handling
andShipping (Low Stacking Profile for BGA Packages)JEP95 Section
4.10 Generic Matrix Tray for Handling andShipping
JEP95 Section 4.14 Ball Grid Array Package (BGA)JEP95 Section
4.17 Ball Grid Array (BGA) Package Mea-surement and Methodology
JEP95 Section 4.22 Fine Pitch Square Ball Grid ArrayPackage
(FBGA) Package on Package (PoP)JESD22-A102 Unbiased Autoclave Test
Method
JESD22-A103 High Temperature Storage Test Method
JESD22-A104 Thermal Shock Test Method
JESD22-A118 Accelerated Moisture Resistance-UnbiasedHAST
JESD22-B103 Board-Level Vibration Test Method
JESD22-B110 Subassembly Mechanical Shock TestMethod
JESD22-B111 Board-Level Drop Test Method
3 SELECTION CRITERIA AND MANAGING BGA IMPLE-MENTATION
Every electronic system consists of various parts: inter-faces,
electronic storage media, and the printed boardassembly. Typically,
the complexity of these systems isreflected in both the type of
components used and theirinterconnecting structure. The more
complex the compo-nents, as judged by the amount of input/output
terminalsthey possess, the more complex is the interconnecting
sub-strate. Cost and performance drivers have resulted inincreased
component density, and a greater number ofcomponents attached to a
single assembly, while the avail-able mounting real estate has
shrunk. In addition, the num-ber of functions per device has
increased and this is accom-modated by using increased I/O count
and reduced contactpitch. Reduced contact pitch represents
challenges for bothassemblers and bare board manufacturers.
Assemblersencounter handling, coplanarity and alignment
problems.
Component packaging in general, microprocessor andmemory
packages in particular, drive the rest of the elec-tronic assembly
packaging issues. Figure 3-1 shows anexample of the package
manufacturing process. The driv-ing forces for component packaging
are thermal and elec-trical performance, real estate constraints
and cost. Periph-eral devices with 1.27 mm pitch have
becomecommonplace in the industry. However, this package can-not
accommodate higher than 84 pins. Larger peripheralpin count devices
require lead pitches of 0.65 mm, 0.5 mmor 0.3 mm.
Die AttachKnown Good
Die
Start Wire Bond Mold Package
Chip Attachusing Flip Chip Process Underfill Die
Print Fluxor Pasteon GBA
Substrate Lands
Place Balls on BGA
Substrate Lands
Perform Electrical
TestInspect Pack Ship
Ball AttachReflow Balls on
BGA Substrate Lands
IPC-7095B-3-1
Figure 3-1 BGA package manufacturing process
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Although pitches below 1.27 mm are useful for reducingpackage
size, the increased density presents manyproblems for most
manufacturers. At these fine-pitches,leads are very fragile and
susceptible to damage such aslead coplanarity, lead bending and
sweep. To place thesepackages, a pick-and-place machine with vision
system andwaffle pack handlers is necessary. These two features,
how-ever, can add substantial capital equipment costs.
Design guidelines must change to allow added interpack-age
spacing between the fine-pitch devices and neighboringconventional
packages. With the exception of no-cleanfluxes, cleaning problems
arise with fine-pitch deviceswhich sit almost flush (0 to 250 m) to
the board. Forproper cleaning, a 0.4 mm to 0.5 mm standoff is
recom-mended, with the need to meet this requirement based onthe
size of the BGA package, since smaller profiles alloweasier
penetration of the cleaning solutions. Using a tempo-rary solder
mask over the vias under a package avoids fluxentrapment problems.
However, this extra process stepincreases production cost.
Since BGAs use solder bump interconnections instead ofleads,
problems associated with lead damage and coplanar-ity are
eliminated. BGA pitches from 1.27 mm to 1.5 mm,have well over 250 m
of standoff height, so problems withpaste printing, placement,
reflow and cleaning are signifi-cantly reduced. BGAs also provide
much shorter signalpaths compared to fine-pitch devices. Shorter
signal pathscan be very critical in high-speed applications.
3.1 Description of Infrastructure The use of BGAs inthe design
through assembly processes has become com-mon place in the last few
years. Nevertheless, incorporat-ing these parts into electronic
assemblies requires dedicatedengineering resources to develop,
implement and integratethe processes into the assembly operation.
Even thoughBGAs can leverage existing SMT infrastructure, there
aremany technical considerations that must be addressed inorder to
be successful in implementing BGA componentsinto existing product
configurations.
3.1.1 Land Patterns and Circuit Board Considerations
Components are soldered to the printed board on the sur-face
mount lands. Lands are areas of copper approximatelythe shape and
size of the lead or termination footprint. Theland pattern design
is critical for manufacturability,because it affects the solder
defect rate, cleanability, test-ability, repair/rework and the
solder joints reliability. Inthe past, component tolerances were
too liberal (some stillare) for effectively designing land
patterns. Additionally,since surface mount packages were not
standardized, landpattern design could not be standardized. As a
result, usershad to develop in-house land pattern dimensions
andqualify a limited number of suppliers who met those
speci-fications. Reducing the number of suppliers reduced the
range of sizes and associated tolerances required of landpattern
design.Land pattern design issues for BGA need to be
understood.This is essential to assure proper solder joint
formation andprevent defects such as bridging, opens and to achieve
opti-mal reliability. In addition to land design, one should
alsokeep in mind that the inner rows of BGA pins require
addi-tional layers for interconnection. Increasing the number
ofpins (vias) drives layer count due to the reduction of rout-ing
channels. Higher layer count means higher cost of thebare board.BGA
lands can be solder mask defined (solder mask over-laps the land)
or copper defined (solder mask stays awayfrom the land). There are
pros and cons of each approachbut the copper defined lands are more
reliable.The board manufacturers must deal with land size
issues,compatible surface finishes, solder mask resolution
andelectrical test problems. The assembler must deal with
theassembly process parameters and make a decision as to thesolder
paste properties, wave solder materials and the pro-cess profiles
for attachment of a variety of component andboard finishes.Based on
industry predictions one would believe that allcomponent packages
have over 200 I/Os and are increasingin I/O count. Actually,
components with the highest usagehave I/O counts in the 16 to 64
I/O range. Over 50% of allcomponents fall into this category, while
only 5% of allcomponents used have over 208 I/Os, which may be
thethreshold for determining the cross-over point betweenperipheral
leaded component style packages and array typeformats.Many
peripherally leaded, lower I/O count devices, such asmemory and
logic devices, are being converted to areaarray packaging formats
as either BGAs or fine pitchBGAs.Although the percentage of high
I/O components used onan electronic assembly is small, they play a
big part indriving the industry infrastructure for both bare board
andassembly manufacturing. These high I/O componentsdetermine the
process for bare board imaging, etching, test-ing and surface
finishing. They determine the materialsused for fabrication and
drive assembly process improve-ments in a similar manner.The
electronics industry has evolved from using throughhole assembly
technology in which the component leadswent into the printed board
substrate and were either sol-dered to the bottom side of the board
or into a plated-through hole. Surface mounting technology (SMT)
hasadvanced to a stage where the majority of electronic com-ponents
manufactured today are only available in SMTform.Manufacturing
products with SMT in any significant vol-ume requires automation.
For low volume, a manually
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operated machine or a single placement machine may besufficient.
High volume SMT manufacturing requires spe-cial solder paste
deposition systems, multiple and variousplacement machines, in-line
solder reflow systems andcleaning systems.
The heart of surface mount manufacturing is the machinethat
places the components onto the printed board landareas prior to
soldering. Unlike through-hole (TH) insertionmachines, surface
mount placement machines are usuallycapable of placing many
different component types. Asdesign densities have increased, new
SMT package styleshave evolved. Examples are fine pitch technology
(FPT),ultra fine pitch technology (UFPT), and array surfacemount
(ASM). This latter category consists of the manyfamilies of ball or
column grid arrays, chip scale packages(CSP), fine pitch BGAs
(FBGA), and flip chip (FC) appli-cations. These parts are all
capable of being placed bymachines provided that the equipment has
the requiredpositioning accuracy.
Increased device complexity has been a primary drivingfactor for
SMT. In order to minimize the component pack-age size, component
lead spacing has decreased (e.g.,1.27 mm to 0.65 mm). Further
increases in semiconductorintegration requiring more than 196 I/Os
can drive pack-ages to even closer perimeter lead spacing, such as
0.5, 0.4,0.3, and 0.25 mm. However, the array package format
hasbecome the favorite for high I/O count devices. Area
arraycomponent package styles have a pitch that originally wasmuch
larger than the equivalent peripherally leaded device,however that
lead format is now also seeing reductions inpitch
configurations.
Ball and column grid arrays were standardized in 1992with 1.5,
1.27 and 1.0 mm pitch. Fine pitch BGA array
packages standards have established pitches of 1.0, 0.8,0.75,
0.65, and 0.5 mm. There are some implementations ofFBGAs where the
pitch has been reduced to 0.4 mm, andfuture components are being
evaluated with 0.3 and0.25 mm pitch configurations. Although
standard configu-rations for BGAs and their associated land
patterns exist, asdescribed in IPC-7351, some component
manufacturershave modified the standard configurations in order
toimprove the interconnection capability in the componentsubstrate.
The tailoring of the standard geometries makes itimportant to check
the manufacturers data sheet to deter-mine the exact
characteristics of the pitch, ball size anddepopulation (removed
balls).There is a question as to how many lead pitches arerequired
between 1.0 mm and 0.5 mm. Some indicate thata 60% rule is of value
where the ball diameter is 60% ofthe pitch. This results in a 0.5
mm ball diameter for a0.8 mm pitch. FBGAs would use a 0.4 mm ball
diameterfor a 0.65 mm pitch. On the other hand, some feel that
itwould be better to standardize a 0.3 mm diameter ball forall FBGA
packages. Standardization of a single ball sizewould facilitate
many characteristics. The motive is toaccommodate conductor routing
on the interconnectingsubstrate and help standardize socket pin
contact design.
Area array packaging has the intrinsic value of being ableto
make coherent designs. This is exemplified on the rightside of
Figure 3-2, where a single pitch might be depopu-lated to meet the
requirements of the design. The trendillustrated on the left side
of Figure 3-2 forces the creationof many different test sockets.
Interconnection of the partIOs is affected both by ball pitch and
ball diameter. Thestandard ball diameter as specified by the US
JEDEC JC11Committee alleviates pressure on the substrate
design.
Figure 3-2 Area array I/O position comparisons
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The selection process for an electronic assembly shouldattempt
to minimize the variation in component packagetypes and the I/O
pitch condition. The large I/O countdevices and problems with
assembly of finer pitch periph-eral packages has caused rethinking
of the packaging stylevs. the assembly complexity relationship, and
the printedboard interconnection and surface characteristics.
The concern in using these very complex parts relates toboard
design and assembly issues. Assembly is concernedabout attaching
all the leads to the mounting structure with-out bridging (shorts)
or missing solder joints (opens).Design is concerned with
interconnecting all the leads andhaving sufficient room for routing
conductors.
Array packages permit a variety of ball configurations,
i.e.,staggered positions or partially populated parts, to
providethe room required for adequate conductor routing. With
acommon base array pitch significant advantages can begained in
terms of providing a coherent standard for all ofthe elements of
the electronic manufacturing infrastructurefor components, sockets,
substrates and test systems (seeFigure 3-3).
3.1.2 Technology Comparison The principles used tomount a single
chip into an organic carrier package can
also be used to connect several chips together. This tech-nique
is referred to as a multichip module-laminate(MCM-L) or a multichip
package (MCP) or the new nameassigned to complex module assemblies
known as multidevice subassembly (MDS). In all the variations that
arebeing developed the one governing condition is the use ofthe
area array format. Thus, ball size and pitch will con-tinue to be
the process governing factor for individual com-ponents or those
that encompass more than one semicon-ductor die. Table 3-1 shows
some examples of an attemptto establish a definition for Multichip
modules housingmore than one die. Figure 3-4 is an example of one
suchproduct using the area array concepts for interconnection.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 126 24 22 20 18 16 14 12 10 8
6 4 2
25 23 21 19 17 15 13 11 9 7 5 3 1
ABCDEFGHJKLMNPRTUVWYAAABACADAEAF
P
P
P P
PIN #1CORNER
PIN #1CORNER
ABCDEFGH
JKL
MNOP
IPC-7095b-3-3
Figure 3-3 Area array I/O position patterns
Table 3-1 Multichip module definitionsMCM Technology Description
Attributes
Type 1 Common Technology Package Multiple same type chips, in
plane.Type 1S Common Technology Package Multiple same type chips,
stacked.Type 1F Common Technology Package Multiple same type chips,
folded.Type 2 Mixed Technology Package Mixed IC technology package,
in plane.Type 2S Mixed Technology Package Mixed IC technology
package, stacked.Type 2F Mixed Technology Package Mixed IC
technology package, folded.Type 3 System in Package Mixed ICs and
discrete devices, in plane.Type 3S System in Package Mixed ICs and
discrete devices, stacked.Type 4 Optoelectronic System Package
Mixed technology for optoelectronics.
IPC-7095b-3-4
Figure 3-4 MCM type 2S-L-WB
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Possible other descriptive attributes include substrate
tech-nology (e.g., -C for ceramic, -L for laminate, -D for
depos-ited, -W for wafer, -S for silicon) & interconnection
tech-nology (e.g., -WB for wire bond, -FC for flip chip, -MX
formixed).Microprocessors typically have between 40-60% of theirI/O
dedicated to power and ground. As an example, a pack-age might have
a total of 1300-1400 I/O where the signalcount is between 600 and
700 I/O. Applications SpecificICs (ASICs) may differ in that I/O
apportionment.The signal I/O escape wiring, and their
interconnection toother high I/O packages, will also require very
high densityprinted boards (HDBs). As the number of I/O on a
chipincreases further, the body size of the single chip packagemay
become unacceptably large, and could require reas-sessment of the
overall package solution, including consid-ering multichip module
packaging or application specificmodule packaging (ASMP) as an
alternative. The signalI/O count for high performance BGAs is about
2.5X thatcommonly required for BGAs used in hand held products.The
interconnection density requirement is linearly propor-tional to
the number of signal I/O per package, andinversely proportional to
the center-to-center pitch betweenadjacent packages. A 2.5X
increase in signal I/O from 500to 1300 pins per package at the same
package-to-packagepitch will require a printed board with a 2.5X
increase inits wiring density, and a proportional increase in the
den-sity of the interlevel vias or Plated-Through Holes (PTHs).This
may require a reduction in the PTH/via pitch, and anincrease in the
number of signal layers in the printed board.
With more of the circuit customization going into siliconand
with the component package size increasing, theprinted board design
will need to change. The higher I/Odemand will require multilayer
or high-density intercon-nection (microvia) designs to support the
required wiringand to provide escape routing from the internal
connectionsof array component patterns to the printed board.
Bothsides of the printed board may be required to place all
thecomponents required by the design. There will also be
anincreased demand on the printed board to handle therequired power
dissipation.
Using high I/O components like BGAs and fine pitchBGAs creates
the challenge of routing all the required sig-nal, power, and
ground I/O balls to the printed board with-out increasing board
complexity and, therefore, cost.Thoughtful package pin assignments
and the package con-figuration considerations (pitch, ball size,
ball count, anddepopulation) can go a long way in making the board
rout-ing easier.
Two interconnection signal layers can be sufficient forBGA
package escape, even when the BGA has very highball counts,
providing the pin assignments are properlyplanned and the escape
routing is carefully designed. Table
3-2 indicates the number of escapes possible on twolayers of
circuitry vs. the array size and the number ofconductors between
lands/vias. It should be noted that, asthe number of I/O increases,
the ability to escape dimin-ishes and thus more layers may be
required. At first glance,Table 3-2 might appear to indicate that
two routing layersare insufficient to escape any array greater than
16 x 16(256 balls). In reality, a significant number of the balls
willbe used for power and ground connections and therefore donot
need escape routing. They can be directly connectedto the
appropriate plane through the dogbone via attachedto the land. That
being said, poor placement of the signalor power/ground balls can
waste available routing chan-nels and significantly reduce the
total number of signalI/Os that can be routed out in a given number
of layers.
Placing signal pin assignments on the outer rows of anarray
package, and using the inner balls for power andground will
facilitate escape routing. However, the cornerballs of large array
packages are more susceptible tomechanical failure, and therefore
it may be better to usethese for redundant ground connections. The
number ofrows of signal I/O that can be routed out will depend on
thedesired number of conductor routing layers in the printedboard
and the number of conductors that can be routedbetween lands and
vias.
Figure 3-5 shows examples of conductor and space widthsthat will
fit between adjacent lands with various pitchesand land diameters.
Note that as the ball pitch decreases,the conductor width and
spacing for a given number ofconductors per channel also decreases,
and it becomesmore difficult and costly to produce the board.
Using 150 m conductors and spaces is quite cost effective,but
printed board cost begins to increase significantly for100 m
conductors and spaces. Using an organic intercon-necting substrate
to mount the bare die within a plasticBGA requires that the
mounting lands on the substratematch the bonding lands on the
die.
The bonding lands are typically positioned for wire bond-ing,
since this is the most popular technique. Thermally
Table 3-2 Number of escapes vs.array size on two layers of
circuitry
Array SizeTotal
Leads
Number of ConductorsBetween Vias (|)
1 2 3| || |||
14 X 14 196 192 196 19616 X 16 256 236 256 25619 X 19 361 272
316 35221 X 21 441 304 356 40025 X 25 625 368 436 49631 X 31 961
464 556 64035 X 35 1225 528 638 736
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conductive adhesive is one of the methods used to attachthe back
of the die to the substrate. Depending on thenumber of I/O and the
lead pitch, multilayer substrate fab-rication techniques may be
used to translate a peripheralbonding land die, to an area array
matrix of bumps, balls,or columns (see Figure 3-6).The transition
of chip bonding lands that are in an arrayformat permits the
mounting of the die in flip chip configu-rations. In this instance,
the die is mounted opposite to thatwhich is wire-bonded and the
bumps of the die come intodirect contact with the substrate being
used to convert thedie pattern to the BGA pattern. This creates new
challengesfor the routing requirements for the organic
high-densitymicrocircuit board manufacturer. In addition, underfill
isusually required to maintain some consistency between
thecoefficient of thermal expansion (CTE) of the chip and theCTE of
the organic multilayer board (see Figure 3-7).3.1.3 Assembly
Equipment Impact Getting into BGAtechnology also requires some new
assembly capability.
Depending upon the type of pick and place systems, achange in
package carrier mechanism may also be requiredto transfer packages
from matrix tray to the pick position.Fiducials may also be helpful
in helping the vision systemsrecognize the exact location of the
land pattern for theBGA, similar to what is used for fine-pitch
peripheralleaded parts. Large BGA parts on tape-and-reel will
require44 mm and 56 mm feeders depending on the body size.Use of a
forced air convection oven is preferred. Repairand inspection of
BGAs are rather difficult. Reworkmachines with paste deposition,
preheat, and vision capa-bility may not be required, but are very
helpful. X-ray andoptical inspection (endoscope) capability for
process devel-opment is a benefit.
3.1.4 Stencil Requirements The stencil thickness mayneed to be
reduced when using finer pitch BGA parts. Sten-cil thickness and
land size will determine paste volume,which is very critical for
ceramic BGAs. It is helpful tohave trapezoidal stencil apertures
(slightly larger opening
Figure 3-5 Conductor width to pitch relationship
Conventional FR-4125 m Line125 m Space700 m Land
Conventional FR-4125 m Line125 m Space600 m Land
High Density FR-4100 m Line100 m Space600 m Land
Next Gen FR-460 m Line50 m Space300 m Land
Next Gen Microvia50 m Line50 m Space50 m Land
Typical Microvia75 m Line100 m Space200 m Land
0.25 mm Pitch 0.5 mm Pitch 0.75 mm Pitch 1.0 mm Pitch 1.27 mm
Pitch
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on the bottom than on the top) for better paste
release.Generally, on larger BGA components with 1.25 mm and1.00 mm
pitch, the aperture is large enough that stencilclogging, print
registration and definition are less of a prob-lem than with quad
flat pack (QFP) components.Matching solder paste stencil openings
to the requirementsof fine-pitch BGAs requires an understanding of
the rela-tionship between the stencil aperture and the size of
theparticles in the paste. IPC-7525 provides good descriptionsto
help make the appropriate relationship decisions as theland
patterns for attachment becomes smaller and arecloser to one
another.
3.1.5 Inspection Requirements As with any surfacemount part,
BGAs should not be moved after componentplacement because this may
smear the paste and cause sol-der bridges. The outline of the
component can be includedin the silk screen to show gross alignment
problems, butthe parts will self align during reflow if not more
than 50%off the land. If a BGA has a gross misalignment problem
it
should be removed before reflow and reworked later.Though it may
not be practical for high volume production,using X-ray or optical
inspection (endoscope) to inspectfailures before removing the part
may be desirable.
3.1.6 Test Test strategies need to be developed beforeusing
BGAs. The solder joints cannot be probed and testpoints are
required. It may be difficult to incorporateenough test points to
adequately test all solder joints. Somealternative test strategies
may be needed. Some BGA com-ponents may have boundary scan designed
into them forincreased test capability. Some BGA components have
testpoints designed right on the top of the package. This is nota
good practice, since it puts pressure on the BGA compo-nents and
the joints.
3.2 Time-to-Market Readiness In some cases eachdesigner will
have an option to use or not to use BGAs.The alternative may be
using a high pin count QFP. How-ever, if a company is new to BGAs,
it may take some time
Overmolded Epoxy
BT Substrate
Wire Bonds
Die AttachSolder Balls(Sn63Pb37)
Silicon Die
IPC-7095b-3-6
Figure 3-6 Plastic ball grid array, chip wire bonded
IPC-7095b-3-7
Figure 3-7 Ball grid array, flip chip bonded
97/3 or 95/5 Sn/Pb Solder orZ-Axis Interconnect Plated
Copper
Conductor
EutecticSolder BallThermal Via
Soldermask BT Epoxy PCB
UnderfillEpoxy
Signal andGround Via
IC
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for the user and the suppliers of printed boards and assem-bly
services to address the technical and business issues inorder to
implement BGAs into products. It is very likelythat time to market
will be adversely impacted if bothproducts and the technology are
developed simultaneously.It is a good idea first to develop and
validate the technol-ogy before implementing it on a real product.
Otherwise, ifany problem develops in the product or technology,
thedeadline for product shipment will be missed. To
assuretime-to-market readiness, BGA implementation methodol-ogy and
process steps should be analyzed.
3.3 Methodology The designer faces a broad task. He orshe must
consider form, fit, function, cost, reliability, andtime-to-market
before choosing a particular course. In gen-eral, product design is
cost, size, and/or performancedriven. But in addition to the design
and assembly chal-lenges discussed above, the product must also be
able toprovide requisite performance in its stated
environment(including temperature, vibration, and moisture).
Reliabil-ity must be such that the product functions as intended
inthe working environment over the predicted life span of
theequipment. Package selection may be driven by environ-ment and
reliability requirements.
3.4 Process Step Analysis There are several availablepaths to
utilizing BGAs effectively. The length of each pathdepends on what
design and assembly facilities a companypresently has, and how
quickly they can be made ready forproduction. The following is an
example of one approach.
1. Select a list of candidate products for BGAs.2. Develop an
equipment list based on the projected vol-
ume needs. If sufficient in-house expertise does notexist, it
may be desirable to use a reputable trainingcenter or consultant to
save cost and time.
3. Organize a team representing design, production,
test,quality, and purchasing. This team is responsible forcomponent
and equipment selections and review.
4. Develop a comprehensive BGA design guide thatstresses
manufacturability. Use existing standards wherepossible.
5. Design the candidate products starting with the conver-sions
of existing products using fine pitch components.
6. Determine the need for lead-free products including thealloy
used on the part as well as the surface finishneeded on the
mounting substrate.
7. Conduct rigorous assembly and test reviews. Carefullymonitor
component purchasing to assure that compo-nents have the specified
package, shipping method, met-allization, solderability, and
orientation in the shippingcontainers.
8. Develop comprehensive workmanship standards and aprocess
control system that is statistically sound.
9. Design the remaining candidate products.
With the major emphasis on using parts that meet bothcustomer
requirements and conform to new global regula-tions, many customers
are requiring that their suppliers,both component and assembly
service providers, indicatethe materials that are a part of the
component or have beenintentionally added in order to provide a
reliable assembly.The requirement to establish a formal declaration
systemhas been in place since the automotive industry was
chal-lenged by the End-of-Life European directives.
To show an example of the breadth of the variation inmaterial
properties that may occur in products, Table 3-3shows a list of
materials that might be used as a surfacefinish or a material that
was added to the assembly as thesecond level interconnection.
3.5 BGA Limitations and Issues Since BGA technologyhas moved
into the mainstream there are still some deci-sions that need to be
considered. These are business andtechnical issues that must be
resolved. The areas of specialconcern are:
Visual Inspection Moisture Sensitivity Rework Cost Availability
Voids in BGA Standards and their adoption Reliability ConcernsBGA
issues are not insurmountable, however they requirededicated
engineering resources to develop and implementthe process.
3.5.1 Visual Inspection BGA is not a package suitablefor
companies that assure quality by inspection and repair.BGA solder
joints cannot be inspected unless X-ray oroptical inspection
techniques are used. To reap the benefitsthat BGA offers, robust
process control must be main-tained. Due to limited time and
training, many companiesfind implementing such tight process
control to be a diffi-cult endeavor.
There are some visual inspections that would show goodflow on an
un-collapsed ball with ceramic BGAs, and alsobe able to show
collapsed balls on plastic BGAs. Visualinspections of BGAs can
identify problems with solderjoints. Visual inspection of the outer
rows serves as anindicator of some of these problems. Examples are
BGAalignment with the lands on the outer rows or how theBGA is
sitting on the board, level or skewed.
3.5.2 Moisture Sensitivity The plastic BGA packagesare very
moisture sensitive. This makes th