ECE 485/585 Microprocessor System Design Lecture 3: Polling and Interrupts Programmed I/O and DMA Interrupts Memory Hierarchy Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F.
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ECE 485/585Microprocessor System Design
Lecture 3: Polling and InterruptsProgrammed I/O and DMA Interrupts Memory Hierarchy
Zeshan Chishti
Electrical and Computer Engineering Dept
Maseeh College of Engineering and Computer Science
Source: Lecture based on materials provided by Mark F.
ECE 485/585
I/O Subsystems – Things to Think About
What instructions does the processor use to communicate with I/O devices?
◼ Direct (Isolated) I/O
◼ Memory Mapped I/O
How do we know if an I/O device is ready or an I/O operation is complete
◼ Polling
◼ Interrupts
How do we transfer data between the I/O device and memory?
◼ Programmed I/O (PIO)
◼ Direct memory access (DMA)
Bus Mastering
ECE 485/585
I/O Completion or Ready Notification
Two methods:
◼ Polled I/O
◼ Interrupt driven I/O
Polled I/O:
◼ Peripheral make status (ex: busy/ready for new I/O request) available through an I/O port or memory mapped register
◼ CPU executes a busy-wait loop reading the status from the peripheral and looping until peripheral is ready to accept a new I/O request (and/or has completed the current I/O request)
Interrupt driven I/O:
◼ Peripheral signals the CPU when it is ready for a new I/O request (and/or has completed the current I/O request)
◼ Program running on the CPU is “interrupted” and starts executing the code that handles the peripheral
ECE 485/585
Simplified Polling Code Fragment
Microprocessor
Memory
I/O DeviceAddre
ss, D
ata
, Contro
l
READB: IN AL, BUSY ; get BUSY flag
TEST AL, BUSY_BIT ; test BUSY bit
JNE READB ; still busy -- loop
IN AL, DATAP ; read data
Polling
ECE 485/585
Interrupt Driven I/O
Permits the processor to execute useful instructions instead of polling an I/O device
The I/O device interrupts the processor when it needs attention (e.g. has data) or an I/O operation has completed
◼ Keyboard character typed, mouse button clicked, etc.
◼ Requested disk block has actually been read (this takes eons in CPU cycle time)
◼ Timer “tick” expired
◼ Analog/Digital conversion complete…new measurement available
◼ System “wake-up” (power saving architectures)
…
ECE 485/585
The Interrupt Mechanism
Hardware Interrupts (Asynchronous)
◼ Non-Maskable Interrupt(s) (NMI)
◼ Priority Maskable Interrupt(s) (INTR)
Software Interrupts (Synchronous)
◼ Nomenclature varies
Intel calls these “exceptions” to distinguish them fromH/W “interrupts”
Often called “traps” or “faults”
RISC architectures (ARM, MIPS, …) tend to name both hardware and software interrupts “exceptions” and handle them the same way