Invited Talk Optical Solutions for System-Level Interconnect Ian O'Connor , F. Gaffiot, F. Mieyeville G. Tosik, F. Tissafi-Drissi, M. Brière Laboratory of Electronics, Optoelectronics and Microsystems Ecole Centrale de Lyon 36 avenue Guy de Collongue, F-69134 Ecully, France
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Invited TalkOptical Solutions for System-Level
Interconnect
Ian O'Connor, F. Gaffiot, F. MieyevilleG. Tosik, F. Tissafi-Drissi, M. Brière
Laboratory of Electronics, Optoelectronics and MicrosystemsEcole Centrale de Lyon
36 avenue Guy de Collongue, F-69134 Ecully, France
15 February 2004
SLIP'04 2
Outline
n Context and motivations for optical interconnect– ITRS– Optical interconnect technology– Target applications
n Clock distribution– Structure and global design methodology– Interface circuit characteristics– Calculating losses in passive devices– Electrical-optical comparison
n Wavelength-reconfigurable networks on chip– Target functionality– Modelling and design environment– Architecture of reconfigurable network
15 February 2004
SLIP'04 3
n the interconnect problem: "For the long term, material innovation with traditional scaling will no longer satisfy performance requirements. Interconnect innovation with optical, RF, or vertical integration ... will deliver the solution" (International Technology Roadmap for Semiconductors 2003)
Context
Itanium IA-64
33%
51%
3%3 52
ClockI/O
Switching Logic
15 February 2004
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The optical alternative
n optical interconnect to:– increase throughput– reduce power dissipation– alleviate thermal constraints– reduce crosstalk– decrease skew– reduce signal distortion– simplify place-and-route for complex circuits
n but:– requires high-speed low-power interface circuits– process modifications– few quantitative analyses exist
15 February 2004
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Target applications
n point-to-point (1-1) links?– routing complexity– number of repeaters
• power• silicon real estate
n broadcast (1-N) links (clock distribution)– timing– clock noise– power and thermal issues
n network (N-N) links– throughput
K. Banerjee et al., Proc. IEEE, May 2001
15 February 2004
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Structure of integrated optical interconnectheterogeneous III-V on Si intégration
1000µm
1150µm
Ibiasimod
Vd
Vdd
driver circuit receiver circuit
2.5Gb/s realisation (ST CMOS
0.25um)
Cd
Rf
Aiin
vref
15 February 2004
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Passive photonic devices
if λi ≠ λkλi
if λi = λk
signal transport = waveguides and couplers
λ-switch =add-drop filter
• resonance mode λk depends on disc radius (um)
• SOI guides• Transmission at 1,55µm• intra-chip optical links
couplers, filters, routers
15 February 2004
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Active devices
InPactive layer
graftinterface SiO2
Silicon Microlasers :- heterogeneous integration (InP on Si)Technological simplification- Coupling to passive SOI guide- Thermal dissipation → low threshold
n concurrent design of electronic and optical parts for optical interconnect– use of predictive models (technology does not yet exist)– generic design methodologies and models
n Context and motivations for optical interconnect– ITRS– Optical interconnect technology– Target applications
n Clock distribution– Structure and global design methodology– Interface circuit characteristics– Calculating losses in passive devices– Electrical-optical comparison
n Wavelength-reconfigurable networks on chip– Target functionality– Modelling and design environment– Architecture of reconfigurable network
15 February 2004
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Clock distribution network (1-N)
source
Electrical local clocks Optical waveguides
Optical receivers
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n the route to calculating overall optical interconnect power is based on required signal quality (BER)
Calculating the power budget
Losses in passive
components
Minimum optical power at receiver
BER (SNR)
Minimum optical power at source (Popt, re)
Electrical power dissipated in optical systemPTOTAL= PLaser +n* PReceiver
PhotodetectorRq,CD,Idark
Transimpedanceamplifiers
q
Nopt R
iQrrP
2
min 11
−+=
1
0
opt
opt
P
Pr =
10-15
15 February 2004
SLIP'04 13
Determining TIA characteristics
n simple analytical equations for transistor characteristics insufficient (>100% error)
n but extraction requires transistor-level schematics
n synthesis
Rq critical for powerCd critical for data rate
total noise at photoreceiver
( ) ( )m
T
fdarkgateN g
CDE
CkT
DC
RkT
IIqi2
2
22 2
164
44
2π
πΓ+
++=
J.J. Morikuni et al., IEEE J. Lightwave Tech., July 1994
15 February 2004
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Photoreceiver front-end IP block
photo-receiverfront endλ
PL
DVdd
vout
CL
PIN photo-diode
TIAiin
Rd Cd
fc BWZin
Zg
sizing dimensions
Design (IP) block
performance criteria evaluation method
evaluation dimensionssizing method(s)
results
meshmZRd
HDL-A / EldoRd iin Zg Zin Cd BW fc
PL vout D
Vd
Vd
in
e
gout i
BWs
Zv ⋅
+=
π21
15 February 2004
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"Design ease" Ro/Av against bandwidth and transimpedance
gain
TIA synthesis
Vo
Ii
Cd
Rf
Cl
-Av
Rf
ClCi
Cm Ro
- AvviCo VoCdIi
v
vfo
g AARR
Z+−
=10
( )mxmxf
v
MMMMMA
CyR +++
=11
0
0ω
( )( ))1()1(1
1)1(
vfmfx
xmxvf
AMMMMMMMAM
Q++++
+++=
sizing dimensions
Design (IP) block
performance criteria evaluation method
evaluation dimensionssizing method(s)
results
bisectionMf
equationsAv Ro
Q ω0 Zg0
Rf
2/1=Q Maximize bandwidth
• sizing TIA with iterative procedure• accurate specification tolerance• systematic convergence
Bonding issuesn flip-chip is today the most effective and proven technique
– alignment down to 1um accuracy– solder bumps under 10um diameter
n in the future:– molecular bonding– direct wafer bonding– ...
CMOS IC
InGaAs/InPphotodiode thermocompression
Au
15 February 2004
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Investigation conditions and program
n comparison of optical and electrical clock distribution networks:– power vs. chip size– power vs. operating frequency– power vs. number of distribution points– power vs. technology node– power vs. sidewall roughness
Optical devices
Transistors
Metallic wires
Technology parameters
Existing technology
BSIM3v3 and BSIM4 model parameters [Berkeley Univ.]
ITRS roadmap
ITRS roadmap
Optical CDNElectrical CDN
InGaAsPhotodiode(InGaAl)As/InPVCSEL
G8376-02Hamamatsu Corp.Amann TUMunchen
15 February 2004
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Electrical-optical comparison
n comparing optical clock distribution power dissipation for varying chip size
n @70nm node, 5.6GHz, 256 drop points
0
500
1000
1500
2000
2500
10 13 16 19 22 25 28 31 34 37Chip width [mm]
Po
wer
co
nsu
mp
tion
[mW
] Electrical CDNOptical CDN
15 February 2004
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Electrical-optical comparison
n comparing optical clock distribution power dissipation for varying operating frequency
n @70nm node, 20mm chip width, 256 drop points
0
200
400
600
800
1000
1200
1400
1600
1 2 3 4 5 6 7 8Operating frequency [GHz]
Pow
er c
onsu
mpt
ion
[mW
]
Electrical CDNOptical CDN
15 February 2004
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Electrical-optical comparison
n comparing optical clock distribution power dissipation for varying number of drop points
n @70nm node, 5.6GHz, 20mm chip width
1
10
100
1000
10000
4 8 16 32 64 128 256 512 1024 2048 4096 8172
Number of output nodes in H-tree
Pow
er c
onsu
mpt
ion
[mW
]
Electrical CDNOptical CDN
15 February 2004
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Electrical-optical comparison
n comparing optical clock distribution power dissipation for varying technology node
n 20mm chip width, 256 drop points
0
200
400
600
800
1000
1200
130 100 70 45Technology node [nm]
Pow
er c
onsu
mpt
ion
[mW
]
Electrical CDNOptical CDNOptical CDN on chip
15 February 2004
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Electrical-optical comparison
n comparing optical clock distribution power dissipation for varying sidewall roughness
n @70nm node, 5.6GHz, 20mm chip width, BER=10-15
0
200400
600800
10001200
140016001800
1 2 3 4 5 6 7 8 9 10
Waveguide transmission loss [dB/cm]
Lase
r ou
tput
pow
er [m
W]
128 output nodes
256 output nodes
2nm roughness [MIT]11mW 5nm roughness
500mW
15 February 2004
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Clock distribution conclusionsn optical clock distribution gives a five-fold improvement in power
dissipation at 5GHzn this factor will increase as optical technology improves and operating
frequencies risen where is work needed?
n more details at DATE Wednesday session 5G 12:00
optical source
passive optical components
optical receiver
source efficiency equal to 10-15%
source improvementsmicrosources
trans. loss ∼1.5db/cmsplitting loss ∼ 0.2dBcoupling loss ∼ 3dB
sidewall roughness improvements
TIA power dissipation too high
reduce photodiode capacitance
improved circuit architecture
15 February 2004
SLIP'04 30
Outline
n Context and motivations for optical interconnect– ITRS– Optical interconnect technology– Target applications
n Clock distribution– Structure and global design methodology– Interface circuit characteristics– Calculating losses in passive devices– Electrical-optical comparison
n Wavelength-reconfigurable networks on chip– Target functionality– Modelling and design environment– Architecture of reconfigurable network
n depending on the disc material parameters and dimensions, several resonant wavelengths exist
n lightwave will couple into the disc (and then out via the otherwaveguide) if its wavelength is equal to one of the microring'sresonant wavelengths
n otherwise there is no coupling and the lightwave propagates normallyn selectivity critical factor in number of channelsn estimation of sensitivity of λk to mismatch ...
λ1
λ1
λ1
λ2 λ2
15 February 2004
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Microring selectivity and FSR
λ1λ1
λ1
λ2 λ2
λ1
=⋅∇
=⋅∇
×∇=∂∂
×∇−=∂
∂
0
0
1
1
B
D
HtE
EtH
r
r
rr
rr
ε
µN
tt
P
−+
= 20
20
20
)(/4/4
)(ωω
ω
15 February 2004
SLIP'04 34
n library of building blocks (Matlab and VHDL-AMS)– equation capture for all elements– parameter extraction for model simulation– simulation results: power, attenuation, data rate ...
Models for system design
E1(t,ω(i))
E2(t,ω(i))
Eopt1(t)φ1(t)∆λ1Eopt2(t)φ2(t)∆λ2
15 February 2004
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Design environment
15 February 2004
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Photonic device simulation tools
1um
7um
6umwaveguides
(transport)resonators(routing)
n 2D-3D FDTD (finite difference time domain) methodn simulation engine integrated into standard EDA
environment (Cadence)n parallel execution and memory bus usage optimization
15 February 2004
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Modelling and simulation of an optical crossbar
Injection in port #1
Port #2 Port #3 Port #4
in
out
out
out
A
B
C
D
λ1
λ1
λ2
λ3
λ3
λ4
A
B
C
D
ABCD
A B C Dλ2 λ4λ3λ3
λ3
λ3
λ1λ1
λ1λ1
λ2λ2
λ2
λ4λ4
λ4
receiver
emitt
er
t λ
15 February 2004
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4x4 optical cross-bar
170µm
25µm
Total area for passive network: 0.00425 mm2
+ Connections to SoC IP blocks
λ1 λ2 λ3 λ4
15 February 2004
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32x32 optical cross-bar
200µm
730µm
Total area for passive network: 0.146 mm2
15 February 2004
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Conclusionn optical links are moving into the chipn first quantitative comparisons show an advantage for
optical clock distribution over electrical schemesn but is it enough?n do we really need global clock distribution?n optical network on chip promising:
– scalable passive structure developed, test under way– low real estate, high throughput, should be full-duplex
n high-level models necessary for design (SystemC)n watch this space for quantitative comparisonn more details at DATE:
– Wednesday session 4E 10:30 and session IP3 11:00– Friday W2 Parallel optical interconnects inside electronic systems