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Investigation of SNM with Random Dopant Fluctuations for FD SGSOI and FinFET 6T SOI SRAM Cell by Three-dimensional Device Simulation R. Tanabe, Y. Ashizawa and H. Oka Fujitsu Laboratories Ltd. 50 Fuchigami, Akiruno, Tokyo, 197-0833 Japan E-mail: tanabe.ryou,jp.fujitsu.com Abstract- As CMOS technology is dramatically scaled down in recent years, the operation of SRAM becomes one of critical issues for further scaling. In this paper, we have focused on both FD SGSOI and DG (FinFET) devices because of the scaling capabilities, and we have simulated SRAM SNM with discrete dopant fluctuations in the channel regions by 3D simulation. As for SNM, FinFET is a promising candidate up to 32nm node, but for 22nm node, it will be difricult to operate even a FinFET with stability. As for fluctuations, the total number of dopant in channel depletion layer is a key factor. The fluctuations of SNM in FinFET are reduced by balancing fin thickness and dopant density in the channel. Keywords-component; FinFET; FDSOI; SRAM; Static Noise Margin;fluctuation; scaling; 3D simulation; TCAD I. INTRODUCTION As CMOS technology is dramatically scaled down in recent years, the operation of SRAM becomes one of critical issues for further scaling. The gate length for high performance operation is predicted to be 9 nm in 2016 [1]. It is important for reliability to keep static noise margin (SNM) large enough to overcome random dopant fluctuations. Recently, in addition to bulk SRAM transistors, novel SRAM structures such as single gate (SG) SOI and double gate (DG) device (FinFET) are frequently reported and discussed. SGSOI and FinFET transistors are very strong for short channel effect and have excellent scalability. In addition, its performance becomes enough to be used for industry production [2, 3, 4, 5]. In this paper, we have focused on both FD SGSOI and DG (FinFET) devices because of the scaling capabilities, and we have simulated SRAM SNM with discrete dopant fluctuations in the channel regions by 3D simulation. We will also show the perspective for scaling in the future. II. SIMULATION METHOD Fig. 1 shows simulated 6T FinFET SRAM cell structure. It was constructed with the combination of 3D process emulator and 3D device simulator. Figure 1. Simulated 6T SOI SRAM structure. This structure is calculated. SRAM characteristic was calculated by coupling Poisson equation and electron and hole continuity equations. We calculated whole this cell layout structure. By this method, real circuit characteristics can be calculated directly, and we can get very accurate circuit characteristics. By recent computer performance improvement, the 3D simulator becomes very powerful tool for future perspectives. In this calculation, we considered 45nm, 32nm and 22nm technology nodes, and the calculation parameters are listed in Table 1. TABLE I. CALCULATION PARAMETERS. WE FOCUSED 3 TECHNOLOGY NODES (45,32, 22NM). Technology Node Scaling Ratio DRAM Pitch Lsd Lg Lov TfinN TfinP Hfin 1 Fin Cell size (uM2) 2 Fin Cell size (uM2) 45 45 40 25 3 15 15 50 0.228 1 0.3397 32 0.71 32 28 18 2.5 12 12 50 0. 1473 0.1742 22 0.69 22 20 13 2 8 8 50 Unit: ,um 0.06942 0.08203 Area Penalty (%) 17.9 18.3 18.2 1-4244-0404-5/06/$20.00 © 2006 IEEE SISPAD 2006 103
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Investigation ofSNMwithRandom Dopant Fluctuations FD ...in4.iue.tuwien.ac.at/pdfs/sispad2006/pdfs/04061591.pdf · The gate length for high performance operation is predictedtobe9nmin

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Page 1: Investigation ofSNMwithRandom Dopant Fluctuations FD ...in4.iue.tuwien.ac.at/pdfs/sispad2006/pdfs/04061591.pdf · The gate length for high performance operation is predictedtobe9nmin

Investigation of SNM with Random Dopant Fluctuationsfor FD SGSOI and FinFET 6T SOI SRAM Cell

by Three-dimensional Device Simulation

R. Tanabe, Y. Ashizawa and H. OkaFujitsu Laboratories Ltd.

50 Fuchigami, Akiruno, Tokyo, 197-0833 JapanE-mail: tanabe.ryou,jp.fujitsu.com

Abstract- As CMOS technology is dramatically scaled down inrecent years, the operation of SRAM becomes one of criticalissues for further scaling. In this paper, we have focused on bothFD SGSOI and DG (FinFET) devices because of the scaling

capabilities, and we have simulated SRAM SNM with discretedopant fluctuations in the channel regions by 3D simulation. As

for SNM, FinFET is a promising candidate up to 32nm node, butfor 22nm node, it will be difricult to operate even a FinFET with

stability. As for fluctuations, the total number of dopant in

channel depletion layer is a key factor. The fluctuations of SNM

in FinFET are reduced by balancing fin thickness and dopant

density in the channel.

Keywords-component; FinFET; FDSOI; SRAM; Static NoiseMargin;fluctuation; scaling; 3D simulation; TCAD

I. INTRODUCTIONAs CMOS technology is dramatically scaled down in recent

years, the operation of SRAM becomes one of critical issuesfor further scaling. The gate length for high performanceoperation is predicted to be 9 nm in 2016 [1]. It is important forreliability to keep static noise margin (SNM) large enough toovercome random dopant fluctuations. Recently, in addition tobulk SRAM transistors, novel SRAM structures such as singlegate (SG) SOI and double gate (DG) device (FinFET) arefrequently reported and discussed. SGSOI and FinFETtransistors are very strong for short channel effect and haveexcellent scalability. In addition, its performance becomesenough to be used for industry production [2, 3, 4, 5].

In this paper, we have focused on both FD SGSOI and DG(FinFET) devices because of the scaling capabilities, and wehave simulated SRAM SNM with discrete dopant fluctuationsin the channel regions by 3D simulation. We will also show theperspective for scaling in the future.

II. SIMULATION METHODFig. 1 shows simulated 6T FinFET SRAM cell structure. It

was constructed with the combination of 3D process emulatorand 3D device simulator.

Figure 1. Simulated 6T SOI SRAM structure. This structure is calculated.

SRAM characteristic was calculated by coupling Poissonequation and electron and hole continuity equations. Wecalculated whole this cell layout structure. By this method, realcircuit characteristics can be calculated directly, and we can getvery accurate circuit characteristics. By recent computerperformance improvement, the 3D simulator becomes verypowerful tool for future perspectives. In this calculation, weconsidered 45nm, 32nm and 22nm technology nodes, and thecalculation parameters are listed in Table 1.

TABLE I. CALCULATION PARAMETERS. WE FOCUSED 3 TECHNOLOGYNODES (45,32, 22NM).

Technology NodeScaling RatioDRAM Pitch

LsdLgLovTfinNTfinPHfin

1 Fin Cell size (uM2)2 Fin Cell size (uM2)

45

4540253151550

0.228 10.3397

320.713228182.5121250

0. 14730.1742

220.6922201328850

Unit: ,um0.069420.08203

Area Penalty (%) 17.9 18.3 18.2

1-4244-0404-5/06/$20.00 © 2006 IEEESISPAD 2006 103

Page 2: Investigation ofSNMwithRandom Dopant Fluctuations FD ...in4.iue.tuwien.ac.at/pdfs/sispad2006/pdfs/04061591.pdf · The gate length for high performance operation is predictedtobe9nmin

For the simulation of discrete dopant fluctuations inchannel regions, we constructed the methodology shown inFig. 2.

)opant Database

Select NMOS x 4, PMOS x 2

Boron Database

FinFET Databese

FDSOI DatabeseArsenic Database

FinFET Databese

FDSOI DatabesezM

III. RESULTS AND DISCUSSIONSIn Fig.4, we show the butterfly curves of FinFET for each

technology node. As scaled down, the area of margin window(SNM) becomes smaller, and it decreases dramaticallyespecially in 22nm node.

1.2

1

0

0.8

0.6

0.4

0.2

Figure 2. Simulation methodology including random dopant fluctuations inthe 6T SRAM.

First of all, we calculate many pairs ofNMOS and PMOSstructures with random dopant distributions in the channelregions, and build an NMOS and PMOS database. Next, wepick up 4 NMOS and 2 PMOS pairs (for 6T SRAM Cell) fromthe database randomly. In this calculation, we distributedcarrier charges by using Sano Model [6]. Finally we calculateSRAM characteristics for many cases. In Fig.3, we show theBoron distribution in the 6T SRAM, which is introduced bydifferent dopant distribution. By calculating many cases, wecan evaluate the fluctuation ofSNM statistically.

(a)

00 0.2 0.4 0.6 0.8 1 1.2

Vin

Figure 4. Butterfly curves ofFinFET for each technology node.

In Fig.5, the comparison of SNM between FD SOI andFinFET is shown. For 45nm node, both SNMs are almost equal,but for 32nm node, SNM of FDSOI decreases. This is becausein FDSOI, short channel effect can not be suppressed enough.For 22nm node, SNM of FinFET also decreases dramatically,and it will be difficult to operate SRAM circuits with stabilityeven in FinFET.

180

160140

120

s 100

z 80' 60

40

20

0

(b)

IN1 O+19

_ _ ._. . . .~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~..

4OE 18

1 6E 18

6.3E 17

25OE+17

Figure 3. Boron distribution in the 6T SRAM.(a) FD SG SOI (b) FinFET

20 25 30 35 40Technobgy Node (im)

45 50

Figure 5. The comparison ofSNM for FD SOI and FinFET (45nm node).

Some methods to improve SNM were proposed forFinFETs [7]. According to this method, we have improved f-ratio by increasing the number of fins at the driver NMOSs asshown in Fig.6. We show the butterfly curves for comparisonin Fig.6. From this result, two-Fin SRAM improves SNM byabout 30 °0 than one-Fin SRAM. But there is area trade-offbecause of added number of fins. This penalty is about 18%.As a result, it is very important for circuit designers to balanceimprovement ofSNM and area penalty.

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C.)\ NCh=5el8cm-3*1LUU

- _ >2 o'7| lo t.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-X\\ 1 S t~~~~~~~~~~~~~~~~~~~~~~~~~. ... ....l , , , ....^\ \: NS - s - , ~~~~~~~~~~~~~~~~~~~~..., . .,... , ....2

\ \\ ~~~~~~~0.1400.145 0.150 0.155 0.160 0.165 0.170 0.175

\ \ ~~~~~~~~~~SNM

~~~~~~~Figure 8. The comparison of SNM frequency distribution between FD S0Il.2 and FinFET. Sample number is 18.

Vin

Figure 6. The butterfly curves of 1-Fin and 2-Fin 6T SRAM.

Next, we will discuss the fluctuations of SRAM SNM byrandom dopant fluctuation. As scaled down with increasingchannel dopant density, the fluctuation of discrete dopant inchannel becomes very important. In Fig.7, many butterflycurves with different channel distribution are shown. Fig.8shows the fluctuations of SNM for FD SOI and FinFET at45nm node. The SNM ofFinFET is larger than that ofFD SOI,but the fluctuation of FinFET is still smaller than that of FDSOI. These results indicate that FinFET will become thepromising candidate for future device structure against bothaverage of SNM and fluctuations. From discussions above, wewill focus on FinFET in next session.

1.2

1

0.8

0 0.6

0.4

0.2

0

0 0.2 0.4 0.6Vin

0.8 1 1.2

Figure 7. The butterfly curves with random dopant fluctuations for SNM in6T FinFET SRAM circuit.

It is very important to analyze the scalability of device forfuture perspectives. Fig.9 shows the fluctuations of SNM inFinFET SRAM for each technology node. Not only the averagevalue of SNM but also the fluctuation decreases as scaled down.

14

12

10

c.)

a)

6

0

0.000 0.050 0.100 0.150

SNM

Figure 9. Frequency distribution of SNM as scaled down in FinFET. Samplenumber is 18.

As channel thickness of the fin becomes thinner and gatearea also becomes smaller with scaling, we consider that thetotal number of dopant in channel depletion layer plays animportant role in fluctuation. To clarify this relationship, wewill show the total number of dopant in channel as a functionof technology node in Fig. 10. Because absolute value of dopantin channel decreases as scaled down, the fluctuations of SNMare also suppressed. This is because the volume of channeldepletion layer is reduced more aggressively with scalingalthough dopant density in channel increased conventionally.This result suggests that the fluctuations of SNM can bereduced by using thinner fins even though dopant density inchannel increased with scaling. Of course, intrinsic channel forfins is more effective in fluctuations than doping channel. Infurther scaled regime, these parameters in FinFET will becomecrucial for designing SRAM circuit.

1-4244-0404-5/06/$20.00 2006 IEEE

1.2

1

0.8

> 0.6

0.4

0.2

0

SISPAD 2006 105

Page 4: Investigation ofSNMwithRandom Dopant Fluctuations FD ...in4.iue.tuwien.ac.at/pdfs/sispad2006/pdfs/04061591.pdf · The gate length for high performance operation is predictedtobe9nmin

(T- (fin=15nm(Tfin=8nm) (Tfin=l 2nm) nm)

+Atom ic Numnber in ChannelC hannelD ensityI I I

a)

cr 60

(.-

') 40

r=

E= 20

¢9

22 32Technobgy Node nim)

1.2E+19 (M

CD

8.OE+18 tCD

4.OE+180

0.OE 00

45

Figure 10. Frequency distribution of SNM as scaled down in FinFET.

IV. CONCLUSIONSNM and fluctuations in FD SGSOI and FinFET 6T SOI

SRAM cell were analyzed by 3D process emulation and devisesimulation. As for SNM, FinFET is a promising candidate upto 32nm node, but for 22nm node, it will be difficult even forFinFET to operate with stability.

As for fluctuations, the total number of dopant in channel isthe key factor. The fluctuations of SNM in FinFET are reducedby balancing fin thickness and dopant density in channeldepletion layer. In further scaled regime, these parameters inFinFET will become crucial for designing future SRAM circuit.

REFERENCES

[1] http://public.itrs.net/[2] J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D.

Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N.Zelick and R. Chau, "Tri-Gate Transistor Architechture with High-kGate Dielectrics, Metal Gates and Strain Engineering," symp. VLSITech. Dig., 2006.

[3] M. Khellar, Y. Ye, N. Kim, D. Somasekhar, G. Pandya, A. Farhang, K.Zhang, C. Webb and V. De, "Wordline & Bitline Pulsing Schemes forImproving SRAM Cell Stability in Low-Vcc 65nm CMOS Design,"symp. VLSI Circuit Dig., 2006.

[4] H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric, S.Lamphier, M. Miller. A. Roberts and F. Towler, " An SRAM Design in65nm and 45nm Technology Nodes Featuring Read and Write-AssistCircuit to Expand Operating Voltage," symp. VLSI Circuit Dig., 2006.

[5] S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda,M. Igarashi, M. Takeuchi, H, Kawashima, H. Makino, Y. Yamaguchi, K.Tsukamoto, M. Inuishi, K. Ishibashi and H. Shinohara, "A 65nm SoCEmbedded 6T-SRAM Design for Manufacturing with Read and WriteCell Stabilizing Circuits," symp. VLSI Circuit Dig., 2006.

[6] N. Sano, K. Matsuzawa,M. Mukai and N. Nakayama, "Role of long-range and short-range Coulomb potentials in threshold characteristicsunder discrete dopants in sub-0.1 gm Si-MOSFETs," IEDM Tech. Dig.,pp. 275 - 278, 2000.

[7] Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King and B. Nikolic,"FinFET-Based SRAM Design," ISLPED'05, pp. 2-7, 2005.

1-4244-0404-5/06/$20.00 2006 IEEE

80 1.6E+19

SISPAD 2006 106