Investigating latchup in the PXL detector Outline: What is latchup? – the consequences and sources of latchup – techniques to reduce latchup sensitivity Other single event effects Latchup tests at BNL Latchup tests at 88” cyclotron Latchup tests at STAR Radiation environment at STAR Summary
Investigating latchup in the PXL detector. Outline: What is latchup? the consequences and sources of latchup techniques to reduce latchup sensitivity Other single event effects Latchup tests at BNL Latchup tests at 88” cyclotron Latchup tests at STAR Radiation environment at STAR - PowerPoint PPT Presentation
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Investigating latchup in the PXL detector
Outline:
What is latchup?– the consequences and sources of latchup– techniques to reduce latchup sensitivity
Other single event effects Latchup tests at BNL Latchup tests at 88” cyclotron Latchup tests at STAR Radiation environment at STAR Summary
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Latch-up – inadvertent creation of a low-impedance path, typically, but not only, between the power supply rails of an electronic component that triggers a thyristor-like parasitic structure, which acts as a short circuit.
– sustainable condition as long as the holding current can be delivered– To remove latchup, the circuit needs to be powered down
Consequences: damage to bond wires localized melting of metallization on the die due to localized overheating
CMOS device with parasitic bipolar transistors
What is latchup
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Sources of latchup
Supply voltages exceeding the absolute maximum ratings.
input/output pin voltage exceeding either supply rail by more than a
diode drop.
incorrect power sequencing.
Various spikes and transients
Energetic particles (Single Event Latchup - SEL)
Increasing density and circuit complexity in modern VLSI CMOS devices makes them more susceptible to latchup.
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Techniques to minimize latchup sensitivity
Increasing PMOS-NMOS spacing
Guard rings to form additional collectors for the parasitic transistors
Clamping diodes, current limiting resistors
CMOS processes:– Epitaxial layer instead of bulk CMOS– Retrograde well– Oxide trenches between
the NMOS and PMOS devices
www.ti.com
www.analog.com
www.ti.com
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What do we do for the PXL detector?
We know that latchup can happen in MAPS (see later slides)
At IPHC– On-going redesign of the standard digital cells for increased
spacing between NMOS and PMOS transistors
At LBL– Building power supply modules for PXL ladders with over-current
monitoring and automated shut down
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Other Single Event Effects (SEE)
Single event upset (SEU)– Bit-flips in memory chips and
microprocessors
Other effects:– a glitch, or a temporary change-of-
state of the output in combinatorial digital circuits
– Spurious pulse in analog electronics
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Latchup tests at TVDG at BNL
Test chamber
Ion beam
Device under test (DUT)
Test chamber
Power supplies + current monitoring
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Latchup cross section of various MAPS prototypes
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1 10 100
LET (Si) (MeV cm2/mg)
Cro
ss
-se
cti
on
(c
m2
)
SUZE
Mimosa22
Phase1
MimoSTAR2(2006)
onset of SEU
LET – Linear energy transfer
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LU and SEU at 88”
• Test chamber• Readout system• Test PCB• Milled down IC package
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Latchup tests at 88” cyclotron
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1 10 100
LET (Si) (MeV cm2/mg)
Cro
ss
-se
cti
on
(c
m2
)
mem
vdd
vda
std
2um
AD
Single counts
Test results: Mimosa26, LU_test_structures, ADC
Preliminary results, raw data
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Summary of heavy ion tests
Estimated the onset energy for latchup(let’s remember that 1.6 MeV cm2/mg 1000 MIP)
Measured latchup cross-sections
However in STAR we don’t expect to see such heavy ions– In STAR we can not generate the amount of required LET based
on the same energy loss mechanisms (primary ionization)
– We expect that the latchup will be dominated by inelastic nuclear collisions from particles with charge 1
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Latchup tests at STAR 2 x Mimosa26 chips
– VDA, VDD, VMEM 1 voltage regulator
Mimosa26 – predecessor of PXL sensor (Ultimate) includes on-chip zero suppression