Introduction to VLSI Programming TU/e course 2IN30 Lecture 2: Control Handshake Circuits (1) Prof.dr.ir Kees van Berkel [Dr. Johan Lukkien] [Dr.ir. Ad.

Introduction to VLSI Programming

TU/e course 2IN30

Lecture 2:Control Handshake Circuits (1)

Prof.dr.ir Kees van Berkel[Dr. Johan Lukkien][Dr.ir. Ad Peeters]

Philips Research, Kees van Berkel, Ad Peeters, 2002-09-10 2

TU/e

Time table 2005date class | lab subject

Aug. 30 2 | 0 hours intro; VLSI

Sep. 6 3 | 0 hours handshake circuits

Sep. 13 3 | 0 hours handshake circuits assignment

Sep. 20 3 | 0 hours Tangram

Sep. 27 no lecture

Oct. 4 no lecture

Oct. 11 1 | 2 hours demo, fifos, registers | deadline assignment

Oct. 18 1 | 2 hours design cases;

Oct. 25 1 | 2 hours DLX introduction

Nov. 1 1 | 2 hours low-cost DLX

Nov. 8 1 | 2 hours high-speed DLX

Nov. 29 deadline final report


TU/e

Last Week – Lecture 1


TU/e

Transistors

• CMOS is the dominant IC technology today (Complementary Metal Oxide Semiconductor)

• Two types of transistors are used– PMOS and NMOS

• Dimensions of transistors are scaled by 2 in every new generation– 0.5 - 0.35 - 0.25 - 0.18 - 0.12 - 90n - 70n - …

• This halves their area and makes them faster


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CMOS circuits

• Pull-up stack consisting of only P-mosts• Pull-down stack consisting of only N-mosts• Only inverting gates can thus be formed

Vdd

Vss

+

–V

Pull-up

Pull-down

P

N


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Boolean functions and transistors

• Transistors can be put in series– Conducting only if all conducting– This implements an AND function

• Transistors can be put in parallel– Conducting if either is conducting – This implements an OR function

• Networks can build AND/OR functions


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Production rules

• Production rules are guarded commands that specify (CMOS) gates F z, G z

• Interpretation– do F then z:=true or G then z:=false od

• Guards must be mutually exclusive (environment)• A gate is combinational if F G is a tautology and

it is sequential (state-holding) otherwise• Guards must be stable: once a guard is true it

must remain true until completion of transition


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Combinational CMOS gates

• Guards of production rules are complementary F z, F z

• This translates into z = F

• Combinational functions can be decomposed into inverting boolean functions

• These can be implemented directly in CMOS transistor stacks


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NAND gate

• z = (a b)• Inverting function, hence

single CMOS stage a b z

– Two P-mosts in parallel

• a b z – Two N-mosts in series

Vss

Vdd

a b

a

b

ab

z

z


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AND gate

• z = a b– a b z a b z

• Non-inverting function, hence two CMOS stages

• First stage: NAND-gate a b y – a b y

• Second stage: Inverter y z – y z

Vss

Vdd

a b

a

b

ab

z

z

y


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And-Or-Invert functions

• z = (a (b c))

• Inverting function, hence single CMOS stage

a (b c) z – Three P-mosts

• a ( b c) z – Three N-mosts

Vss

Vdd

ab

a

b

zc

c


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Exclusive-Nor in 10 transistors

• z = a b• = (a b) (a b)• = (a b) (a b)• = ((a b) (a b))

• y = (a b) Nand-gate, 4 mosts• z = (y (a b)) Or-And-Inv-gate, 6

mosts


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Sequential CMOS gates

• Guards of production rules are not complementary F z, G z

• This translates into z = F (z G) – Or (equivalently) z = G (z F)

• This can be decomposed in two combinational functions y = (F (z G)) and z = y

• Combinational function F (z G) can be transformed into basic inverting functions


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Realization of a Muller-C element

• Production rules a b z, a b z

• Implementation– z = F (z G ) – z = a b (z (a b )) – z = (a b) (b z) (z a) – z = majority(a,b,z)

Majab

z

C za

b


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Vss

Vdd

a b

a

b

z

z

a

b z

a b


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Vss

Vdd

a b

a

b

zz

abz

a

b


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Realization of an asymmetric C element• Production rules

a b z, b z

• Implementation– z = F (z G ) – z = (a b) (z b) – z = b (a z)

• Or-And-Inv plus an inverter• 8 transistors

C za

b

+


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VLSI basics

Vdd (power)

Vss (ground)

C

+

–V

Charge Q

wire

gate


TU/e

VLSI metrics

dimensionless quantities (0.25 m CMOS):

A area gate equivalent (Nand, 4 mosts)

(33 m2, or 30,000 geq/mm2)T time gate delay (0.35

nanosecond)(per basic inverting CMOS

gate)E energy transition (1 picojoule)

(per basic inverting CMOS stage)


TU/e

This Week – Lecture 2


TU/e

Handshake protocol

• Handshake between active and passive partner• Communication is by means of alternating

request (from active to passive) and acknowledge (from passive to active) signals

• Active: send request, then wait for acknowledge

• Passive: wait for request, then send acknowledge

Active Passive


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Handshake component: sequencer

Sequencer

Master

Task 1 Task 2


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Four-phase handshake protocol

• Circuit level implementation has separate wires for request and acknowledge

• Four-phase handshake protocol implements return-to-zero of these wires

Active Side Req := 1 ; Wait (Ack); Req := 0 ; Wait (-Ack);

Passive Side Wait (Req); Ack := 1; Wait (-Req); Ack := 0;

Req

Ack


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Handshake signaling

active side passive siderequest ar

acknowledge ak

acknowledge ak

request ar

time

event sequence: ar ak ar ak


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Handshake behaviors

Let xi be boolean variables, and Si commands:

• skip always terminates without effect• x is a shorthand for x:= true and x for x:= false • S1 ; S2 denotes sequential execution of S1 and S2

• S1 || S2 denotes parallel execution of S1 and S2

Program notation inspired by [Martin].


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Handshake behaviors

Let Gi be boolean expressions.

• Selection [G1 S1 [] … [] GN SN ] execute an arbitrary Si for which guard Gi holds. When no guard holds then suspend execution until otherwise.

• Repetition [G1 S1 [] … [] GN SN ] repeatedly execute Si for which Gi holds until all guards are false.


TU/e

Useful shorthands

• ‘wait until’ [G] = [G skip]

• Note: [G] ; S = [G S]

• Unbounded repetition [S] = [true S]


TU/e

Useful shorthands

• Four-phase handshakes– a = [ar] ; ak ; [ar] ; ak– a = ar ; [ak] ; ar ; [ak]

• Two-phase handshakes– a = [ar] ; ak – a = [ar] ; ak– a = ar ; [ak] – a = ar ; [ak]


TU/e

Reorder properties

In the absence of timing assumptions,

1. One cannot observe the order of output transitions x1 ; x2= x2 ; x1= x1 || x2

2. One cannot fix the order of input transitions [x1] ; [x2] = [x2] ; [x1] = [x1] || [x2]= [x1 x2]


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Enclosure and properties

• Enclosure – a : S = [ ar] ; S ; ak – a : S = [ ar] ; S ; ak

• Reorder propertya : b

= [ar] ; ([br] ; bk) ; ak= [br] ; ([ar] ; ak) ; bk= b : a


TU/e

Decomposition rule

• Let program P = … S … and let a be a “fresh” channel

• Program P can be decomposed into two parallel processes: P’ = … a ; a … and [a : S ; a ]


TU/e

Some handshake components

• Repeater : [a : [b ; b] ]

• Mixer : [ [ a : c ; [a : c] [] b : c ; [b : c]

] ]• Sequencer :

[[a : (b ; b ; c) ] ; [a: c]]

a

b

a

;

b c

|a

c

b


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Handshake circuit: duplicator

• For each handshake on a0 the duplicator produces two handshakes on a1

[[a0 : (a1

; a1 ; a1

) ] ; [a0: a1]]

• cf. Handshake behavior sequencer.


TU/e

Time for a break


TU/e

Production rules

• Production rules are guarded commands that specify (CMOS) gates F z, G z

• Interpretation– do F then z:=true or G then z:=false od

• Guards must be mutually exclusive (environment)• A gate is combinational if F G is a tautology and

it is sequential (state-holding) otherwise• Guards must be stable: once a guard is true it

must remain true until completion of transition


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Behavior of a gate network

• Gate network is the union of all pairs of production rules (gates)

• The concurrent execution of this set of PRs amounts to [Martin]:

[ select a PR ; fire that PR]

• If guard of PR equals false, firing = skip• (firing a PR is an atomic action)


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Initializable

A handshake component realization is initializable :

• when all inputs are false, the gate network must autonomously proceed to an initial state;

• when all passive inputs are false, the component must autonomously proceed to a state with all active outputs false.


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Handshake components: realization

From handshake notation to gate network in 8 steps:

1 Specify component in handshake notation.2 Expand to individual boolean variables (wires).3 Introduce auxiliary state variables (if required).4 Derive a set of production rules that

implements this refined specification.5 Make production rules more symmetric

(cheaper).6 (Verify isochronic forks.)7 Verify initialization constraints.8 Analyze time, area, and energy.


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Handshake components realizations• Connector: trivial• Repeater: alternative ‘symmetrizations’• Mixer: isochronic forks• Sequencer: introduction of auxiliary

variable• Duplicator: up to you? • Selector: up to you!


TU/e

Connector realization• Behavior: [a : b ; a : b ]

• Expansion: [ [ar] ; br ; [bk] ; ak ; [ar] ; br ; [bk] ; ak]

• Production rules: bk ak ar br bk ak ar br

• A pair of wires (!): no area, no delay, no energy.

a

b


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Repeater realization• Behavior: [a : [b ; b] ]

• Expansion:

[ [ar] ; [ br ; [bk] ; br ; [bk] ] ; ak ]

• Production rules:

false ak ar bk brtrue ak bk br

• However, not initializable!

a

b


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Repeater realizations


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Repeater: area, delay, energy

Repeater: area, delay, energy • Area: 2 gate equivalents• Delay per cycle: 2 gate delays• Energy per cycle: 2 transitions


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Mixer realization

• Behavior: [ [ a : c ; a : c [] b : c ; b : c

] ]• Restriction: ar br must hold at all times!• Expansion:

[ [ [ar] ; cr ; [ck] ; ak ; [ar] ; cr ; [ck] ; ak [] [br] ; cr ; [ck] ; bk ; [br] ; cr ; [ck] ; bk ] ]

a

c

b|


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Mixer realization

• Production rules:

ar ck ak br ck bk ck ak ck bk

ar br cr ar br cr

• More symmetric production rules:

ar ck ak ar ck ak

ar ck ak ar ck ak

premature ak more expensive

|a

c

b


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Mixer realizations

Mixer: area, delay, energy • Area: 6 gate equivalents• Delay per cycle: 8 gate delays• Energy per cycle: 8 transitions


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Assignment: duplicator realization

• Behavior:[[a : (b ; b ; b) ] ; [a: b]]

• Required: realization with 2 sequential gates(sequencer + mixer requires 3 sequential gates)

• Follow all 8 realization steps!!• Add comparison with sequencer+mixer

realization.

#2

a

b


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Duplicator chains

• Assume aM toggles at frequency f. • Hence a0 toggles at frequency f / 2M.

• Let Edup be the duplication energy per cycle.

• Power of duplicator chain equalsP = f Edup (1/2 + 1/4 + 1/8 + ...) < f Edup


TU/e

For those who are interested in the details• Synthesis of Asynchronous VLSI Circuits

– Alain J. Martin – Caltech CS-TR-93-28– PostScript link via async.bib (html version)

• Programming in VLSI: From communicating processes to delay-insensitive circuits– Pages 1–64 in C.A.R. Hoare, ed.,– Developments in Concurrency and

Communication


TU/e

General asynchronous background

• Principles of Asynchronous Circuit Design– Eds. Jens Sparsø and Steve Furber– Kluwer Academic Press, Dec. 2001– ISBN 0-7923-7613-7

• The ‘Asynchronous’ Bibliography– http://www.win.tue.nl/async-bib/

• The Asynchronous Logic Home Page– http://www.cs.man.ac.uk/async/


TU/e

Next week: lecture 3

Outline:• Handshake components • … and their realization as networks of

gates • Handshake circuits• Initialization of handshake circuits

Introduction to VLSI Programming TU/e course 2IN30 Lecture 2: Control Handshake Circuits (1) Prof.dr.ir Kees van Berkel [Dr. Johan Lukkien] [Dr.ir. Ad.

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