Introduction to Quartus and the DE2 Board ReadMeFirst · 2017-12-23 · Introduction to Quartus and the DE2 Board ReadMeFirst Lab ... A truth table of a half_adder with all possible

Introduction to Quartus and the DE2 Board

ReadMeFirst

Lab Summary

In this lab, you will learn the basic steps to create a project in the Quartus II development platform from Altera Corporation. This software allows you to implement digital circuitry on the FPGA chip. In addition to the FPGA, the DE2 board includes a number of peripheral devices that may be accessed and incorporated into the project, such as switches and LEDs. These will be incorporated in future labs, but your focus in this lab should be the basic mechanisms to create simple circuits and incorporate them into functional blocks.

One circuit you are asked to design in this laboratory is a 2-bit adder. You begin by constructing an exclusive or (XOR) logic gate. The gate is then incorporated in a higher-level design, the single bit adder. This will introduce you to hierarchical, that is, multi-layered design. The single bit adder can then be incorporated into a multi-bit adder design by using the “carry” bit to string the single bits together. You are also introduced to two utilities used to test and debug a design: the In System Memory Content Editor, and the Signal Tap II Logic Analyzer.

In the lab, you are introduced to methods for grouping a collection of logic elements into functional blocks that can be re-used in a schematic level design. This is actually an application of hierarchical design that you learned earlier in the lab.

Background

Arithmetic operations such as addition are essential to digital design. Given that it requires 8 inputs lines to add numbers even as small as 4-bits, it is impractical to use Boolean algebra alone. The solution is to break up the addition operation into its simplest pieces. For addition, the simplest piece is a half_adder, a device that adds two 1-bit numbers.

A truth table of a half_adder with all possible combinations of two 1-bit numbers A and B is shown below. The outputs S and C represent the 2-bit result of the addition where S stands for sum and C stands for carry. Notice that right most column corresponds to the final row in the truth table for adding two 1-bit numbers. The result of 1+1=2 cannot be stored in a single bit. As a result, the C bit or carry, needs to be sent to the next column, which is the overflowed bit.

A B A+B=? S C

0 0 0+0=0 0 0

0 1 0+1=1 1 0

1 0 1+0=1 1 0

1 1 1+1=2 0 1

You will see that the addition of three 1-bit numbers can be split into two additions of two 1-bit numbers with if an additional carry bit is included in the design. The resulting circuit is known as a full_adder. The full_adder circuit can be connected in series to add any number of binary bits. A group of hardware that you convert into a block in Quartus is called symbol file, since it is given its own block symbol with labeled input and output lines. Any schematic can be grouped into a symbol file. You may also use a software file written in a hardware design language called VHDL to create a symbol file. The latter is very useful since timing constraints can be defined in the VHDL code, and Quartus will generate the hardware needed to satisfy the timing criteria.

Altera also provides a library of symbol files for the most commonly used functions in an FPGA design. In Quartus, these are referred to as Megafunctions. The examples that you will use today include adders and multipliers, D flip-flops, ROM’s, and data selection switches called Multiplexers. The use of these functional blocks is collectively referred to as RTL (Register Transfer Level) design. The term is derived from the fact that nearly all logical functions in a synchronous digital design can be implemented using a combination of 1-bit storage latch (a “register”) called a D-flip-flop, and basic logic gates.

Lab Preparation

Supplies

DE2 Board x 1 USB Blaster Cable x 1 (already on your lab bench)

Videos: Videos are available on the Sophomore Experience website (u.osu.edu/ece2060labs)

For each part of the lab, follow the screencasts indicated below:

Part 1

1) Intro to DE2.mp4 2) Example Quartus Project.mp4 3) Program the FPGA.mp4

Part 2-4

4) Hierarchy.mp4

Part 5 5) Make Symbol Files from VHDL Files .mp4

Part 6

6) Buses and Megafunctions.mp4 7) In System Memory Content Editor.mp4 8) Signal Tap II Logic Analyzer.mp4

Part 1: XOR Gate

Dr. Khan goes through setting up a Quartus project in the following screencast:

1. Intro to DE2 & FPGA Chip.mp4 2. Example Quartus Project.mp4

The latest version of the DE2 contains an FPGA with a core voltage that can be changed. To match the core voltage to the library parts, this value must be set by the user. To do this perform the following steps:

1. Select the Files tab at the bottom of the Project Navigator window. 2. Select the Project pull-down menu at the top of the window and click on Add/Remove

Files from Project. 3. In the pop-up window select the (…) button to the right of File Name. 4. Change the “Files of Type” to (*.*) and add the .qsf file (there’s only one) to you project.

The name of the file should match your project name. 5. Click “Add” to add the file. 6. Click on the .qsf file in the Project Navigator window to open it. 7. Edit the line that reads:

set_global_assignment – name NOMINAL_CORE_SUPPLY_VOLTAGE 1.0V

8. Change the 1.0V to 1.2V and save the file. Now you can perform the lab. Construct the following circuit just as Dr. Khan does in the videos:

On the Lab website, navigate to THE LABORATORIES and LAB 2. From Files, you must copy the pin assignment file, DE2_115_pin_assignments.csv into the working directory of your project before programming the FPGA. In order to use the pin assignments in your project you MUST PERFORM ALL THREE OF THE FOLLOWING STEPS IN ORDER:

1. Copy the DE2_115_pin_assignments.csv file into your working directory.

2. ADD THE FILE TO YOUR PROJECT

3. LAST, Import the pin assignments from the file

***************************************************************************** NOTE: Not doing this correctly (or at all) is THE MOST COMMON REASON THAT A PROJECT DOES NOT WORK IN THE ENTIRE ECE 2000 LAB SERIES) *****************************************************************************

To program the FPGA, watch the following screencasts for Dr. Khan’s step by step instructions:

1. Programming the FPGA.mp4 2. Additional Information about Programmer.mp4

Don’t forget to make the following pin name changes when instructed to do so in the video:

X → SW[0]

Y → SW[1]

F → LEDG[0]

Checkpoint 1: Demonstrate your working XOR gate to the Lab Monitor.

Part 2: Half Adder

Start a new project called Hierarchy_Project and put it in its own folder. Your lab directory could look like the following screenshot.

Never nest two projects (i.e. do not put one project’s directory inside another projects directory).

Make a new block diagram called the half_adder and build the schematic of a half_adder shown below. Make the following pin name changes when instructed to do so in the video:

X → SW[0]

Y → SW[1]

S → LEDG[0]

C→ LEDG[1]

Compile the project. The shortcut icon is the purple arrow:

Program the board with the Half Adder. The shortcut icon looks like this:

Checkpoint 2: Demonstrate your working half_adder gate to one of the Lab Monitor.

Part 3: Full Adder

Keep working in the Hierarchy_Project. Make a new block diagram called full_adder Follow the screencast Hierarchy.mp4 and build full_adder as shown in the screencast. Set the full_adder as the Top Level Entity, compile, and program the FPGA. Use the following pin names substitutions for the full_adder:

X → SW[0]

Y → SW[1]

Cin→ SW[2]

S → LEDG[0]

Cout→ LEDG[1]

Checkpoint 3: Demonstrate your working full_adder gate to one of the Lab Monitor.

Part 4: 2-Bit Adder

A full_adder can be used to compute any column of a binary addition. The final step in building a binary adder is to connect multiple full_adders together. For this exercise, you will build a circuit that adds two 2-bit numbers (2-bit_adder). Keep working in the Hierarchy_Project. Build the circuit shown below in a new block diagram. Remember to set your new diagram as the Top Level Entity.

Import DE2_115_pin_assignments.csv into the pin assignments, compile, and program the FPGA on the DE2 board.

Checkpoint 4: Demonstrate your 2-bit adder to the Lab Monitor.

Part 5: Creating Symbol Files

Create a project (in a folder of the same name) and call it Symbol_File_Project. Once you have created the project, follow the process in the Make Symbol Files from VHDL Files.mp4. Add the VHDL file FirstTest.vhd to your project. You can find this file under Lab 2 on the course website by clicking on the ECE2060labs icon, located on your lab computer desktop. Once you have created a symbol file, use it to construct the following schematic.

Remember to add the pin assignment file DE2_115_pin_assignment.csv to the project. Compile and program the DE2 Board

The inputs are SW[0] and SW[1] and the output is LEDR[0]. Do the SW0 and SW1 switches and LED still behave like an XOR gate? ****************************************************************************** Note: If the switches and LEDs do not do anything, double check that the DE2 pin assignment file is 1) copied into the project folder, 2) added to the project, and 3) the pin assignments are imported. IN THAT ORDER.

******************************************************************************

Checkpoint 5: Demonstrate your functional XOR block to a Lab Monitor

Project 6: Using Megafunctions

Make a new folder and create a project called Megafunction_Project. Follow along with the screencasts Buses and Megafunctions.

**************************************************************************** WARNING: Make sure that you do NOT create component files outside of the current project. Use the directory selection inside the Wizard to select the current project. Accidentally creating an lpm component outside the project directory will introduce errors that can only be resolved by STARTING THE PROJECT OVER. Check the default directory every time as it sometimes changes. If the component is listed with: ..\ preceding the path name, it is certainly outside of the current project.

**************************************************************************** If you have followed the Buses and Megafunctions video correctly, your schematic should appear as follows:

Please use the naming conventions in this schematic. Continue by watching the In System Memory Constant Editor.mp4, and Signal Tap II Logic Analyzer.mp4 videos. Set up the Signal Tap II Logic Analyzer and in System Memory Editor as shown in the video.

Checkpoint 6: Demonstrate the In System Memory Content Editor and Signal Tap II Logic Analyzer to the lab monitor by changing values in the In System Memory Content Editor and re-sampling the results in Signal Tap II. The Lab Monitor will check that the numerical answer in Signal Tap II is correct for the inputs.

Checkpoint 7: Return your DE2 board to the cabinet. Turn off any benchtop equipment. Clean up your workbench and ask your lab monitor to check your area.

Discussion Questions:

Topic 1: Where should you create a project folder? Is it OK to create more than one project in a single folder?

Topic 2: The Cyclone IV E on the DE2 is an FPGA. What does FPGA stand for?

Topic 3: Is it necessary to have pin assignments before you can program the FPGA? What are the three steps, in order, that must be performed in order to use the pin assignments?

Topic 4: How do you select the file that you want to compile? What does it mean to declare a schematic as the top-level entity? What determines which file the compiler operates on?

Topic 5: When creating a megafunction, how can you tell where Quartus will create the megafunction files?

Topic 6: What is the advantage of using the In-System Memory Content Editor?

Topic 7: How do you enable the In-System Memory Content Editor when creating a LPM_CONSTANT or LPM_ROM?

Topic 8: Why do you have to recompile after setting up Signal Tap?

Topic 9: Where is the Signal Tap Logic Analyzer running, on the computer or on the FPGA?

Topic 10: How do you change the bus display format in Signal Tap?