Introduction to IC Test

Page 1EL/CCUT T.-C. Huang May 2004

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Introduction to IC TestIntroduction to IC Test

Tsung-Chu Huang(黃宗柱 )

Department of Electronic Eng.Chong Chou Institute of Tech.

Email: [email protected]

2004/05/10


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Syllabus & Chapter PrecedenceIntroduction

Modeling

Logic Simulation Fault Modeling

Fault Simulation

Testing for Single Stuck Faults

Test Compression

Built-In Self-Test

Design for Testability


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Built-In Self-Test (BIST)Objectives

1. To Reduce input/output pin signal traffic.2. Permit easy circuit initialization and observation.3. Eliminate as much test pattern generation as possible.4. Achieve fair fault coverage on general class of failure

mode.5. Reduce test time.6. Execute at-speed testing.7. Test circuit during burn-in.


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1. Area overhead2. Performance degradation3. Fault coverage4. Ease of Implementation5. Capability for system test6. Diagnosis capability

Built-In Self-Test (BIST)Issues


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Typical BIST Techniques

1. Stored Vector Based (Pattern Generated)1. Microinstruction support2. Stored in ROM

2. Algorithmic Hardware Test Pattern Generators1. Counter2. Linear Feedback Shift Register3. Cellular Automata4. FSM (ASM) Based

Design with BIST

Test Good (or Not)


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Classification1. Forms

1. Off-Line• Functional• Structural

2. On-Line• Concurrent

• Parallel• Pipeline• Asynchronous

• Non-concurrent

2. Level1. Production Testing2. Field Testing

3. TPG for BIST1. Exhaustive Testing2. Pseudo-random Testing

• Weighted • Adaptive

3. Pseudo-exhaustive Testing• Counter-Based: Syndrome, Constant-Weight• LFSR-Based: Shift/Scan, XOR, Condensed, Cyclic


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General BIST Architecture

CUT

CUT

CUT

ORATPG

ORATPG

CUT

CUT

ORATPG

ORATPG

ORATPG

DIST DIST

BISTC

CUT

ORATPG

DIST DIST

BISTC

Em

bedded

Separat

e

Centralized Distributed

TPG: Test Pattern Generator, ORA: Output Result AnalyzerCUT: Circuit under Test, BISTC: BIST Controller


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Specific BIST ArchitectureArchitecture Ref. Remark

CSBL Benowitz, 1975 Centralized & Separate Board-Level BIST

BEST Resnick, 1983 Built-In Evaluation and Self-Test

RTS Bardell, 1982 Random Test Socket

LOCST Eichelberger, 1983 LSSD On-Chip Self-Test

STUMPS Bardell, 1982 Self-Testing Using MISR and Parallel SRSG

CBIST Saluja, 1988 Concurrent BIST

CEBS Komanytsky, 1982 Centralized and Embedded BIST with Boundary Scan

RTD Bardell, 1987 Random Test Data

SST Gupta, 1982 Simultaneous Self-Test

CATS Burkness, 1987 Cyclic Analysis Testing System

CSTP Krasniewski, 1989 Circular Self-Test Path

BILBO Koenemann, 1979 Built-In Logic-Block Observation


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Specific BIST ArchitectureArchitecture Ref. Control Circuit On-line Boundary Scan

CSBL Benowitz, 1975 Centralized Separate V 　　BEST Resnick, 1983 Centralized Separate 　 V 　RTS Bardell, 1982 Distributed Separate 　 V LSSD

LOCST Eichelberger, 1983 Centralized Separate 　 V LSSD

STUMPS Bardell, 1982 Centralized Separate 　 V Multiple

CBIST Saluja, 1988 Centralized Separate V 　　CEBS Komanytsky, 1982 Centralized Embedded 　 V 　RTD Bardell, 1987 Distributed Embedded 　　　SST Gupta, 1982 Distributed Embedded 　　 No LFSR

CATS Burkness, 1987 Centralized Separate 　　　CSTP Krasniewski, 1989 Centralized Separate 　　　BILBO Koenemann, 1979 Distributed Embedded 　　　


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Specific BIST Architecture (1)CSBL

CUT(C or S)M

UX

MUX SISRCounterPRPG

n

k1

mn

m

1

PIs

POs

k m log2

1. Centralized and Separate Board-Level BIST [Benowitz 75]2. Use only one Signature Register3. Tests repeat m times to reduce hardware cost


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Specific BIST Architecture (2)Combinational Sequential

LFSR

Combinationalcircuit

SA

LFSR

Combinationalcircuit

SA

(Circular BIST)(BEST)

1. Pseudo random testing2. Hardware overhead is low3. Test length can be long for CUT with random-pattern

resistant faults.


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Specific BIST Architecture (3)RTS

CUT (S)

Sin SoutClocks Controls

PR

PG

MIS

R

SR

PG

R1 R3

R2S

ISR

R4

BIST controller

1. Combine LSSD Scan Chain and BIST2. Can insert scan points to reduce test length for random-

pattern resistant faults


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Specific BIST Architecture (4)LOCST

1. Boundary scan is required to unify the test architecture2. Single scan chain may cause high test time overhead.

CUT(S)

Si S0

SRSG

PIs

SRL

R1

SISR

POs

SRL

R2

On-chipmonitor(OCM) Error-detection circuitry

Sin

Sin

Error signalControl signals


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Specific BIST Architecture (5)CBIST

1. Detect test patterns from normal inputs sequence

2. Once a pattern is detected, compress the response and tick the test clock.

3. If waited too long, insert a test pattern from PRPG.

Comparator

PRPG

MUX N / T

N / T

Normal inputs

CUT(C)

MISR

Normal outputs

EN

CBIST Circuitry


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Specific BIST Architecture (6)

Circuit Under Test

Shift registerLFSR

SA

LFSR

SA

SR

SR

SR

CUT CUT

(CEBS) (STUMPS)Self-Testing using MISR & Parallel SRSGCentralized and Embedded BIST with BS

low cost version of RTS or LOCST


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Specific BIST Architecture (7)

LFSR

1/8 3/4 1/2 7/8 1/2

LFSR BasedWeighted Pseudo Random Test


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Specific BIST Architecture (8)SST

CUTCombinational

POPI1. Similar to MISR but

without LFSR part


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Specific BIST Architecture (9)HP Focus Chip (Stored Pattern)

1. Chip Summaries1. 450,000 NMOS devices, 300,000 Nodes2. 24MHz Clocks, 300K bits of on-chip ROM3. Used in HP9000-500 computer

2. BIST Micro-program1. Use microinstructions dedicated for testing2. 100K-bit BIST micro program in CPU ROM3. Executes 20 million clock cycles4. Greater than 95% stuck-at coverage5. A power-up test used in system test, filed test,

and wafer test


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Specific BIST Architecture (10A)Motivation of BILBO

Combinational Circuit

Di

Si

Dn

Ci

Normal

MISR

RPG

Scan


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Specific BIST Architecture (10B)Built-in Logic Block Observation (Koenemann ‘79)

Q

0

1

MU

X

Z1

QD

Q

Q1

Z2

D

Q

Q

Q2

...

...

...

D

Q

Qn-1

Zn

D

Q

Q

Qn

S0

...

Si

B2

B1

C1

BILBO1

BILBO2

C2

BILBO3

C3B1 B2 BILBO0 0 shift register0 1 reset1 0 MISR (inputconstantLFSR)1 1 parallel load (normal operation)


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Syllabus & Chapter PrecedenceIntroduction

Modeling

Logic Simulation Fault Modeling

Fault Simulation

Testing for Single Stuck Faults

Test Compression

Built-In Self-Test

Design for Testability


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VLSI TestingTheoretical Classification

• By Signals Modes:• Voltage Test

• Current Test

• By Signal Types: • Digital (Logic) Testing

• Analogue Testing


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IDDQ TestingBasic Concept

VDD

Current Sensor

IDD

IDD

t

IDD

t


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IDDQ TestingAdvantages

1. Can detect more physical defects including bridging defects.

2. The error response is easily detected by deep submicron era.

3. The ATPG is easily to design.4. The test size (pattern count) is usually small.5. Current test technology is sufficient.


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Types of IDDQ Test Architecture

ATEAutomatic Test Equipment

DUTDevice under Test

External Motoring

Test FixtureOff-Chip Current Monitor


Test Fixture

ATEAutomatic Test Equipment BICS

Built-In Current Sensor


Built-In Current Test

QTAG (Quality Test Action Group),1993


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Power Dissipation

• Static Power Dissipation

VDD

• Dynamic Power Dissipation • Switching Transient

(Short-circuit) Current

• Loading Dissipation(Charging/Discharging of CL)

VDD


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Power Dissipation

Pd

PscPs

Sub-micronMicronDeep-

submicron

Nano-meter

1m 80nmm

50%


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Power DissipationStatic Dissipation

• Quiescent State• Input steady for enough time

• Either P- or N- Network is off

• Theoretically, IDDQ→0

• However, small static dissipation due to

• Reverse bias leakage ISB

• Gate leakage

• Considerable in deep submicron era

Introduction to IC Test

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