1 Logic Synthesis TSRI 楊智喬 Email: [email protected]Outline Introduction to Cell-based Design Flow Logic Synthesis Introduction to Logic Synthesis Coding Style for Synthesis Static Timing Analysis Synopsys Design Compiler SDF and Gate-Level Simulation 2
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Introduction to HDL-based design methodologyviplab.cs.nctu.edu.tw/course/DCL2019_Fall/DCL_Mat_02.pdf · 3 Write HDL Code A Hardware Description Language (HDL) is a high-level programming
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Static Timing Analysis Determine the longest and shortest path between
register to register or register to IO boundary
Advantage: Exhaustive timing coverage, Does not require input vectors, More efficient than DTA in memory and CPU resources (Faster operation & Capacity for millions of gates)
Disadvantage: For synchronous logic only, Difficult to learn, Tricky constraints beyond the boundaries of single clock flip-flop design chips, Lack of consistent conventions
IN Q D
QN
Q D
QN
CLK
OUT
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Formal Verification
Model Checking determine if a design obeys behavioral characteristics
defined by the user, typically in the form of assertions or properties
Formal Equivalence Checking (EC) To verify the consistency of a design as it is transformed
from one level of abstraction to another, such as when a RTL design is synthesized into gates
To ensure that some modifies on the circuit will not change the functionality
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Physical Verification – DRC, ERC
DRC checks the layout geometries against fabrication rules.
width check
area check
outside spacing check
inside spacing check
enclosure spacing check
ERC checks for electrical violations such as open circuits, short circuits, or floating devices and nodes.