Introduction To Embedded System Design Embedded Systems Architecture : A Comprehensive Guide for Engineers and Programmers - An Elsevier Science Publication.

Introduction To Embedded System DesignIntroduction To Embedded System Design

Embedded Systems Architecture : A Comprehensive Guide for Engineers and Programmers- An Elsevier Science Publication

Name of University - Class Title


OverviewOverview What is an Embedded System? Embedded Systems Design

– Embedded Systems Design & Development Lifecycle Model

What is an Embedded Systems Architecture?– The 6 Stages of Creating an Embedded Architecture.

Stage 1 : Have a Strong Foundation– Know Your Standards

– Embedded Software Putting It All Together

– Stages 2-6 of Creating an Architecture


What Is An Embedded System ?What Is An Embedded System ?

A type of computer system. Some of the Most Common Traditional Definitions :

– Embedded systems are more limited in hardware and/or software functionality then the PC.

– An embedded system is designed to perform a dedicated function

– … Why don’t these definitions entirely apply, today?


What is an Embedded System [Continued]?What is an Embedded System [Continued]?

Automotive– i.e. : Ignition Systems, Engine Control, Antilock Braking System, …

Consumer Electronics– i.e. : TVs, STBs, appliances, toys, automobiles, cell phones …

Industrial Control– i.e. : robotics, control systems…

Medical– i.e. : Infusion Pumps, Dialysis Machines, Prosthetic Devices,Cardiac Monitors, …

Networking– i.e. : routers, hubs, gateways, …

Office Automation– i.e. : fax machines, photocopiers, printers, monitors, …

** Aside from being types of computer systems, there is no single definition or characterization of embedded systems reflecting them all. **


Embedded Systems DesignEmbedded Systems Design

Embedded Systems Design and Development Lifecycle Model

Product Concept

Preliminary Requirements Analysis

Creation of Architecture Design

Develop Version of Architecture

Deliver Version of Architecture

Review & Obtain Feedback

Incorporate Feedback

Deliver Final Version of Architecture

Develop [Implement] the System

Review and Test the System

Deliver & Maintain the System

Incorporate Feedback

Phase 1 : Creating The Architecture

Phase 2 : Implementing the Architecture

Phase 3 : Testing the System

Phase 4 : Maintaining the System


What is Embedded Systems Architecture?What is Embedded Systems Architecture?

• An abstraction of the embedded device that represents the

embedded system as some combination of interacting elements.- physically represented as structures

- many types of structures

• Layered, Kernel, Decomposition, Client/Server, Process, …

Sum of Structures = Embedded Architecture

• Why care about the architecture of an embedded system?


6 Stages of Creating an Embedded Architecture6 Stages of Creating an Embedded Architecture

Many industry popular methodologies for creating architectures (adaptable to embedded systems)– Rational Unified Process (RUP), Attribute Driven Design (ADD),

Object Oriented Process (OOP), … More Pragmatic Approach [the best of all worlds]

– Stage 1 : Having a Solid Technical Base

– Stage 2 : Understanding the ABCs of Embedded Systems

– Stage 3 : Defining the Architectural Patterns & Reference Models

– Stage 4 : Creating the Architectural Structures

– Stage 5 : Documenting the Architecture

– Stage 6 : Analyzing & Evaluating the Architecture

Stage 1 : Having a Strong Technical BaseStage 1 : Having a Strong Technical Base

Stanford University - EE109


Embedded Systems ModelEmbedded Systems Model

Hardware Layer

System Software LayerSystem Software Layer

Application Layer Application Layer

Embedded System


EE109 Platform and the Embedded Systems ModelEE109 Platform and the Embedded Systems Model

System LayerSystem Layer

Application LayerApplication Layer

Memory Memory Management Management DriversDrivers

HardwareHardware

Cypress EZ-USB FX-2Cypress EZ-USB FX-2 Xilinix FPGAXilinix FPGA 16 MB DRAM16 MB DRAM ........

......USB DriversUSB Drivers Interrupt DriversInterrupt Drivers

User InterfaceUser Interface ......CameraCameraApplicationApplication


Know Your StandardsKnow Your Standards

Market Specific – Consumer Electronics, Medical, Industrial Automation & Control, Networking &

Communications, Automotive, Aerospace & Defense, Office Automation, …

General Purpose – Networking, Programming Language, Security, Quality Assurance, …

Hardware LayerHardware Layer


Application Software Layer Application Software Layer Market SpecificStandards

MHP ATSCDTVHAViFDA …

General PurposeStandards

PJavaJ2MESSL128…

EthernetTCP/IPHTTP…


How can a Programming Language Spec Add to An Embedded System’s Architecture ?How can a Programming Language Spec Add to An Embedded System’s Architecture ?

Target [Embedded System]




Host [Development System]

CompilerCompiler Linker …Linker …PreprocessorPreprocessor



Application Layer

Translating Code– Interpretation, Just-in-Time (JIT), Way-Ahead-of-Time (WAT)/Ahead-of-Time (AOT)

Garbage Collection– Copying, Mark&Sweep, Generational, …


Translation of Code on Host : CompilingTranslation of Code on Host : Compiling

C Source File (s)

C Header File (s)

C Compiler

Preprocessing

Compiling

C Object File (s)

Linker

C Executable File

C System Libraries

Embedded System

Host Computer


Translation of Code on TargetTranslation of Code on Target

Source File (s)

Compiler

Byte Code File (s)

Source L1

Source L2

Source L3

Source L4

Source L5

Source L6

Target Code for Source L1



………….

vtab

Byte Code 1

Byte Code 2

Byte Code 3

….

Byte Code 1Parsing & Interpreting

Byte Code 1JIT

Compiling

Byte Code 2Parsing &

Interpreting

Byte Code 2JIT

Compiling

…

Compiled Byte Code 3

…



First Pass of Processing Byte Code

2nd and Additional Passes of Processing Byte Code

vtab

Byte Code 1

Byte Code 2

Byte Code 3

….

Byte Code 1Parsing

Byte Code 1Interpreting

Byte Code 2Parsing

Byte Code 2Interpreting

…

Interpretation

Interpretation

Just-In-Time [JIT]

JVM WAT Compiler.class File

Byte Code 1

Byte Code 2

Byte Code 3

….

object File

JVM Linker

Runtime Libraries

executables

1

2

Way-Ahead-of-Time/Ahead-Of-Time

[WAT/AOT]

Host


Garbage Collection : CopyingGarbage Collection : Copying

Copying Garbage CollectorCopying Garbage Collector

Memory Before GC

Object 1

Object 2

Object 3

Object 4

Memory After GC

Object 1

Object 2

Object 4


Garbage Collection : Mark&SweepGarbage Collection : Mark&Sweep

Mark & Sweep Garbage CollectorMark & Sweep Garbage Collector

[Mark]

Memory Before GC

Object 1

Object 2

Object 3

Object 4

Memory After GC

Object 1

Object 2

Object 4

[Sweep]


Garbage Collection : GenerationalGarbage Collection : Generational

Older Generation

Mark (Sweep) & Compact GC

Mark,Sweep, & Compact Garbage CollectorMark,Sweep, & Compact Garbage Collector

[Mark]

Memory Before GC

Object 1

Object 2

Object 3

Object 4

Memory After GC Mark & Sweep

Object 1

Object 2

Object 4

[Sweep]

Memory After GC Compaction

Object 1

Object 2

Object 4

[Compact]

Copying Garbage CollectorCopying Garbage CollectorMemory Before GC

Object 1

Object 2

Object 3

Object 4

Memory After GC

Object 1

Object 2

Object 4

Youngest Generation [Nursery]

Copying GC


How can Java Add to An Embedded System’s Architecture ?How can Java Add to An Embedded System’s Architecture ?

Embedded Java– Standards (pJava, J2ME, Embedded Java, …)– Processing Bytecode (Interpretation, JIT, WAT/AOT)– Garbage Collection (Copying, Mark&Sweep, …)

JVM part of System layeri.e. : Skelmir’s Cee-J, Esmertec/Insignia’s Jeode and Jbed,

Tao’s Intent, Kava’s KavaVM …

JVM in Hardwarei.e. :

ARM’s Gazzelle, AJile’s aj100,…JVM compiled in application

i.e. Esmertec’s Jbed, Kava’s KavaVM, IBM’s J9 …




JVMJVM


SystemSystem Software LayerSoftware Layer



System System Software LayerSoftware Layer


Java ProcessorJava Processor

Java DeviceJava DeviceDriversDrivers

JVMJVM


How can .NetCE Add to An Embedded System’s Architecture ?How can .NetCE Add to An Embedded System’s Architecture ?

.NetCE Compact Framework– Standard = Common Language Specification– Processing Bytecode (Interpretation/JIT)– Garbage Collection ( Generational)


CLRCLR

[JIT] Execution Engine

BCL/Platform Extension Libraries

Application LayerApplication LayerMSIL Application

Class LoaderClass Loader

.NET Compact Framework

GC

Hardware LayerHardware LayerMemory


How can Scripting Languages Add to An Embedded System’s Architecture ?How can Scripting Languages Add to An Embedded System’s Architecture ?

Scripting Languages– Perl, JavaScript, HTML, …– Processing Bytecode (Interpretation)


Application Software LayerApplication Software Layer

Browser

Real AudioReal AudioHTML4.0HTML4.0 DOM 0DOM 0

SSL 128 Bit EncryptionSSL 128 Bit Encryption CSS 1 …CSS 1 …Java ScriptJava Script HTTPHTTP



How can Networking Add to an Embedded System’s Architecture ?How can Networking Add to an Embedded System’s Architecture ?

Network 2 – Client/Server ArchitectureNetwork 1 – Peer-to-Peer Architecture

Client AClient A

Networking ComponentsNetworking Components

Client BClient B


Server Server


Client CClient C


Device ADevice A


Device BDevice B


Device CDevice C


Transmission Medium

Distance

Network ‘s Overall Structure


Open Systems Interconnection (OSI) ModelOpen Systems Interconnection (OSI) Model



Application Software Layer Application Software Layer

Physical LayerPhysical Layer

Data-Link LayerData-Link Layer

Network LayerNetwork Layer

Transport LayerTransport Layer

Session LayerSession Layer

Presentation LayerPresentation Layer


OSI Model


Networking LayersNetworking Layers

Transmission Medium

Layer 7

Layer 1 Physical Layer

Data Link Layer

Network Layer

Transport Layer

Session Layer

Presentation Layer

Application Layer Layer 7

Layer 1Physical Layer

Data Link Layer

Network Layer

Transport Layer

Session Layer

Presentation Layer

Application Layer

Data

DataHeader 2

DataHeader 1

DataHeader 3

DataHeader 4

DataHeader 5

Data

Application

Presentation

Session

Transport

Network

Data Link

Physical


OSI and Real-World Networking Models : TCP/IPOSI and Real-World Networking Models : TCP/IP

Hardware Layer


Network Access LayerNetwork Access Layer

Internet LayerInternet Layer


Application Software LayerApplication Software LayerApplication LayerApplication Layer

TCP/IP Model








OSI Model


OSI and Real-World Networking Models : WAPOSI and Real-World Networking Models : WAP

Hardware Layer










OSI Model

Transaction LayerTransaction Layer



WAP Model

Security LayerSecurity Layer



OSI and Real-World Networking Models : BluetoothOSI and Real-World Networking Models : Bluetooth

Hardware Layer



Transport Protocol Group Transport Protocol Group

Middleware Protocol GroupMiddleware Protocol Group

Application Protocol GroupApplication Protocol Group

Bluetooth Model








OSI Model

TCP/IPTCP/IP

WAPWAP


OSI Layer 1 : Physical LayerOSI Layer 1 : Physical Layer




WANWAN

WirelessWireless

CDMACDMA

TDMATDMA

EIA/TIA 232 (RS-232)EIA/TIA 232 (RS-232)

ATM (SONET,…)ATM (SONET,…)

WiredWired

LANLAN

WirelessWireless WiredWired

IEEE802.11 Wireless Radio & IRIEEE802.11 Wireless Radio & IR

Bluetooth Radio and BroadbandBluetooth Radio and Broadband

IEEE 802.3 EthernetIEEE 802.3 Ethernet

IEEE 802.5 Token RingIEEE 802.5 Token Ring

ARCnetARCnet

FDDIFDDI……

TDMATDMA

GPRSGPRS

GSMGSM

CPDPCPDP

……

……


X.21X.21


……


Device 1 Device 2

Physical Layer ProcessingPhysical Layer Processing

Transmission Medium

Layer 1 Physical Layer

Data Link Layer

1001

1101

0111

0

Layer 2

Layer 2


Data Link Layer

0111

0101

1100

1


OSI Layer 2 : Data-Link LayerOSI Layer 2 : Data-Link Layer

Hardware Layer Hardware Layer


System Software LayerSystem Software Layer WANWAN

WirelessWireless

PPPPPP

NSNSX.25 PSTN LAPBX.25 PSTN LAPB

PPPPPP

WiredWired

LANLAN

WirelessWireless WiredWired

IEEE 802.3 EthernetIEEE 802.3 Ethernet

IEEE 802.5 Token RingIEEE 802.5 Token Ring

ARCnetARCnet

BSSGPBSSGP

RFCOMMRFCOMM

……

……

HDLCHDLC

SLIPSLIP

ATMATM

……

IEEE 802.2 LLC/SNAP

Physical Layer

IEEE802.11 MACIEEE802.11 MAC

Bluetooth LMP, L2CAP, Baseband …Bluetooth LMP, L2CAP, Baseband …

……

IEEE802.2 LLC/SNAPIEEE802.2 LLC/SNAP

FDDIFDDI


Data-link Layer ProcessingData-link Layer Processing

Layer 3Network Layer


Data Link Layer

Layer 2

Dat

agra

m

1110

1110

0011

01

Data-link Headers Stripped

[data]

Data-Link Headers Appended to Data Field

DataLink Frame 110110101101110111011101110001100111000001100101000111[Start of frame] [source addr][dest addr][admin][data] [ error chk][end of frame]


OSI Layer 3 : Network LayerOSI Layer 3 : Network Layer


System Software Layer System Software Layer

ISDNISDN ……..

Data-link Layer

Physical Layer

RIPRIP

IPIP

BGPBGP ……OSPFOSPF ICMPICMP

TCP/IP Stack

VIPVIP

……RTPRTP ICPICP

Banyan/VINES

BSSMAPBSSMAPBSSAPBSSAPSCCPSCCP

GPRS



Network Layer ProcessingNetwork Layer Processing

Layer 4Transport Layer

Layer 2Data-link Layer

Network Layer

Layer 3

Pac

ket

Network Headers Stripped

[data]

Network Header Appended to Data Field

Network Datagram11011011001101110001100001101101110111011101110001100111000001100101000111[IP Version] [header len][data type][data len][frag info] [# hops][upper layer][checksum][source IP][dest IP][data]

Dat

agra

m


OSI Layer 4 : Transport LayerOSI Layer 4 : Transport Layer




Data-link Layer

Physical Layer

Network Layer

UDPUDPTCPTCP ……

TCP/IP Stack

DTAPDTAPBSSMAPBSSMAP ……

GSM WAP

WDPWDP ……


Transport Layer ProcessingTransport Layer Processing

Layer 5Session Layer

Layer 3Network Layer

Transport Layer

Layer 4

Mes

sage

/Psc

ket

Transport Headers Stripped

[data]

Transport Header Appended to Data Field

TCP Packet11011011001101110001100001101101110111011101110001100111000001100101000111[Src Port][Dest Port][Seq #][Ack #][H Len][Res][Uflag][Pflag][Rflag][Sflag][Fflag][WinSz][Chksum][UP[O] [Data]

Pac

ket


OSI Layer 5 : Session LayerOSI Layer 5 : Session Layer



Data-link Layer

Physical Layer

Network Layer

Transport Layer


NFSNFSDNSDNS ……

TCP/IP Stack WAP Stack

WSPWSP ……

……


Session Layer ProcessingSession Layer Processing

Layer 6Presentation Layer

Layer 4Transport Layer

Session Layer

Layer 5 M

essa

ge

Session Headers Stripped

[data]

Session Header Appended to Data Field

L2CAP Packet1101101100110111000110000110[Length][Destination Channel ID][Data]

Mes

sage

/Pac

ket


OSI Layer 6 : Presentation LayerOSI Layer 6 : Presentation Layer



Data-link Layer

Physical Layer

Network Layer

Transport Layer


MIDIMIDIJPEGJPEG ……

Session Layer

SSLSSL MPEGMPEG


Presentation Layer ProcessingPresentation Layer Processing

Layer 7Application Layer

Layer 5Session Layer

Presentation Layer

Layer 6

Mes

sage

[data]

Presentation Header Appended to Data Field

Bluetooth Message1101101100110111000110000110[Length][Destination Channel ID][Data]

Mes

sag

e

Message conversion


OSI Layer 7 : Application LayerOSI Layer 7 : Application Layer




Data-link Layer

Physical Layer

Network Layer

Transport Layer

IMAP4IMAP4POP3POP3 HTTPHTTP

Session Layer

SMTPSMTP FTPFTP

Presentation Layer

……

TelnetTelnet

BootpBootp SNMPSNMP RLOGINRLOGIN

MIMEMIME NFSNFS

FingerFinger

NCPNCP APPCAPPC BT-SDPBT-SDP

Embedded HardwareEmbedded Hardware



Many Many ManyMany Many Many Embedded Processors To Choose FromEmbedded Processors To Choose From

Architecture Processor Manufacturer

AMD Au1xxx Advanced Micro Devices,…

ARM ARM7, ARM9, … ARM, …

C16X C167CS, C165H, C164CI,… Infineon,…

ColdFire 5282, 5272, 5307, 5407, … Motorola,…

I960 I960 Vmetro, …

M32/R 32170, 32180, 32182, 32192, … Renesas/Mitsubishi, …

M Core MMC2113, MMC2114, … Motorola

MIPS32 R3K, R4K, 5K, 16, … MTI4kx, IDT, MIPS Technologies, …

NEC Vr55xx, Vr54xx, Vr41xx NEC Corporation, …

PowerPC (PPC) 82xx, 74xx,8xx,7xx,6xx,5xx,4xx IBM, Motorola,…

68k 680x0 (68K, 68030, 68040, 68060,…) ,683xx Motorola, …

SuperH (SH) SH3 (7702,7707, 7708,7709), SH4 (7750) Hitachi, …

SHARC SHARC Analog Devices, Transtech DSP, Radstone, …

strongARM strongARM Intel, …

SPARC UltraSPARC II Sun Microsystems, …

TMS320C6xxx TMS320C6xxx Texas Instruments, …

x86 X86 [386,486,Pentium (II, III, IV)…] Intel, Transmeta, National Semiconductor, Atlas, …

TriCore TriCore1, TriCore2, … Infineon,…

… … …


ISA ModelsISA Models

Application Specific – Controller– Datapath– Finite State Machine with Datapath [FSMD]– Java Virtual Machine– ….

General Purpose – Complex Instruction Set Computing [CISC]– Reduced Instruction Set Computing [RISC]

Instruction Level Parallelism – Single Instruction Multiple Data [SIMD]– Superscaler Machine– Very Long Instruction Word (VLIW) Computing– ….


Implementing an ISA & Von-NeumannImplementing an ISA & Von-Neumann

data from cpu or input devices stored inmemory until a cpu or output device request

controls usage and manipulation of data

Master Processor

Memory

OutputInputbrings data into the embedded system gets data out of the embedded system

5 system components commonly connected via buses

embedded system board

Output Input

Memory

CPU

Embedded SoftwareEmbedded Software



Embedded Software : The System Software LayerEmbedded Software : The System Software Layer




Device Driver LayerDevice Driver Layer





Operating System LayerOperating System Layer





Middleware LayerMiddleware Layer



Board Support Package Layer Board Support Package Layer

Device DriversDevice Drivers












Operating System Layer Operating System Layer

MiddlewareMiddleware






















……………………

Name of University - Class TitleWhat are Device Drivers?What are Device Drivers?

Hardware Layer

System Software Layer

Application Layer

Device Drivers

I/O

Ethernet (SCC1)

RS-232 (SMC2)

Buses Memory …

PCMCIA

…

I2C

DMA (IDMA) Interrupts

T1/E1 (TDM)

ISDN (TDM)

…

MMU

L1 Cache

Timers

…

Generic (Architecture and Board Specific Driver) Architecture Specific Device Drivers





rr

Higher-layer InterfaceHigher-layer Interface----------------------------------------------Hardware Interface

Higher-layer InterfaceHigher-layer Interface

Hardware Interface


Most Common Types of Device Drivers RoutinesMost Common Types of Device Drivers Routines

Hardware Startup, initialization of the hardware upon power-on or reset. Hardware Shutdown, configuring hardware into its power-off state. Hardware Disable, allowing other software to disable hardware on-the-fly. Hardware Enable, allowing other software to enable hardware on-the-fly. Hardware Acquire, allowing other software gain singular (locking) access

to hardware. Hardware Release, allowing other software to free (unlock) hardware. Hardware Read, allowing other software to read data from hardware Hardware Write, allowing other software to write data to hardware Hardware Install, allowing other software to install new hardware on-the-fly Hardware Uninstall, allowing other software to remove installed hardware

on-the-fly


Embedded Operating SystemsEmbedded Operating Systems Process Management.

– Process Implementation– Scheduling– Intertask Communication & Synchronization

• Interrupt Handling, Error Detection, …

– …

Memory Management. – Segmentation– Paging– Virtual Memory– System Security – …

I/O System Management. – File System– …

Embedded OSEmbedded OS

Middleware (optional) Middleware (optional)

Device Drivers (Optional)Device Drivers (Optional)

Kernel Kernel

Memory ManagementMemory ManagementProcess Management Process Management

I/O System ManagementI/O System Management Interrupt/Error Handling Interrupt/Error Handling

Security System Management Security System Management


OS ModelsOS Models

Hardware

Monolithic Kernel

I/O DriversMemory Drivers

InterruptDrivers

file I/O Memory ManagementProcess

Management

Higher-level Software (Middleware, Applications)

The Operator The Operator

User Program User Program

Operator Process CommunicationOperator Process Communication

Input/Output Management Input/Output Management

Memory & Drum Management Memory & Drum Management

Processor Allocation and MultiprogrammingProcessor Allocation and Multiprogramming

Layered OS

Layer 5

Layer 4

Layer 3

Layer 2

Layer 1

Layer 0

Device Drivers

Hardware

Microkernel

I/O Memory Interrupt

Memory ManagementProcess

Management

Higher-level Software (Middleware, Applications)


Process ManagementProcess Management

What is a process?

Tasks vs. Threads

Program 1 OS

Task Program 1Task RegistersTask Stack

Program 1

Program 2

…

OS(ie:..)

Task 1Program 1Task 1 RegistersTask 1 Stack



Thread 1Program 1Thread 1 Registers



Memory


Unitasking vs. Multitasking OSesUnitasking vs. Multitasking OSes

Program 1

Program 2

…

MultitaskingOS


Process 2Program 1Task 2 RegistersTask 2 Stack

Process 3Program 2Task 3 RegistersTask 3 Stack

Program 1Unitasking

OS

Task Program 1Task RegistersTask Stack


The OS Multitasking IllusionThe OS Multitasking Illusion

OS

How? – Implementation– Scheduling– Synchronization– Inter-task Communication


Process Implementation & the Task HierarchyProcess Implementation & the Task Hierarchy

OS Initial Task

Task Task Task

Task Task Task Task

Task Creation Task Deletion Task Suspension Task Resumption


Task Creation and Fork/ExecTask Creation and Fork/Exec

<< Task creation based upon “fork/exec” involve 4 major steps >>

fork System Call

1. Parent task makes fork system call to create child task

Memory

Parent Task TCB TCB TCBProcess Table

Parent Task

stack Parent Program

Memory

Child Task TCB TCB TCBProcess Table

Parent Task


Child Task [Parent Task Clone]


exec System Call

3. Parent task makes exec system call to load child task’s program

Memory

Child Task TCB TCB TCB

Parent Task


Child Task

stack Child Program

4. The child task program loaded into memory.


Task Creation & SpawnTask Creation & Spawn<< Task creation based upon “spawn” involve 2 major steps >>

Spawn System Call

1. Parent task makes spawn system call to create child task

2. Child Task loaded into memory, including program, TBC, stack, etc.

Memory

Child Task TCB TCB TCB

Memory

Parent Task TCB TCB TCBProcess Table

Process Table

Parent Task


Parent Task


Child Task

stack Child Program


Task DeletionTask Deletion System Call

Garbage Collection

I

1

32

4


Resuming & Suspending Tasks : Resuming & Suspending Tasks : Task StatesTask States

3 Main States– Ready : The process is ready to be executed at anytime, but is waiting for permission to use the CPU. – Running : The process has been given permission to use the CPU, and can execute. – Blocked or Waiting: The process is waiting for some external event to occur before it can be “ready”

to “run”.

Task States and Queues


Process State Transition ModelsProcess State Transition Models

When a task that is moved from one of the queues (READY or BLOCKED/WAITING) into the RUNNING state, it is called a context switch.

Name of University - Class TitleScheduling in OSesScheduling in OSes

Non-preemptive Schedulers– First-Come-First-Serve (FCFS)/ Run-To-Completion

– Shortest Process Next [SPN]/ Run-To-Completion

– Co-operative

TN …….. T3 T1T2 Scheduler Master CPUT1 T2

Current Task

No Context Switching After This Point

TN …….. T3 T1T2 Scheduler Master CPUT2 T1 T3

Current Task

Time T1 = 10ms Time T3 = 2msTime T2 = 20 ms

TN …….. T3 T1T2 Scheduler Master CPUT1 T2

Current Task

Only Running Task can force a context switch before completion


Scheduling in OSes [Continued]Scheduling in OSes [Continued]

Preemptive Schedulers– Round Robin/FIFO (First-in-First out) Scheduling

Priority

Time

HIGH

LOW

KEY

= preemption

| = task completion

Task 1 Task 2 Task 3 Task 2Task 1 Task 3

Time slice



Preemptive Schedulers [Continued]– Priority [Preemptive] Scheduling

Priority

Time

HIGH

LOW

KEY

= preemption

| = task completion

Task 1

Task 2

Task 3

Task 2

Task 1



Preemptive Schedulers [Continued]– EDF (Earliest Deadline First)/Clock Driven Scheduling

What is an RTOS? – A preemptable kernel!– Deterministic

r

p2 p3p1

p2 p3q p1p1

r

p2 p3q p1p1 r

admit r?


Intertask Communication & SynchronizationIntertask Communication & Synchronization

Memory Sharing

Message Passing

Signaling – Interrupt Handling

Memory

Shared Data

Process 1

Process 2

Process N


Memory ManagementMemory Management User vs. Kernel Memory Space User Memory Space Divided Into Partitions

– Segments– Pages– What is Virtual Memory?

User Memory Allocation and Deallocation Scheme Depends on Programming Language


What is a BSP [Board Support Package] ?What is a BSP [Board Support Package] ?


Middleware & Application SoftwareMiddleware & Application Software




Video-On-Demand Video-On-Demand

e-mail e-mail

browser browser

Web server Web server Navigation Navigation






Middleware ExamplesMiddleware Examples

NetworkingMiddleware

Hardware Layer

System Software Layer

Application Software Layer








OSI Model

Hardware Layer


pJava 1.1.8 JVMpJava 1.1.8 JVMjava.net Socket API


IPIP

TCPTCP UDPUDP


Application Layer ExamplesApplication Layer Examples




… … HTTP HTTP FTPFTP




JVMJVM




Browser Real AudioReal AudioHTML4.0HTML4.0 DOM 0DOM 0

SSL 128 BitSSL 128 Bit EncryptionEncryption CSS 1CSS 1

Java ScriptJava Script HTTPHTTP

Putting It All TogetherPutting It All Together



6 Stages Creating An Embedded System’s Architecture6 Stages Creating An Embedded System’s Architecture

Stage 1 Having a solid technical base [Software & Hardware]

Stage 2 Understanding the ABCs of Embedded Systems

Stage 3 Defining the architectural patterns & reference models

Stage 4 Creating the architectural structures Stage 5 Documenting the architecture Stage 6 Analyzing and evaluating the

architecture.


Stage 2 : Understanding the ABCs [Architecture Business Cycles] of Embedded SystemsStage 2 : Understanding the ABCs [Architecture Business Cycles] of Embedded Systems

Influences on Architecture

ArchitectureArchitecture

System Stakeholders

Technical Requirements

Engineers

Managers

Customers

….

Sales & Marketing Requirements

Quality Assurance Requirements

Industry Standard Requirements

……

Embedded SystemEmbedded System

ArchitectureBusiness Cycle


What are General ABC Requirements?What are General ABC Requirements?

- Business (Sales & Marketing) : sellability (how the device will sell), time-to-market (when will the device be delivered), costs (development, overhead, etc.), device lifetime (how long the device will be available on the market), target market (what type of device it is), schedule & features (schedule of versions to be released with associated features), etc.

- Technical : performance, user friendliness (usability), modifiability (how simple it is to modify the various functional elements), security, reliability, portability, testability, availability, technical industry standards (see industry standards below), etc.

- Industry : typically are a result of industry standards (introduced at start of presentation), which

may be market specific (i.e. TV standards, medical device standards, etc.) or general purpose across different families of devices (programming language standards, networking standards, etc.)

- Quality Assurance : testability (how easily the system can be tested), availability (when the

system is available for testing), schedule & features (schedule of versions to be tested with associated features), QA industry standards (ie : ISO9000, ISO9001, and so on – see industry requirements above), etc.

….


Performance ScenerioPerformance Scenerio

Internal Stimulus Sources (other internal system elements)

External Stimulus Sources(user, data over network, etc.)

Performance Stimuli(periodic events, one-time events, etc.)

Effected Element(Entire Embedded System)

System Response(events processed in timely manner, etc)

Environment(normal, high network traffic, etc.)

System Response Measures(throughput, latency, data loss, etc.)


How to Derive System Components from Performance Requirements?How to Derive System Components from Performance Requirements?



Performance Stimuli(periodic events, one-time events, etc.)

Embedded System

System Response(events processed in timely manner, etc)

System Response Measures(throughput, latency, response timedata loss, etc.)

Tactic : Resource Management

Requests Arbitration ……

Operating System

- Process events concurrently reducing response times-Scheduler manages requests and arbitration of resources to events-….

response time decrease


Security ScenerioSecurity Scenerio

External Stimulus Sources(user, data over network, etc.) Security Stimuli

(system shutdown, altering data, copying data, etc.)

Effected Element(Data in Memory of Embedded System, other accessible system

services)

System Response(recovering, detecting, resisting attacks, etc)

Environment(normal, connected/disconnected to network, data

uploads/ downloads, etc.)

System Response Measures(latency in system recovery, effectiveness of system

fix for previously encountered stimuli,etc.)


How to Derive System Components from Security Requirements?How to Derive System Components from Security Requirements?

External Stimulus Sources(user, data over network, etc.) Security Stimuli

(system shutdown, altering data, copying data, etc.)

Embedded System

System Response(recovering, detecting, resisting attacks, etc)

System Response Measures(latency in system recovery, effectiveness of system

fix for previously encountered stimuli,etc.)

Tactic : Managing Resource Access

Authentication Authorization ……

Operating System

- Memory Management- Security Management-….

fewer security breeches

Java [JVM]

- Garbage Collector- Cryptography- Authentication- Authorization- Security “Sandbox”-….


Testability ScenerioTestability Scenerio



Testability Stimuli(hardware/software completed, hardware/software update, etc.)

Effected Element(Some or all software/hardware

elements within Embedded System) System Response(easily controlled and observable

responses to tests, , etc)

Environment(development, production, in field, etc.)

System Response Measures(testing times, number of tests

performed, accuracy of tests, etc.)


How to Derive System Components from Testability Requirements?How to Derive System Components from Testability Requirements?

Embedded System

Tactic : Internal Monitoring

Visibility Accessibility ……

Processor

- Built-In Monitor

easier testing

Debug System Software Subroutines

- Manipulate Variables- Memory Dumps- Single-step through executing code ….



Testability Stimuli(hardware/software completed, hardware/software update, etc.)

System Response(easily controlled and observable

responses to tests, , etc)

System Response Measures(testing times, number of tests

performed, accuracy of tests, etc.)


Stage 3 : Stage 3 : Defining the Architectural Patterns & Reference ModelsDefining the Architectural Patterns & Reference Models

Create the system profile Make a matrix to determine if

components meet cost, time-to-market, performance ... requirements

Requirement 1 Requirement 2 Requirement 3 Requirement … Requirement “N”

Product 1 YES Features …

NO NOT YETNext Year

… …


YES Features …

YES Features …

… …

Product 3 NO YES Features …

NO … …


NOT YETIn 3 Months

NOT YETIn 6 Months

… …

Product … …. …. …. …. …

Product “N” … … … … …


Selecting a Programming LanguageSelecting a Programming Language

Real-Time Fast Performance MHP-Spec ATVEF-Spec Browser Application …

Assembly YES YES NOT Required NOT Required NOT Required …

C YES YESSlower then assembly

NOT Required NOT Required NOT Required …

C++ YES YESSlower then C


.NetCE (C#) NOWinCE NOT RTOS

Depends on processor, slower then C on less powerful processors


JVM (Java) Depends on JVM’sGarbage Collector and is OS ported to is RTOS

Depends on JVMs byte code processing scheme (WAT almost as

fast as C where interpretation requires more powerful processor i.e. 200+

MHz), slower then C on slower processors

YES NOT Required NOT Required …

HTML (Scripting) Depends on what language written in, and the OS (an RTOS in C/assembly OK, .NetCE platform no, Java depends on JVM

Slower because of the interpretation that needs to be done but depends on what language interpreter written in

(see above cells of this column)

NOT Required YES YES …

… … … … … … …


Selecting an OSSelecting an OS Questions to ask :

– 1. What type of systems typically use or require an OS?

– 2. Is an OS needed to fulfill system requirements? – 3. What is needed to support an OS in a design? – 4. How to select the OS that best fits the requirements?

Tools Portability Non-kernel Processor Scheduling Scheme …

vxWorks Tornado IDE, SingleStep debugger, …

BSP Device Drivers w/ BSP, graphics, networking, …

x86, MIPS, 68K, ARM,

strongARM, PPC …

Hard Real-Time, Priority-based …

…

Linux Depends on vendor for development IDE, gcc, …

Depends on vendor, some with no BSP

Device Drivers graphics, networking, …

Depends on vendor

(x86, PPC, MIPS, …)

Depends on vendor, some are hard real-time, others soft-

real time …

…

Jbed Jbed IDE , Sun Java compiler, … BSP Device Drivers – the rest depends on JVM specification (graphics,

networking, …)

PPC, ARM, … EDF Hard Real Time Scheduling …

…

… … … … … … …


Selecting a Master ProcessorSelecting a Master Processor Tools Java-specific

FeaturesOS Support …

aJile aj100 Java Processor (Application Specific ISA) JEMBuilder, Charade debugger,

J2ME/CLDC JVM NOT Needed …

Motorola PPC823 (General Purpose ISA) Tornado tools, Jbed Tools, Sun tools, Abatron BDM…

Implemented in software (Jbed,

PERC, CEE-J, …)

Coming Soon -- Linux, vxWorks,

Jbed, Nucleus Plus, OSE, …

…

Hitachi Camelot Superscaler SoC(Instruction Level Parallel ISA) Tornado Tools, QNX Tools, JTAG, …

Coming Soon --Implemented in software (IBM,

OTI, Sun VMs ..)

Coming Soon --QNX, vxWorks,

WinCE, Linux, ....

…

… … … … …

Select processor on requirements and its impact on the remainder of the system (especially software).

Why ?– The master processor essentially impacts what enhancements are

implementable in software, and what constraints are placed upon the software


Stage 4 : Define the Architectural StructuresStage 4 : Define the Architectural Structures

“4+1” Model

Logical Process Development Deployment

Module Component & Connector

Allocation

Validation - Logical Scenarios - Process Scenarios - Development Scenarios - Deployment Scenarios


Stage 5 : Document the ArchitectureStage 5 : Document the Architecture

Step 1 : A document outlining the entire architecture. Step 2 : A document for each structure.

Step 3 : An architecture glossary.

UML Sequence Diagram UML Use Case Diagram

User Embedded Device

…….

User opens application via user interface

OS task spawned loading application into memory and begins to execute

User selects option X in application

Rough/Informal Sequence Diagram


Stage 6 : Analyze and Evaluate ArchitectureStage 6 : Analyze and Evaluate Architecture

Step 1- Members of the evaluation team obtain copies of the architecture documentation from the responsible architect (s), and it explained to the various team members the evaluation process, as well as, the architecture information within the documentation to be evaluated.

Step 2 - A list of the architectural approaches and patterns is compiled based upon feedback from the members of the evaluation team after they have analyzed the documentation.

Step 3 – The architect (s) and evaluation team members agree upon the exact scenarios derived from the requirements of the system (the team responding with their own inputs of the architect’s scenarios : changes, additions, deletions, etc.), as well as, the priorities of the various scenarios are agreed upon in terms of both importance and difficulty of implementation.

Step 4 - The (agreed upon) more difficult and more important scenarios are where the evaluation

team spends the most time on evaluating, because these scenarios introduce the greatest risks.

Step 5 – Results of evaluation team should include (at the very least) the 1) uniformly agreed upon list of requirements/scenarios, 2) benefits (i.e. the ROI – Return-On-Investment aka. the ratio of benefit to cost), 3) risks, 4) strengths, 5) problems, and 6) any of the recommended changes to the evaluated architectural design.

Introduction To Embedded System Design Embedded Systems Architecture : A Comprehensive Guide for Engineers and Programmers - An Elsevier Science Publication.

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