Slide 1 Loke, Wee & Pfiester Agilent Technologies Introduction to Deep Submicron CMOS Device Technology & Its Impact on Circuit Design Alvin L.S. Loke, Tin Tin Wee & James R. Pfiester Agilent Technologies, Fort Collins, CO IEEE Solid-State Circuits Society December 8, 2004
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Introduction to Deep Submicron Cmos Devicw Tech & Its Impact on Ckt Design
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Slide 1Loke, Wee & PfiesterAgilent Technologies
Introduction to Deep Submicron CMOS Device Technology
& Its Impact on Circuit Design
Alvin L.S. Loke, Tin Tin Wee & James R. PfiesterAgilent Technologies, Fort Collins, CO
IEEE Solid-State Circuits SocietyDecember 8, 2004
Slide 2Loke, Wee & PfiesterAgilent Technologies
Outline• CMOS Technology Trends• MOSFET Basics• Deep Submicron FET Fabrication Sequence• Enabling Technologies• Second-Order Consequences• Dealing with Process Variations in Manufacturing• Conclusions
Disclaimer• A proper introduction alone would take weeks,
let alone a whole semester• Need to omit lots of nitty-gritty yet important process
details • Hopefully, we’ll still learn lots of cool device physics � � � � � � � �
Slide 3Loke, Wee & PfiesterAgilent Technologies
Source: Thompson et al., Intel (2002)
Where is CMOS Technology Today?• Scaling is still alive & well
• 130nm now standard fare• 90nm already in volume manufacturing• 65nm integration tough but not insurmountable
• Some key trends:• Aggressive scaling of gate CD (critical dimension)• Scaling driven by exclusively by digital circuit needs
Source: Wu et al., TSMC (2002)
90nm Technology
59nm59nm
Slide 4Loke, Wee & PfiesterAgilent Technologies
Why Aggressive FET Scaling?
• The road to higher digital performance• Cload↓ � reduce parasitics (largely dominated by interconnect now)• ∆V ↓ � reduce VDD or logic swing, need for core & I/O FET’s• IFET ↑ � all about moving charge quickly
• Hiccups along the way• Interconnect scaling much more difficult than
anticipated, especially Cu/low-K reliability• FET leakage doesn’t go well with VDD scaling
tdelay ≈ Cload ∆VIFET
Idsat ≈ ½ µCox (W/L) (VGS - VT)2
• How to beef up IFET?• Tweak with µ, Cox, L & VT
• Technology upgrades not necessarily compatible with analog design
Stress-Induced Voiding
Got redundant vias?
Slide 5Loke, Wee & PfiesterAgilent Technologies
The Most Basic MOS Concept – VT
• VT = FET ON voltage, i.e., gate voltage required to form inversion layer connecting source & drain; shorts out back-to-back pn-junctions with substrate
VT = VFB + 2φb +Qdep
Cox
φb = lnNA
ni
kBTq
p-substrate
–
–
–
–
–
– –
– –
––
+ + + + + + + + + + + + + + + +
– – – – –
Qdepdepletioncharge
n– inversion layer
poly gate
n+
sourcen+
drain
siliconsurface + + + + + + + + + + + + + + +
– – – – –– – – – –– – – – –
flatband (offset) voltage due to oxide charge & work function difference oxide capacitance
per unit area = εox / tox
bulk potential
depletion charge per unit area = qNAxdep ∝ NA (xdep ∝1/ NA)
Remember ∇∇∇∇ • E = ρ / ε ?
Slide 6Loke, Wee & PfiesterAgilent Technologies
More MOS Fundamentals (Energy Band Diagram)Formation of Inversion Layer
VT = gate voltage required to reverse doping of silicon surface, i.e., move φs by 2φb
onset of inversion(surface is undoped)
φb
φs
M O S
φs = 0
onset of strong inversion(VT condition)
φsφs
φb
φsVT
M O S
φs = -φb
inversionlayer
VT = VFB + 2φb +Qdep
Cox
offset bulk drop
oxide drop
EC
EV
Ei
flatband(no field in silicon)
φbφs
EF
EF
siliconsurface
M O S
φs = φb
φb = lnNA
ni
kBTq
Slide 7Loke, Wee & PfiesterAgilent Technologies
Reintroducing (…drum roll…) the MOSFET
VGS > VTVDS > 0 (net source-to-drain current flow)Carriers easily overcome source barrierSurface is strongly inverted
VGS ≈ VTVDS = 0 (no net current flow)Source barrier is loweredSurface is inverted
VGS = 0VDS = 0 (no net current flow)Large source barrier(back-to-back diodes)
electronelectroncurrentcurrent
Source: Sze (1981)
Slide 8Loke, Wee & PfiesterAgilent Technologies
Life’s Never So Perfect
Ideal
IDS
VDS
Reality
Now plunging deep into a lot of interesting second-order effects…
IDS
VDS
VGS
VGS
Ideal MOSFET = voltage-controlled current source
Slide 9Loke, Wee & PfiesterAgilent Technologies
Warp Speed Ahead ���� Short-Channel Effect (SCE)
• Prominent in older CMOS technologies• How to minimize SCE?
• Minimize volume of charge depleted by source/drain junctions• Higher substrate doping for thinner junction depletion regions (xdep ∝∝∝∝1/ N )
• Higher VT & junction capacitance ���� not consistent with scaling• Shallower source/drain junctions
Etch silicon around active area –profile critical to minimize stress
Grow liner SiO2, then deposit conformal SiO2 – void-free deposition is critical
CMP excess SiO2
Strip Si3N4 polish stop
etched away in subsequent oxide cleans
Slide 15Loke, Wee & PfiesterAgilent Technologies
Let’s Think a Little Bit More About CMP
• Ideal world for CMP: want perfectperiodicity of patterns throughout wafer
• Need to throw in dummy features to minimize pattern density variations � optimize planarity
• Polishing pad will flex
oxide CMP
dishing
wafer carrierin situ pad conditioner
(critical)
polishing table
polishingpad
wafer(facing down)
slurry
opticalendpointdetection
CMP technology pioneered by IBM• Leveraged expertise from lens polishing
Slide 16Loke, Wee & PfiesterAgilent Technologies
Always Think Dummies in Any CMP Process• Dummification is key to minimize topography in any CMP process• Add dummy patterns to open spaces to minimize layout density variations
→ Added design complexity to check layout density & insert dummy patterns
• Also critical to step dummy dies along wafer circumference
Slide 17Loke, Wee & PfiesterAgilent Technologies
Well Implants – Lots of Transistor Variants• core vs. I/O FET’s, core low-/nom-/high-VT variants, native vs. implanted
Coren-well
Coren-well
Corep-well
I/On-well
Coren-well
Corep-well
I/On-well
I/Op-well
Corenative
I/Onative
Coren-well
Corep-well
free lunch!!!
Slide 18Loke, Wee & PfiesterAgilent Technologies
Well Engineering
Retrograded well dopant profile(implants before poly deposition)
p-well
Depth
SubstrateDoping
Deeper subsurface implant• Extra dopants to prevent subsurface
punchthrough under halos• Prevent parasitic channel formation on
active sidewall beneath source/drain• Faster diffusers OK (B, As/P)
Very deep high-dose implant• Latchup prevention• Noise immunity• Faster diffusers OK (B, As/P)
STIoxide
STIoxide
Implant order matters to prevent ion channeling, especially for the shallow implant
Slide 19Loke, Wee & PfiesterAgilent Technologies
Gate Oxidation• Need two gate oxide tox’s – thin for core FET’s & thick for I/O FET’s
• Grow 1st oxide, strip oxide for core FET’s, grow 2nd oxide• Gate oxide is really made of silicon oxynitride (SiOxNy)
• N content prevents boron penetration from p+ poly to channel in pFET’s• Side benefit – increased εox
Source: Maex, IMEC (2002)
Subroutine on Equipment Technology• Gate oxide no longer furnace grown• Multi-chamber cluster tools now ubiquitous• Pre-oxidation clean, gate oxidation &
poly/ARL deposition performed in separate chambers without breaking vacuum
• Better thickness & film compositional control (native SiO2 grows instantly when exposed to air)
• Fast – minutes-seconds per wafer vs. hours per wafer batch
TopView
Slide 20Loke, Wee & PfiesterAgilent Technologies
Poly Gate Definition
Si substrate
• Process control is everything – resist & poly etch chamber conditioning is critical (lesson to remember: don’t clean those residues in tea cups or woks)
• Way to get smaller CD’s to trim more (requires tighter control)• Dummification also necessary for poly mask
poly-Si
1 2 3
anti-reflection layer (ARL)
gateoxide
resistresist
Pattern resist Trim resist (oxygen ash)
Etch gate stack
polygate
• Gate CD way smaller than lithography capability, even with mask tricks
Slide 21Loke, Wee & PfiesterAgilent Technologies
Source/Drain & Channel Engineering
Resulting structure has:• Smaller SCE• Shallow junction where needed most• Low junction capacitanceNot to be confused with LDD’s in I/O FET’s• Same process with spacers but Iightly
doped drain (LDD) is used for minimizing peak E fields that cause hot carriers & breakdown
• Extensions need to be heavily doped to minimize series resistance
Different halo & extension/LDD implants for each FET variant
• Reverse short- & narrow-channel effects• Well proximity effect
• Active area mechanical stress effect• Leakage current mechanisms• Multiple VT devices• Impact of halos• Manufacturability
Slide 26Loke, Wee & PfiesterAgilent Technologies
Poly Depletion & Surface Charge Centroid Effects
• Increasing discrepancy between electrical & physical gate oxide thicknesses since charges are not intimately in contact with oxide interface ���� Cox not as small
• Cox must account for gate & Si surface charge centroids as well as εεεεSi
• Modeled in BSIM4 ���� more accurate I-V & C-V calculations• Motivation for high-K gate dielectrics & metal/silicided gate technology
Si surface charge centroid few Å’s awayfrom oxide interface
n+ poly gate
p-well
gate oxide
poly depletion (band bending) results from nonzero conductivity
gate charge centroid few Å’s away from oxide interface
Cox = εox / EOT
EOT = Equivalent Oxide Thickness
Source: Wong, IBM (2002)
CCoxox
1.5nm (151.5nm (15ÅÅ))
polypoly--SiSigategate
SiSisubstratesubstrate
gategateoxideoxide
Slide 27Loke, Wee & PfiesterAgilent Technologies
VT Variations Across FET L & W in 90nm
• Wondered why so many transistor L & W bins in SPICE models?• e.g., SPICE model linear VT’s for 90nm nom-VT core nFET @ 85°C
Well Proximity Effect• |VT| ↑↑↑↑ if FET is too close to edge of well resist mask due to
extra channel dopants from lateral scattering off resist sidewall into active area during well implants
• |∆∆∆∆VT| depends on:• FET distance to well mask edge• FET orientation• implanted ion species/energy
• Most impact on narrow- & long-channel devices• No impact on native FET’s• Well mask matching critical especially in analog layout • Not modeled in BSIM4
high-energywell implant
Source: Hook et al., IBM (2003)
nFET0.24/1.0µm
1.0/1.0µm
0.24/0.18µm1.0/0.18µm
pFET
1.0/1.0µm
1.0/0.18µm0.24/0.18µm
0.24/1.0µm
Slide 32Loke, Wee & PfiesterAgilent Technologies
Active Area Mechanical Stress Effect• Silicon is piezoresistive – electrical properties depends on mechanical stress state
• STI ���� compression in Si channel due to 10x CTE mismatch between Si & SiO2
• Idsat’s can change by as much as 10-15% ���� affects digital device ratios• Channel stress is strong function of distance from poly to active edge
• Known for some time• Can play tricks with tensile spacer &
silicide films to relieve channel stress• Basis of high-µn strained-Si technology
• Modeled in BSIM4 not BSIM3 (SA, SB)
high compression lower compression
Source: Xi et al., UC Berkeley (2003)
Slide 33Loke, Wee & PfiesterAgilent Technologies
ON vs. OFF Current Benchmark
• “No free lunch” principle prevails again: high ION � high IOFF
• VT’s not scaling as aggressively as VDD
• Technology providers offer variety of VT’s on same die to concurrently meet high-speed vs. low-leakage needs
Comparison of 90nm Technology Foundry Vendors
1.2V1.0V1.2V1.0V
nFETpFET
0.1
1.0
10.0
100.0
1000.0
0 200 400 600 800 1000 1200
OFF
Lea
kage
Cur
rent
(nA
/µm
)
ON Drive Current (µA/µm)
Slide 34Loke, Wee & PfiesterAgilent Technologies
Leakage Current Contributions
130nm 100nm 65nm
Source: Assenmacher, Infineon (2003)
ISUB Subthreshold leakage from source
IG Gate leakage (direct tunneling)
IGIDL Gate-induced drain leakage (GIDL)
IJ Junction reverse-bias leakage
• Relative contributions of OFF-state leakage
p-well
poly gate
n+ n+
VDD
IG
IGIDL
IJ
ISUB
Slide 35Loke, Wee & PfiesterAgilent Technologies
Subthreshold Conduction• ON vs. OFF current – big issue with VDD & VT scaling
• FET does not abruptly turn on: large ION ���� low VT ���� large IOFF leakage• Diffusion current due to carriers from source spilling over source barrier into channel
due to application of VG to lower φφφφs (weak dependence on VDS in long-channel FET)
• Want to maximize coupling of VG to φφφφs but have capacitive sharing with substrate• Large Cox ���� high-K gate dielectrics, thinner gate oxides• Small CSi ���� low substrate doping, fully-depleted SOI• Inverse subthreshold slope (S) ≈≈≈≈ 100mV/decade at 300K (ideally 60mV/decade)
• e.g., VT=0.2V & ION= 100µA ���� IOFF=1µA !!!
∆φs = ∆VG ×Cox
Cox + CSi
Silicon surfacePotential (φs)
Coxgate oxide
capacitance
CSisilicon
depletion capacitance
p-substrate
gate
VG
VB
S = ln(10) ×Cox + CSi
Cox
kBTq
source
drainVG
Slide 36Loke, Wee & PfiesterAgilent Technologies
Basic Intuition on Body Effect• Body or backgate effect
• Tug-o-war between VG & VB to control surface potential through Cox & Csi
• Inversion layer forms when φs is lowered sufficiently with respect to source (that’s where carriers come from)
• Csi decreases with increasing |VB|
• Steeper subthreshold slope with body effect – only valid for long channel
Silicon surfacePotential (φs)
Coxgate oxide
capacitance
CSisilicon
depletion capacitance
p-substrate
gate
VG
VB
Slide 37Loke, Wee & PfiesterAgilent Technologies
p-well
poly gate
n+ n+
VDD
Drain-Induced Barrier Lowering (DIBL)• Soft punchthrough induced by drain-to-substrate depletion region
• |VT | ↓ as VD ↑ (drain-induced SCE)• VD ↑ � drain-to-substrate depletion region grows with more reverse bias• Lateral electric fields in drain-induced depletion region lowers source-to-
channel barrier, allowing more carriers to diffuse from source to channel
• Typical DIBL magnitude: ∆VT = –0.12V for ∆VD = +1.2V in 90nm
reduction of electron barrier height in conduction band (CB)
at edge of source
CB
VDD
source drain
p-well
poly gate
n+n+
Slide 38Loke, Wee & PfiesterAgilent Technologies
Gate-Induced Drain Leakage (GIDL)• Drain-to-substrate leakage due to band-to-band tunneling current in
very high-field depletion region in drain overlap region
• Similar gate-induced source leakage (GISL) mechanism exists when source is raised above gate potential
• Modeled in BSIM4 not BSIM3
p-well
poly gate
n+ drainhalo
VDD
poly gate
gateoxide E-field & band bending
are strong functions of VGD& weak function of VDB
drain
Slide 39Loke, Wee & PfiesterAgilent Technologies
Gate Leakage (Direct Tunneling)
Historical Trends
Source: Taur, IBM (2002)
• tox has been scaling aggressively with Lmin
• higher IFET
• tighter gate control � less SCE• Significant direct tunneling for tox < 2nm• Gate leakage = f (tox, VG)
• Tunneling probability ∝ exp (-α tox)• VG dependence from Fermi-Dirac statistics
& density-of-states considerations• Hole & electron tunneling in CB & VB• High-K gate dielectric achieves same COX with
much thicker tox
• Modeled in BSIM4 not BSIM3
Slide 40Loke, Wee & PfiesterAgilent Technologies
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.1 1 101
Line
ar V
T at 8
5o C (V
)
L, Drawn Channel Length (µm)
high-VT
nom-VT
low-VT
low-VT
nom-VT
high-VT
pFET
nFET
Using FET’s with Multiple VT’s• Be very careful when using multiple-VT FET’s, especially in analog land
• VT separation typically advertised only for L ≈ Lmin
long L
no ∆VT between low-VT & nom-VT
devices
• Different mechanisms for setting VT in low-VT vs. high-VT devices• Want to share as many implant masks as possible to save $$$• VT adjustment: channel implant vs. halo implant
short L
∆VT ≈ 0.1V between devices
∆VT’s
∆VT’s
Simulated 90nm Core FET VT’s (W=0.6µm)
Slide 41Loke, Wee & PfiesterAgilent Technologies
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
-40 -20 0 20 40 60 80 100 120 140 160Li
near
VT (V
)
Temperature (C)
high-VT
nom-VT
low-VT
low-VT
nom-VT
high-VT
pFET
nFET -0.82mV/C
-0.67mV/C
-0.55mV/C
-0.88mV/C
-1.04mV/C-1.08mV/C
VT vs. Temperature
• |VT| ↓ as T ↑• T ↑� Eg ↓� ni ↑� φb ↓ for constant NA� |VT| ↓
• VT can vary a lot with temperature
• Worse IOFF due to |VT| ↓ & S ↑• Temperature sensitivity depends on W & L
• Analog implication: With VT becoming increasing % VGS given reduced VDD, cold temperatures may yield worst headroom
φb = lnNA
ni
kBTq
Simulated Linear VT for 0.6/0.1µm Core FET’s
Slide 42Loke, Wee & PfiesterAgilent Technologies
Impact of Halos on Analog Design• Halo at source side suppresses SCE & DIBL in short-channel devices
• Halo at drain side creates Drain-Induced Threshold Shift (DITS) in long-channel devices• Drain bias very effective in modulating drain halo barrier ���� VT ↓↓↓↓ ���� Ids ↑↑↑↑• Worse DIBL compared to uniform-doped FET• Can degrade FET rout by 10-100x!!!• Critical limitation for building current sources
(cascoding difficult with low VDD)• Asymmetric FET’s with only source-side halo
shown to improve rout significantly
• Halos increase Cgb when FET is not in inversion• Modeled in BSIM4 not BSIM3, but still need improvement
Source: Cao et al., UC Berkeley (1999)
halo
uniform-doped
CB
VD
source drain
Slide 43Loke, Wee & PfiesterAgilent Technologies
Characterizing Process Variations• Statistical variations in IC manufacturing � variations in FET characteristics
• Circuits must function across operating VDD & temperature but also across statistically acceptable process tolerances
• Statistical variations summarized by spread in nFET & pFET VT’s, or in Idsat’s, i.e., use VT or Idsat to summarize cumulative effect of ALL process variances
• Elliptical 2-D Gaussian distribution from natural variations with no deliberate retargetting of process parameters
• Tougher to control poly CD than implant doses
1.5
2.0
2.5
3.0
3.5
4.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
10/0.13µm nFET Idsat (mA)
10/0
.13 µ
m p
FET
I dsat (m
A)
3.0 σ2.5 σMeasurements
SPICE Targets
TT
FF
SS
FS
SF
correlated variations due to common processes e.g., poly photo/etch CD & gate oxide thickness
uncorrelated variations due to uncommon processes e.g., channel & well ion implants
Slide 45Loke, Wee & PfiesterAgilent Technologies
Skew Process for Design Margin Verification• Process wafers with Idsat’s that target SPICE corners of acceptable distribution• Statistical distribution is cumulative result of ALL variations for processes
targetted as NOMINAL• Countless possibilities of tweaks to achieve skew nFET/pFET Idsat combination• Fab typically employs SIMPLE means of retargetting nFET & pFET Idsat’s with
very few deliberate non-nominal process tweaks• FF vs. SS
• Adjust poly CD, no change in gate oxide thickness• Nominal implant doses
• FS vs. SF• Adjust surface channel or halo implant dose• Nominal poly CD & gate oxide thickness
• Consequences• Nominal & skew results frequently miss intended targets since nominal (by
definition) can land anywhere in distribution• Not 100% representative of natural process corners• Decent approximation for vanilla digital circuits• May be bad approximation for some analog & high-speed digital circuits if
they are insensitive to selected tweaks
Slide 46Loke, Wee & PfiesterAgilent Technologies
Additional Commentary Manufacturing Impact on Design
• Importance of poly gate orientation – align FET gate along x or y?• Preferred orientation will likely exist due to step-and-scan nature of gate
lithography• FET mismatch
• Symmetric circuits that are built asymmetric may fail • DFM (design for manufacturability) is a big buzz word now
� need for Monte Carlo simulations to statistically validate design• Exposure λ is not scaling as aggressively as Lmin
• Roadmaps are just guidelines• Huge industry resistance to move to 157nm
• Requires reflective optics � $$$• Expect more gate resist trimming & relatively worse CD/overlay control
at 65nm node• Whole business of minimum vs. recommended design rules
• Who is willing to design let alone pay for poor yield?• Statistical design considerations & layout engineering becoming more critical
than ever
Slide 47Loke, Wee & PfiesterAgilent Technologies
Conclusions• CMOS scaling continues to be driven by digital circuit needs
• Should expect incremental changes in 65nm CMOS technology• Hopefully no major surprises
• Increasing mechanical engineering opportunities in IC technology
• Always a time lag for SPICE models to account for new effects• Pressing issue since tapeout mistakes are costlier than ever • Need to work closely with technology providers to quickly find
out about these new effects• Account for them or avoid them!!!
• Statistical design & layout considerations more critical than ever
• Analog designers have to keep living with what they get from digital • Designers with intimate knowledge of technology constraints
will be best positioned to avoid pitfalls & to turn bugs into features
• Could you think of a better time to be doing design? �
Slide 48Loke, Wee & PfiesterAgilent Technologies
References• T. B. Hook et al., “Lateral Ion Implant Straggle and Mask Proximity Effect,” IEEE Trans. Electron
Devices, vol. 50, no. 9, pp. 1946-1951, Sept. 2003.• J. Assenmacher, “BSIM4 Modeling and Parameter Extraction,” Technical Univ. Berlin Analog
Integrated Circuits Workshop, Mar. 2003. • X. Xi et al., BSIM4.3.0 MOSFET Model – User’s Manual, The Regents of the University of California
at Berkeley, 2003.• International Technology Roadmap for Semiconductors, Front End Processes (2003 Edition), 2003.• H.-S. P. Wong, “Beyond the Conventional Transistor,” IBM Journal of Research & Development, vol.
46, no. 2/3, pp. 133-168, Mar. 2002.• Y. Taur, “CMOS Design Near the Limit of Scaling,” IBM Journal of Research & Development, vol.
46, no. 2/3, pp. 213-222, Mar. 2002.• C. R. Cleavelin, “Front End Manufacturing Technology,” IEEE IEDM Short Course on The Future of
Semiconductor Manufacturing, Dec. 2002.• D. Harame, “RF Device Technologies,” IEEE IEDM Short Course on RF Circuit Design for
Communication Systems, Dec. 2002.• S. Thompson et al., “A 90nm Logic Technology Featuring 50nm Strained Silicon Channel
Transistors, 7 Levels of Cu Interconnect, Low k ILD, and 1µm2 SRAM Cell,” IEEE IEDM Tech. Digest, pp. 61-64, Dec. 2002.
• C. C. Wu et al., “A 90nm CMOS Device Technology with High-Speed , General-Purpose, and Low-Leakage Transistors for System on Chip Applications,” IEEE IEDM Tech. Digest, pp. 65-68, Dec. 2002.
Slide 49Loke, Wee & PfiesterAgilent Technologies
References (cont’d)• R. Rios et al., “A Three-Transistor Threshold Voltage Model for Halo Processes,” IEEE IEDM Tech.
Digest, pp. 113-116, Dec. 2002.• R.A. Bianchi et al., “Accurate Modeling of Trench Isolation Induced Mechanical Stress Effects on
MOSFET Electrical Performance,” IEEE IEDM Tech. Digest, pp. 117-120, Dec. 2002.• B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.• J. D. Plummer et al., Silicon VLSI Technology– Fundamentals, Practice and Modeling, Prentice-Hall,
2000.• K. M. Cao et al., “Modeling of Pocket Implanted MOSFETs for Anomalous Analog Behavior,” IEEE
IEDM Tech. Digest, pp. 171-120, Dec. 1999.• A. Chatterjee et al., “Transistor Design Issues in Integrating Analog Functions with High
Performance Digital CMOS,” IEEE Symp. VLSI Technology Tech. Digest, pp. 147-148, June 1999.• T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press,
1998.• D. P. Foty, MOSFET Modeling with SPICE: Principles and Practice, Prentice-Hall, 1996.• A. Beiser, Concepts in modern Physics (4th ed.), McGraw-Hill, 1987.• S.M. Sze, Physics of Semiconductor Devices (2nd ed.), John Wiley & Sons, 1981.