Introduction to CMOS VLSI Design Instructed by Shmuel Wimer Bar-Ilan University, Engineering Faculty Technion, EE Faculty Credits: David Harris Harvey Mudd College (Some materials copied/taken/adapted from Harris’ lecture notes)
Dec 30, 2015
Introduction to CMOS VLSI Design
Instructed by Shmuel WimerBar-Ilan University, Engineering Faculty
Technion, EE Faculty
Credits: David HarrisHarvey Mudd College
(Some materials copied/taken/adapted from Harris’ lecture notes)
CMOS VLSI Design 2Oct 2010
Course Topics
Introduction to CMOS circuits
MOS transistor theory, processing technology
CMOS circuit and logic design
System design methods
CAD algorithms for backend design
Case studies, CAD tools, etc.
CMOS VLSI Design 3Oct 2010
Bibliography Textbook
– Weste and Harris. CMOS VLSI Design(3rd edition)• Addison Wesley• ISBN: 0-321-14901-7• Available at
amazon.com.
CMOS VLSI Design 4Oct 2010
Introduction
Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors Introduction: How to build your own simple CMOS
chip– CMOS transistors– Building logic gates from transistors– Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
CMOS VLSI Design 5Oct 2010
A Brief History 1958: First integrated circuit
– Flip-flop using two transistors– Built by Jack Kilby at Texas Instruments
2003– Intel Pentium 4 processor (55 million transistors)– 512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years– No other technology has grown so fast so long
Driven by miniaturization of transistors– Smaller is cheaper, faster, lower in power!– Revolutionary effects on society
CMOS VLSI Design 6Oct 2010
Annual Sales
1018 transistors manufactured in 2003– 100 million for every human on the planet
0
50
100
150
200
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002
Year
Global S
emiconductor B
illings(B
illions of US
$)
CMOS VLSI Design 7Oct 2010
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable
1947: first point contact transistor– John Bardeen and Walter Brattain at Bell Labs– Read Crystal Fire
by Riordan, Hoddeson
CMOS VLSI Design 8Oct 2010
Transistor Types
Bipolar transistors– npn or pnp silicon structure– Small current into very thin base layer controls
large currents between emitter and collector– Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors– nMOS and pMOS MOSFETS– Voltage applied to insulated gate controls current
between source and drain– Low power allows very high integration
CMOS VLSI Design 9Oct 2010
1970’s processes usually had only nMOS transistors– Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
CMOS VLSI Design 10Oct 2010
Moore’s Law
1965: Gordon Moore plotted transistor on each chip– Fit straight line on semilog scale– Transistor counts have doubled every 26 months
Year
Transistors
40048008
8080
8086
80286Intel386
Intel486Pentium
Pentium ProPentium II
Pentium IIIPentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
CMOS VLSI Design 11Oct 2010
CMOS VLSI Design 12Oct 2010
CMOS VLSI Design 13Oct 2010
CMOS VLSI Design 14Oct 2010
Corollaries
Many other factors grow exponentially – Ex: clock frequency, processor performance
Year
1
10
100
1,000
10,000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro/II/III
Pentium 4
Clock S
peed (MH
z)
CMOS VLSI Design 15Oct 2010
Silicon Lattice
Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors
Si SiSi
Si SiSi
Si SiSi
CMOS VLSI Design 16Oct 2010
Dopants
Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
CMOS VLSI Design 17Oct 2010
p-n Junctions
A junction between p-type and n-type semiconductor forms a diode.
Current flows only in one direction
p-type n-type
anode cathode
CMOS VLSI Design 18Oct 2010
nMOS Transistor
Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS) capacitor
– Even though gate is
no longer made of metal
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
CMOS VLSI Design 19Oct 2010
nMOS Operation
Body is commonly tied to ground (0 V) When the gate is at a low voltage:
– P-type body is at low voltage– Source-body and drain-body diodes are OFF– No current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
0
S
CMOS VLSI Design 20Oct 2010
nMOS Operation Cont.
When the gate is at a high voltage:– Positive charge on gate of MOS capacitor– Negative charge attracted to body– Inverts a channel under gate to n-type– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
1
S
CMOS VLSI Design 21Oct 2010
pMOS Transistor
Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON– Gate high: transistor OFF– Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
CMOS VLSI Design 22Oct 2010
Power Supply Voltage
GND = 0 V In 1980’s, VDD = 5V
VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
CMOS VLSI Design 23Oct 2010
Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF ON
ON OFF
CMOS VLSI Design 24Oct 2010
CMOS Inverter
A Y
0
1
VDD
A Y
GNDA Y
CMOS VLSI Design 25Oct 2010
CMOS Inverter
A Y
0
1 0
VDD
A=1 Y=0
GND
ON
OFF
A Y
CMOS VLSI Design 26Oct 2010
CMOS Inverter
A Y
0 1
1 0
VDD
A=0 Y=1
GND
OFF
ON
A Y
CMOS VLSI Design 27Oct 2010
CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1
A
B
Y
CMOS VLSI Design 28Oct 2010
CMOS NAND Gate
A B Y
0 0 1
0 1
1 0
1 1
A=0
B=0
Y=1
OFF
ON ON
OFF
CMOS VLSI Design 29Oct 2010
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0
1 1
A=0
B=1
Y=1
OFF
OFF ON
ON
CMOS VLSI Design 30Oct 2010
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1
A=1
B=0
Y=1
ON
ON OFF
OFF
CMOS VLSI Design 31Oct 2010
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A=1
B=1
Y=0
ON
OFF OFF
ON
CMOS VLSI Design 32Oct 2010
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
BY
CMOS VLSI Design 33Oct 2010
3-input NAND Gate
Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0
A
B
Y
C
CMOS VLSI Design 34Oct 2010
Compound Gates
Compound gates can do any inverting function Ex: (AND-AND-OR-INVERT, AOI22)Y A B C D
A
B
C
D
A
B
C
D
A B C DA B
C D
B
D
YA
CA
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
CMOS VLSI Design 35Oct 2010
Example: O3AI
Y A B C D
A B
Y
C
D
DC
B
A
CMOS VLSI Design 36Oct 2010
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or
etched Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing process
CMOS VLSI Design 37Oct 2010
Inverter Cross-section
Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
YGND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
CMOS VLSI Design 38Oct 2010
Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection (used for Schottky Diode)
Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
YGND VDD
n+p+
substrate tap well tap
n+ p+
CMOS VLSI Design 39Oct 2010
Inverter Mask Set
Transistors and wires are defined by masks Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tapnMOS transistor pMOS transistor
CMOS VLSI Design 40Oct 2010
CMOS VLSI Design 41Oct 2010
Detailed Mask Views
Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
CMOS VLSI Design 42Oct 2010
Fabrication Steps
Start with blank wafer Build inverter from the bottom up First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate
CMOS VLSI Design 43Oct 2010
Oxidation
Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2
CMOS VLSI Design 44Oct 2010
Photoresist
Spin on photoresist– Photoresist is a light-sensitive organic polymer– Softens where exposed to light
p substrate
SiO2
Photoresist
CMOS VLSI Design 45Oct 2010
Lithography
Expose photoresist through n-well mask Strip off exposed photoresist
p substrate
SiO2
Photoresist
CMOS VLSI Design 46Oct 2010
Etch
Etch oxide with hydrofluoric acid (HF)– Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist
CMOS VLSI Design 47Oct 2010
Strip Photoresist
Strip off remaining photoresist– Use mixture of acids called piranha etch
Necessary so resist doesn’t melt in next step
p substrate
SiO2
CMOS VLSI Design 48Oct 2010
n-well
n-well is formed with diffusion or ion implantation Diffusion
– Place wafer in furnace with arsenic gas– Heat until As atoms diffuse into exposed Si
Ion Implanatation– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
n well
SiO2
CMOS VLSI Design 49Oct 2010
Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps
p substraten well
CMOS VLSI Design 50Oct 2010
Polysilicon
Deposit very thin layer of gate oxide– < 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon– Heavily doped to be good conductor
Thin gate oxidePolysilicon
p substraten well
CMOS VLSI Design 51Oct 2010
Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxidePolysilicon
n well
CMOS VLSI Design 52Oct 2010
N-diffusion
Use oxide and masking to expose where n+ dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact
p substraten well
CMOS VLSI Design 53Oct 2010
N-diffusion (cont.)
Pattern oxide and form n+ regions
p substraten well
n+ Diffusion
CMOS VLSI Design 54Oct 2010
N-diffusion (cont.)
Historically dopants were diffused Usually ion implantation today But regions are still called diffusion
n wellp substrate
n+n+ n+
CMOS VLSI Design 55Oct 2010
N-diffusion (cont.)
Strip off oxide to complete patterning step
n wellp substrate
n+n+ n+
CMOS VLSI Design 56Oct 2010
P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
CMOS VLSI Design 57Oct 2010
Contacts
Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
CMOS VLSI Design 58Oct 2010
Metalization
Sputter on copper / aluminum over whole wafer Pattern to remove excess metal, leaving wires
p substrate
MetalThick field oxide
n well
n+n+ n+p+p+p+
Metal
CMOS VLSI Design 59Oct 2010
Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power) Feature size f = distance between source and drain
– Set by minimum width of polysilicon Feature size scales ~X0.7 every 2 years both lateral
and vertical– Moore’s law
Normalize feature size when describing design rules Express rules in terms of = f/2
– E.g. = 0.3 m in 0.6 m process Today’s = 0.01 m (10 nanometer = 10-8 meter)
CMOS VLSI Design 60Oct 2010
Simplified Design Rules
Conservative rules to get you started
CMOS VLSI Design 61Oct 2010
Inverter Layout
Transistor dimensions specified as Width / Length– Minimum size is 4 / 2sometimes called 1 unit– In f = 0.01 m process, this is 0.04 m wide, 0.02
m long
CMOS VLSI Design 62Oct 2010
Summary
MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start
designing schematics and layout for a simple circuit!