VLSI Design 1 Introduction to CMOS VLSI Design Randy E. Saputra Prodi S1 Sistem Komputer Fakultas Teknik Eletro Credits: David Harris Harvey Mudd College (Some materials copied/taken/adapted from Harris’ lecture notes)
VLSI Design 1
Introduction to CMOS
VLSI Design
Randy E. Saputra Prodi S1 Sistem Komputer
Fakultas Teknik Eletro
Credits: David Harris
Harvey Mudd College
(Some materials copied/taken/adapted from Harris’ lecture notes)
VLSI Design 2
Course Topics
Introduction to CMOS circuits
MOS transistor theory, processing technology
CMOS circuit and logic design
System design methods
CAD algorithms for backend design
Case studies, CAD tools, etc.
VLSI Design 3
Bibliography
Textbook
– Weste and Harris.
CMOS VLSI Design (3rd edition)
• Addison Wesley
• ISBN: 0-321-14901-7
• Available at
amazon.com.
VLSI Design 4
Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors
Introduction: How to build your own simple CMOS
chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
VLSI Design 5
A Brief History
1958: First integrated circuit
– Flip-flop using two transistors
– Built by Jack Kilby at Texas Instruments
2003
– Intel Pentium 4 mprocessor (55 million transistors)
– 512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years
– No other technology has grown so fast so long
Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society
VLSI Design 6
Annual Sales
1018 transistors manufactured in 2003
– 100 million for every human on the planet
0
50
100
150
200
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002
Year
Glo
bal S
em
iconducto
r Billin
gs
(Billio
ns o
f US
$)
VLSI Design 7
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century
Large, expensive, power-hungry, unreliable
1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs
– Read Crystal Fire
by Riordan, Hoddeson
VLSI Design 8
Transistor Types
Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration
VLSI Design 9
1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit mProc
VLSI Design 10
Moore’s Law
1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months
Year
Tra
nsis
tors
40048008
8080
8086
80286Intel386
Intel486Pentium
Pentium ProPentium II
Pentium III
Pentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
VLSI Design 11
VLSI Design 12
VLSI Design 13
VLSI Design 14
Corollaries
Many other factors grow exponentially
– Ex: clock frequency, processor performance
Year
1
10
100
1,000
10,000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro/II/III
Pentium 4
Clo
ck S
peed (M
Hz)
VLSI Design 15
Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
Si SiSi
Si SiSi
Si SiSi
VLSI Design 16
Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
VLSI Design 17
p-n Junctions
A junction between p-type and n-type semiconductor
forms a diode.
Current flows only in one direction
p-type n-type
anode cathode
VLSI Design 18
nMOS Transistor
Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor
– Even though gate is
no longer made of metal
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
VLSI Design 19
nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
VLSI Design 20
nMOS Operation Cont.
When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
VLSI Design 21
pMOS Transistor
Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
VLSI Design 22
Power Supply Voltage
GND = 0 V
In 1980’s, VDD = 5V
VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
VLSI Design 23
Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFFON
ONOFF
VLSI Design 24
CMOS Inverter
A Y
0
1
VDD
A Y
GNDA Y
VLSI Design 25
CMOS Inverter
A Y
0
1 0
VDD
A=1 Y=0
GND
ON
OFF
A Y
VLSI Design 26
CMOS Inverter
A Y
0 1
1 0
VDD
A=0 Y=1
GND
OFF
ON
A Y
VLSI Design 27
CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1
A
B
Y
VLSI Design 28
CMOS NAND Gate
A B Y
0 0 1
0 1
1 0
1 1
A=0
B=0
Y=1
OFF
ON ON
OFF
VLSI Design 29
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0
1 1
A=0
B=1
Y=1
OFF
OFF ON
ON
VLSI Design 30
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1
A=1
B=0
Y=1
ON
ON OFF
OFF
VLSI Design 31
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A=1
B=1
Y=0
ON
OFF OFF
ON
VLSI Design 32
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
BY
VLSI Design 33
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
A
B
Y
C
VLSI Design 34
Compound Gates
Compound gates can do any inverting function
Ex: (AND-AND-OR-INVERT, AOI22)Y A B C D A
B
C
D
A
B
C
D
A B C DA B
C D
B
D
YA
CA
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
VLSI Design 35
Example: O3AI
Y A B C D
A B
Y
C
D
DC
B
A
VLSI Design 36
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process
VLSI Design 37
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
YGND V
DD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
VLSI Design 38
Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection (used for Schottky Diode)
Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
YGND V
DD
n+p+
substrate tap well tap
n+ p+
VLSI Design 39
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
VLSI Design 40
VLSI Design 41
Detailed Mask Views
Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
VLSI Design 42
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate
VLSI Design 43
Oxidation
Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2
VLSI Design 44
Photoresist
Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
p substrate
SiO2
Photoresist
VLSI Design 45
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
p substrate
SiO2
Photoresist
VLSI Design 46
Etch
Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist
VLSI Design 47
Strip Photoresist
Strip off remaining photoresist
– Use mixture of acids called piranha etch
Necessary so resist doesn’t melt in next step
p substrate
SiO2
VLSI Design 48
N-well
n-well is formed with diffusion or ion implantation
Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
n well
SiO2
VLSI Design 49
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
p substrate
n well
VLSI Design 50
Polysilicon
Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substraten well
VLSI Design 51
Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
VLSI Design 52
N-diffusion
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact
p substraten well
VLSI Design 53
N-diffusion (cont.)
Pattern oxide and form n+ regions
p substraten well
n+ Diffusion
VLSI Design 54
N-diffusion (cont.)
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n wellp substrate
n+n+ n+
VLSI Design 55
N-diffusion (cont.)
Strip off oxide to complete patterning step
n wellp substrate
n+n+ n+
VLSI Design 56
P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
VLSI Design 57
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
VLSI Design 58
Metalization
Sputter on copper / aluminum over whole wafer
Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field
oxide
n well
n+n+ n+p+p+p+
Metal
VLSI Design 59
Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
– Set by minimum width of polysilicon
Feature size scales ~X0.7 every 2 years both lateral and vertical
– Moore’s law
Normalize feature size when describing design rules
Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process
Today’s l = 0.01 mm (10 nanometer = 10-8 meter)
VLSI Design 60
Simplified Design Rules
Conservative rules to get you started
VLSI Design 61
Inverter Layout
Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.01 mm process, this is 0.04 mm wide, 0.02
mm long
VLSI Design 62
Summary
MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start
designing schematics and layout for a simple circuit!