Introduction to CMOS VLSI Design Lecture 22: Case Study: Intel Processors David Harris Harvey Mudd College Spring 2004.

Introduction toCMOS VLSI

Design

Lecture 22: Case Study: Intel Processors

David Harris

Harvey Mudd College

Spring 2004

CMOS VLSI Design22: Processor Case Study Slide 2

Outline Evolution of Intel Microprocessors

– Scaling from 4004 to Pentium 4– Courtesy of Intel Museum

CMOS VLSI Design22: Processor Case Study Slide 3

4004 First microprocessor (1971)

– For Busicom calculator Characteristics

– 10 m process– 2300 transistors– 400 – 800 kHz– 4-bit word size– 16-pin DIP package

Masks hand cut from Rubylith– Drawn with color pencils– 1 metal, 1 poly (jumpers)– Diagonal lines (!)

CMOS VLSI Design22: Processor Case Study Slide 4

8008 8-bit follow-on (1972)

– Dumb terminals Characteristics

– 10 m process– 3500 transistors– 500 – 800 kHz– 8-bit word size– 18-pin DIP package

Note 8-bit datapaths– Individual transistors visible

CMOS VLSI Design22: Processor Case Study Slide 5

8080 16-bit address bus (1974)

– Used in Altair computer• (early hobbyist PC)

Characteristics– 6 m process– 4500 transistors– 2 MHz– 8-bit word size– 40-pin DIP package

CMOS VLSI Design22: Processor Case Study Slide 6

8086 / 8088 16-bit processor (1978-9)

– IBM PC and PC XT– Revolutionary products– Introduced x86 ISA

Characteristics– 3 m process– 29k transistors– 5-10 MHz– 16-bit word size– 40-pin DIP package

Microcode ROM

CMOS VLSI Design22: Processor Case Study Slide 7

80286 Virtual memory (1982)

– IBM PC AT Characteristics

– 1.5 m process– 134k transistors– 6-12 MHz– 16-bit word size– 68-pin PGA

Regular datapaths and

ROMs

Bitslices clearly visible

CMOS VLSI Design22: Processor Case Study Slide 8

80386 32-bit processor (1985)

– Modern x86 ISA Characteristics

– 1.5-1 m process– 275k transistors– 16-33 MHz– 32-bit word size– 100-pin PGA

32-bit datapath,

microcode ROM,

synthesized control

CMOS VLSI Design22: Processor Case Study Slide 9

80486 Pipelining (1989)

– Floating point unit– 8 KB cache

Characteristics– 1-0.6 m process– 1.2M transistors– 25-100 MHz– 32-bit word size– 168-pin PGA

Cache, Integer datapath,

FPU, microcode,

synthesized control

CMOS VLSI Design22: Processor Case Study Slide 10

Pentium Superscalar (1993)

– 2 instructions per cycle– Separate 8KB I$ & D$

Characteristics– 0.8-0.35 m process– 3.2M transistors– 60-300 MHz– 32-bit word size– 296-pin PGA

Caches, datapath,

FPU, control

CMOS VLSI Design22: Processor Case Study Slide 11

Pentium Pro / II / III Dynamic execution (1995-9)

– 3 micro-ops / cycle– Out of order execution– 16-32 KB I$ & D$– Multimedia instructions– PIII adds 256+ KB L2$

Characteristics– 0.6-0.18 m process– 5.5M-28M transistors– 166-1000 MHz– 32-bit word size– MCM / SECC

CMOS VLSI Design22: Processor Case Study Slide 12

Pentium 4 Deep pipeline (2001)

– Very fast clock– 256-1024 KB L2$

Characteristics– 180 – 90 nm process– 42-125M transistors– 1.4-3.4 GHz– 32-bit word size– 478-pin PGA

Units start to become

invisible on this scale

CMOS VLSI Design22: Processor Case Study Slide 13

Summary 104 increase in transistor count, clock frequency over

30 years!

CMOS VLSI Design22: Processor Case Study Slide 14

Intel Core2 Duo

Slide added by R. Reese

65 nm

L1 Data 32KB

L1 Code 32KB

L2 4MB (shared between both CPUs) – Increased to 6MB in later versions

First Quad cores were two of these in same package.

CMOS VLSI Design22: Processor Case Study Slide 15

IBM Cell ProcessorJointly developed by IBM, Sony, Toshiba – to be used in Playstation 3.

Power Efficient Processor Architecture and The Cell Processor Hofstee, H.P.;High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on12-16 Feb. 2005 Page(s):258 - 262

64b PowerPC core combined with eight Synergistic Processor Elements (SPE)s.

SPEs provide power-efficient execution of digital signal processor (DSP) oriented tasks required in media processors.

Slide added by R. Reese

CMOS VLSI Design22: Processor Case Study Slide 16

Intel Corei7 Quad

Slide added by R. Reese

45 nm

L1 Data 32KB

L1 Code 32KB

L2 256 KB per core

L3 8 MB (shared with all cores)