Introduction to CMOS VLSI Design Circuit Families.

Introduction toCMOS VLSI

Design

Circuit Families

Slide 2CMOS VLSI Design

Outline Pseudo-nMOS Logic Dynamic Logic Pass Transistor Logic


Introduction What makes a circuit fast?

– I = C dV/dt -> tpd (C/I) V

– low capacitance– high current– small swing

Logical effort is proportional to C/I pMOS needs a wider channel

– High capacitance for a given current Can we take the pMOS capacitance off the input? Various circuit families try to do this…

B

A

11

4

4

Y


Pseudo-nMOS In the old days, nMOS processes had no pMOS

– Instead, use pull-up transistor that is always ON In CMOS, use a pMOS that is always ON

– Ratio issue– Make pMOS about ¼ effective strength of

pulldown network

Vout

Vin

16/2

P/2

Ids

load

0 0.3 0.6 0.9 1.2 1.5 1.8

0

0.3

0.6

0.9

1.2

1.5

1.8

P = 24

P = 4

P = 14

Vin

Vout


Pseudo-nMOS Gates Design for unit current on output

to compare with unit inverter. pMOS fights nMOS

Inverter NAND2 NOR2

AY

B

AY

A B

gu =gd =gavg =pu =pd =pavg =

Y



finputs

Y




Inverter NAND2 NOR2

4/3

2/3

AY

8/3

8/3

2/3

B

AY

A B 4/34/3

2/3


Y



finputs

Y




Inverter NAND2 NOR2

4/3

2/3

AY

8/3

8/3

2/3

B

AY

A B 4/34/3

2/3

gu = 4/3gd = 4/9gavg = 8/9pu =pd =pavg =

Y



finputs

Y




Inverter NAND2 NOR2

4/3

2/3

AY

8/3

8/3

2/3

B

AY

A B 4/34/3

2/3

gu = 4/3gd = 4/9gavg = 8/9pu = 6/3pd = 6/9pavg = 12/9

Y



finputs

Y


Pseudo-nMOS Design Ex: Design a k-input AND gate using pseudo-nMOS.

Estimate the delay driving a fanout of H

G = F = P = N = D =

In1

Ink

Y

Pseudo-nMOS1

1 H


Pseudo-nMOS Design Ex: Design a k-input AND gate using pseudo-nMOS.

Estimate the delay driving a fanout of H

G = 1 * 8/9 = 8/9 F = GBH = 8H/9 P = 1 + (4+8k)/9 = (8k+13)/9 N = 2 D = NF1/N + P =

In1

Ink

Y

Pseudo-nMOS1

1 H

4 2 8 13

3 9

H k


Pseudo-nMOS Power Pseudo-nMOS draws power whenever Y = 0

– Called static power P = I•VDD

– A few mA / gate * 1M gates would be a problem– This is why nMOS went extinct!

Use pseudo-nMOS sparingly for wide NORs Turn off pMOS when not in use

A BY

C

en


Dynamic Logic Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate

1

2A Y

4/3

2/3

AY

1

1

AY

Static Pseudo-nMOS Dynamic

Precharge Evaluate

Y

Precharge


The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight.

AY

foot

precharge transistor

Y

inputs

Y

inputs

footed unfooted

f f


Logical Effort

Inverter NAND2 NOR2

1

1

AY

2

2

1

B

AY

A B 11

1

gd =pd =

gd =pd =

gd =pd =

Y

2

1

AY

3

3

1

B

AY

A B 22

1

gd =pd =

gd =pd =

gd =pd =

Y

footed

unfooted

32 2


Logical Effort

Inverter NAND2 NOR2

1

1

AY

2

2

1

B

AY

A B 11

1

gd = 1/3pd = 2/3

gd = 2/3pd = 3/3

gd = 1/3pd = 3/3

Y

2

1

AY

3

3

1

B

AY

A B 22

1

gd = 2/3pd = 3/3

gd = 3/3pd = 4/3

gd = 2/3pd = 5/3

Y

footed

unfooted

32 2


Monotonicity Dynamic gates require monotonically rising inputs

during evaluation A could be from:

– 0 -> 0– 0 -> 1– 1 -> 1– But not 1 -> 0

Precharge Evaluate

Y

Precharge

A

Output should rise but does not

violates monotonicity during evaluation

A


Monotonicity Woes But dynamic gates produce monotonically falling

outputs during evaluation Illegal for one dynamic gate to drive another!

AX

Y

Precharge Evaluate

X

Precharge

A = 1

Y


Monotonicity Woes But dynamic gates produce monotonically falling

outputs during evaluation Illegal for one dynamic gate to drive another!

AX

Y

Precharge Evaluate

X

Precharge

A = 1

Y should rise but cannot

Y

X monotonically falls during evaluation


Domino Gates Follow dynamic stage with inverting static gate

– Dynamic / static pair is called domino gate– Produces monotonic outputs

Precharge Evaluate

W

Precharge

X

Y

Z

A

BC

C

AB

W XY Z =

XZH H

A

W

B C

X Y Z

domino AND

dynamicNAND

staticinverter


Domino Optimizations Each domino gate triggers next one, like a string of

dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic

S0

D0

S1

D1

S2

D2

S3

D3

S4

D4

S5

D5

S6

D6

S7

D7

YH


Dual-Rail Domino Domino only performs noninverting functions:

– AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem

– Takes true and complementary inputs – Produces true and complementary outputs

sig_h sig_l Meaning

0 0 Precharged

0 1 ‘0’

1 0 ‘1’

1 1 invalid

Y_h

f

inputs

Y_l

f


Example: AND/NAND Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B)


Example: AND/NAND Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B) Pulldown networks are conduction complements

Y_h

Y_l

A_h

B_hB_lA_l

= A*B= A*B


Example: XOR/XNOR Sometimes possible to share transistors

Y_h

Y_l

A_l

B_h

= A xor B

B_l

A_hA_lA_h= A xnor B


Leakage Dynamic node floats high during evaluation

– Transistors are leaky (IOFF 0)

– Dynamic value will leak away over time– Formerly milliseconds, now nanoseconds!

Use keeper to hold dynamic node– Must be weak enough not to fight evaluation

A

H

2

2

1 kX

Y

weak keeper


Charge Sharing Dynamic gates suffer from charge sharing

B = 0

AY

x

Cx

CY

A

x

Y



B = 0

AY

x

Cx

CY

A

x

Y

Charge sharing noise

x YV V



B = 0

AY

x

Cx

CY

A

x

Y

Charge sharing noise

Yx Y DD

x Y

CV V V

C C


Secondary Precharge Solution: add secondary precharge transistors

– Typically need to precharge every other node Big load capacitance CY helps as well

B

AY

x

secondaryprechargetransistor


Noise Sensitivity Dynamic gates are very sensitive to noise

– Inputs: VIH Vtn

– Outputs: floating output susceptible noise Noise sources

– Capacitive crosstalk– Charge sharing– Power supply noise– Feedthrough noise– And more!


Domino Summary Domino logic is attractive for high-speed circuits

– 1.5 – 2x faster than static CMOS– But many challenges:

• Monotonicity• Leakage• Charge sharing• Noise

Widely used in high-performance microprocessors


Pass Transistor Circuits Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates

CMOS + Transmission Gates:– 2-input multiplexer– Gates should be restoring

A

B

S

S

S

Y

A

B

S

S

S

Y


LEAP LEAn integration with Pass transistors Get rid of pMOS transistors

– Use weak pMOS feedback to pull fully high– Ratio constraint

B

S

S

AYL


CPL Complementary Pass-transistor Logic

– Dual-rail form of pass transistor logic– Avoids need for ratioed feedback– Optional cross-coupling for rail-to-rail swing

B

S

S

S

S

A

B

AY

YL

L

Introduction to CMOS VLSI Design Circuit Families.

Documents

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pseudonmos design ex

nmos processes

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