Introduction to ARM LPC2148 Microcontroller · –I2C-bus: •Two Fast I2C-bus with 400 kbit/s (I2C0,I2C1) ... •In LPC2148 three types of busses are used to connect the core with

Dr.R.Sundaramurthy.,M.E.,Ph.D., [email protected] of EIE / PEC

Introduction to ARM LPC2148 Microcontroller

Dr.R.SundaramurthyDepartment of EIE

Pondicherry Engineering College

[email protected]


Features of LPC2148 in a Nut Shell• CPU = ARM 7 Core• Word Length = 32 Bit• ROM = 512 KB• RAM = 40KB• 2 Parallel Port (P0,P1 29+16 = 45 GPIO)• 2 Timers (32 Bit) 4 Compare,4 Capture,6 PWM• Interrupts sources = 22• 1 Watch Dog Timer• 1 RTC• 2 ADC (AD0,AD1) 8+6 = 14 Channels (10 Bit)• 1 DAC (10 Bit)

• 2 - I2C-bus, 2 –UARTs, 2-SPI/ SSP, 1 USB


8051 (Vs) LPC2148Feature LPC2148 8051

Word Length 32 Bit 8 Bit

ROM 512 KB 4 KB

RAM 40 KB 128 Bytes

Parallel Port P0,P1 (45 GPIO) P0,P1,P2,P3 (32 GPIO)

2 Timers T0,T1 (32 Bit)Capture, Compare, PWM

T0,T1 (16 Bit)(No Extra Features)

Interrupts sources 22 6

Watch Dog Timer 1 NIL

RTC 1 NIL

ADC 2 (AD0,AD1) 8+6 = 14 channels NIL

DAC 1 NIL

UART 2 1

USB 1 NIL

I2C 2 NIL

SPI 2 NIL


8051 (Vs) LPC2148


Pin Diagram


Important Features of LPC2148


• PACKAGE:

– 32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package with 64 Pins

• MEMORY:

– 40 kB of on-chip static RAM

– 512 kB of on-chip flash program memory.

• SPEED:

– Max speed upto 60 MHz operation.


• ADC

– Two 10-bit A/D converters(AD0 and AD1) provide a total of 14 analog inputs

– conversion times as low as 2.44 μs per channel.

• DAC

– Single 10-bit D/A converter provides variable analog output.


• TIMERS

– Two 32-bit timers/external event counters

– Each timer with four capture and four compare channels

– Six PWM outputs

– 1 Watchdog timer

• RTC

– Low power real-time clock with independent power and dedicated 32 kHz clock input.


• Serial Interfaces:– I2C-bus:

• Two Fast I2C-bus with 400 kbit/s (I2C0,I2C1)

– UART communication:• Two UARTs (UART0,UART1)

– SPI (Serial Peripheral Interface) and SSP(Synchronous Serial Port)

– GPIO:

– Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.


INTERRUPTS:

– Total of 22 interrupt Sources

– Vectored interrupt controller with 16 configurable priorities and vector addresses.

Speed :

60 MHz maximum CPU clock speed from programmable on-chip PLL with settling time of 100 μs.


• OSCILLATOR:

– On-chip integrated oscillator operates with an external crystal in range from 1 MHz to 30 MHz

• Power saving modes:

– Idle mode

– Power-down mode

• CPU operating voltage : Range of 3.0 V to 3.6V

(3.3 V ± 10 %) with 5 V tolerant I/O pads.


Other Features:

• In-System / In-Application Programming (ISP/IAP) via on-chip boot-loader software.

• USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.

• In addition, the LPC2148 provide 8 kB of on-chip RAM accessible to USB by DMA.


Applications of LPC2148

• Industrial control

• Medical systems

• Access control

• Point-of-sale

• Communication gateway

• Embedded soft modem

• General purpose applications


Activating LPC2148 Microcontroller


Power Vdd

51

43

23

Vss

50

42

25

18

6

Pins


Crystal

Main

Crystal

61

62

RTC

Crystal

3

5

Main Crystal

RTC Crystal


Recommended Capacitor Values


Reset Pin (Active Low)


ISP (In system Programming)• To enable ISP mode on the LPC2148, we need to pull the ISP line (P0.14) low and

reset the device.

• If the LPC2148 detects that P0.14 is low after a reset, it will boot into ISP mode, at

which point we can update the device using Flash Magic.

• Then we simply need to remove the ISP jumper and reset the device again to boot

with the newly updated firmware.


P0

P1

P2

P0.8- P0.15

P1.16- P1.23

P1.24- P1.31

LPC2148 Development Board


Activation Circuit

P0

P1

P2

P0.8- P0.15

P1.16- P1.23

P1.24- P1.31


LPC2148 Bus Architecture


Types of Buses

• In LPC2148 three types of busses are used to connect the core with other peripherals on chip.

1. Local Bus to connect the onchip memory controllers and fast GPIO’s

2. Advance High Performance Bus (AHB) for interrupt controller

3. VLSI Peripheral Bus (VPB) for other onchip peripherals.

• AHB acts as a bridge for VPB.

• VPB is mainly meant for connecting slower peripherals with processor.


Bus Architecture


Bus Architecture


Advanced High performance Bus (AHB)

• The ARM7 core is connected to the Advanced High performance Bus (AHB)

• This is the Fastest Bus in ARM7 core.

• Connected to the AHB is the vector interrupt controller and a bridge to a second bus called the VLSI peripheral bus (VPB).

• Since the Interrupt vector controller is responsible for managing all the device interrupt sources, it is connected to the ARM7 core by the fastest bus.


VLSI Peripheral Bus [VPB]

• All the user peripherals are connected to the VPB.

• The VBP bridge contains a clock divider, so the VPB bus can be run at a slower speed than the ARM7 core and the AHB.


Why VPB is operated at Slow Speeds

• For two reasons

• First, we can run the user peripherals at a slower clock rate than the main processor to conserve power.

• Second, it gives Philips the option of adding a slower peripheral to the LPC2000 family without it becoming a bottleneck on the AHB bus.


What is the Optimum speed of VPB

• Currently all the on-chip peripherals are capable of running at 60MHz so the VPB bus can be set to the same speed as the AHB bus.

• It is important to note that after reset the VPB divider is set to divide down the AHB clock by four, so all the on-chip peripherals will

be running at ¼ the CPU clock frequency.


Local Bus

• There is a third local bus which is used to connect the on-chip Flash and RAM to the CPU.

• Connection of the program code and data store to the ARM7 CPU via the AHB bus is possible, but this introduces some execution stalls because of contention on the bus.

• Using a separate local bus removes the possibility of these stalls to give the best processor performance.


Bus Architecture


SFR Programming in ARM

• Each underlying SFR is controlled by three user registers.

• Set register which is used to set bits,

• Clear register which is used to clear bits by writing a logic 1 to the bits you wish to clear

• Status register which is used to read the current contents of the register.

• The most common mistake made when new to the LPC2100 is to write zero into the Clear register

which has no effect.


END OF SESSION

Introduction to ARM LPC2148 Microcontroller · –I2C-bus: •Two Fast I2C-bus with 400 kbit/s (I2C0,I2C1) ... •In LPC2148 three types of busses are used to connect the core with

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