Introduction to Advanced embedded systems course

Embedded Systems-II – IP Cores

Prof. Anish Goel

Contents of ES-II course Section A

Introduction to Intellectual Property (IP) Circuits or Cores, Core examples. Peripherals interfacing with IP Cores. Core based SOC design. Concept and Fundamentals of RTOS essential features, ROS Kernel Function, RTOS examples Lynox, QNX, Neutrino, VRTX, Vx Works.

Section B OS services. Operating Modes. Threads, Context Switching

overheads, Scalability, Embedding with application code.TaskScheduling, Interrupt handling, Inter task communication. Comparison and application of various RTOS.

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Elective Courses offered in this Semester… Low power VSLI design. Video lectures, Seminar’s and Discussion on power reduction

techniques, Short channel effects and SRAM design.

Advanced Computer Architecture.

Embedded Systems –II Everything in the course, ARM Microcontroller, AVR

microcontroller and NIOS-2 and softcores.

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IP CORES An IP (intellectual property) core is a block of logic or

data that is implemented in a field programmable gatearray ( FPGA ) or application-specific integrated circuit (ASIC ) for a product.

Universal Asynchronous Receiver/Transmitter ( UART s),central processing units ( CPU s), Ethernet controllers,and PCI interfaces are all examples of IP cores

IP cores fall into one of three categories: hard cores , firmcores , or soft cores

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IP CORE OVERVIEWTypes of IP Cores and main deliverables

Soft IP Coressynthesisable VHDL or Verilog (54 % of IPs) Firm IP Coresnetlist after synthesis in the target technology (20

% of IPs) Hard IP Cores

layout of the block on chip (GDSII, CIF) (26 % of IPs)

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Types of IP Cores…

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Flexibility and performance

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System IP

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Altera IP Cores Embedded Peripherals IP ■SDRAM Controller Core ■CompactFlash Core ■Common Flash Interface Controller Core ■EPCS Serial Flash Controller Core ■JTAG UART Core ■UART Core ■SPI Core ■Optrex 16207 LCD Controller Core ■PIO Core ■Avalon-ST Serial Peripheral Interface Core ■PCI Lite Core ■Cyclone III Remote Update Controller Core ■MDIO Core

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SDRAM Controller Interface Block Diagram

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SDRAM interface The SDRAM controller core provides Memory-Mapped

interface to off-chip SDRAM. The SDRAM controller allows designers to create

custom systems in an Altera device that connect easily to SDRAM chips.

The SDRAM controller supports standard SDRAM. The SDRAM controller connects to one or more

SDRAM chips, and handles all SDRAM protocol requirements.

The core can access SDRAM subsystems with various data widths (8, 16, 32, or 64 bits), various memory sizes, and multiple chip selects

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Example ConfigurationsSingle 128-Mbit SDRAM Chip with 32-Bit Data

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Example ConfigurationsTwo 64-MBit SDRAM Chips Each with 16-Bit Data

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UART Core

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RS-232 Interface The UART core implements RS-232 asynchronous transmit

and receive logic. The UART core sends and receives serial data via the TXD

and RXD ports. The I/O buffers on most Altera FPGA families do not comply with RS-232 voltage levels, and may be damaged if driven directly by signals from an RS-232 connector.

To comply with RS-232 voltage signaling specifications, an external level-shifting buffer is required (for example, Maxim MAX3237) between the FPGA I/O pins and the external RS-232 connector.

The UART core uses a logic 0 for mark, and a logic 1 for space. An inverter inside the FPGA can be used to reverse the

polarity of any of the RS-232 signals, if necessary.

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Optrex 16207 LCD Controller Core

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LCD interface The Optrex 16207 LCD controller core provides the

hardware interface and software driver required for a Nios II processor to display characters on 6×2-character LCD panel

Eleven signals that connect to pins on the Optrex 16207 LCD panel—These signals are defined in the Optrex16207 data sheet.

■ E—Enable (output)■ RS—Register Select (output)■ R/W—Read or Write (output)■ DB0 through DB7—Data Bus (bidirectional)

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Altera Avalon Interface Specifications Avalon® interfaces simplify system design by allowing you

to easily connect components in an FPGA. The Avalon interface family defines interfaces for use in

both high-speed streaming and memory-mappedapplications.

These standard interfaces are designed into thecomponents available in the SOPC Builder and theMegaWizard® Plug-In Manager.

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Avalon Interfaces in a System Design

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Nios II Processor System

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Nios II Processor Core Block Diagram

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References… Altera Embedded Peripherals IP User Guide Nios II Hardware Development Tutorial Nios II Software Developer’s Handbook Nios II Processor Reference Handbook Avalon Interface Specifications

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